MITEL MT9085AP Datasheet



CMOS

MT9085

PAC - Parallel Access Circuit

Features

• Configurab le for pa rallel-to-s erial o r serial-to-p arallel co nve rsion of 1024 chan nels

• Interfaces to Mitel’s MT9080 Switch Matrix Module (SM X). Gen erat es all fram ing signal s required in 1K or 2K swit ching a pplica tio ns

• Serial da ta rates of 2 . 048 Mbit/s or 4. 0 96 Mbit/s

•Mitel ST-BUS c ompa tible ser ial in puts/ou tpu ts

Applications

• Interfacing the MT9080 Switch Matrix Module to an ST-BUS system

• Rate conve rsio n bet ween 4 M bit/s and 2 Mbit/s serial stream s

• Interfacing a parallel system bus to devices utiliz ing se ria l I/ O

ISSUE 3 January 1993

Ordering Information

MT9085AP 68 Pin PLCC

-40°C to 70°C

Descript ion

The MT9085 Parallel Access Circuit (PAC) provides an interface between an 8 bit, parallel time division multiplexed bus and a serial time division multiplexed bus. A single PAC device will accept data clocked out on the parallel bus of the Mitel MT9080 (SMX) and output it on 32/16 time division multiplexed serial bus streams. A second device can be configured to perform the conversion from the serial format into an SMX compatible parallel format. The time division, serial multiplexed streams may operate at 2.048 Mbit/s or at 4.096 Mbit/s. The PAC generates all framing signals required by the SMX for 1024 and 2048 channel configurations.

S0 S1

S30 S31

P0

•

Shift

Registers

LOAD

C16

C4

Parallel/Serial

Address Decoder

VSS VDD

Timing

Generation

C16 C4

Mode

Control

P7 C4i

F0i C16i

C2o C4o

F0o DFPo

DFPo CFPo

OE MCA MCB CKD

/4S

2

Figure 1 - Functional Block Diagram

2-125

MT9085 CMOS

VSS

S10 S11 S12

S13 VDD VSS

S14

S15

S16

S17

S18

S19

S20

S21

S7S6S5S4S3S2S1S0VSS

987654321

10

S8

11

S9

12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

27

282930313233343536373839404142

S22

S23

S24

S25

VSS

S26

S27

VSS

VDD

VDDP7P6P5P4P3P2

68676665646362

S28

S29

S30

S31

P1

61 60

P0

59

MCB

58

VSS

57

NC

56

C2o

55

C4o

54

DFPo

53

VDD

52

VSS

51

C16i

50

F0i

49

F0o

48

DFPo CFPo

47

IC

46

IC

45

MCA

44

43

OE

C4i

2/4S

CKD

Figure 2 - Pin Connections

2-126

CMOS MT9085

Pin Description

Pin # Name Description

1VSSGround.

2-9 S0-S7 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial

bus streams; input s in serial to parallel mode (MCA= 0), and out puts in parallel to serial mode (MCA=1). Data rate on the serial streams can be selected to be 2.048 Mbit/s (2/4S=0) or 4.096 Mbit/s (2/4S= 1). Refer to Figures 3, 4 and 5 for functiona l timing inform ati on.

10 V

SS

Ground.

11-16 S8-S13 Serial Input/Outputs. See des criptio n for pins 2 - 9 above.

17 V 18 V

Supp ly Inpu t . +5V.

DD

Ground.

SS

19-20 S14-S 15 Serial Input/Outputs. See des criptio n for pins 2 - 9 above. 21-26 S16-S 21 Serial Input/Outputs (TTL compatible with internal pullups). Time division, multiplexed serial

bus streams which are configured as inputs in serial to parallel mode (MCA =0), and outputs in

27 V

parallel to serial mode (MCA =1). Data is clocked at 2.048 Mbit/ s (2 outputs are inactive when the device is configu red for 4.096 Mbit/s operation (2

Ground.

SS

/4S = 0). These input/

/4S=1).

28-33 S22-S 27 Serial Input/Outputs. See des cription for pins 21-26 above.

34 V 35 V

Ground.

SS

Supply In pu t +5V.

DD

36-39 S28-S 31 Serial Input/Outputs. See des cription for pins 21-26 above.

40 CKD Clock Delay (Input). Control input which configures internal device timi ng.

CKD=0 Internal master counter is reset at the system frame boundary established by the

frame pulse (F0i

).

CKD=1 Internal master counter is reset one C16 clock period after system frame boundary.

All data input/output wil l be delayed by one C16 clock period. Timing for data input/output and for OE phase between the frame boundary establi she d by F0i DFPo, DFPo

and CFPo is also affected by the state of the CKD input. See descripti ons

is affected by the level asserted on CKD. The relative

and output signals F0o, C2o, C4o,

pertaining to each specific pin for mo re inform at ion.

41 C4i

42 OE

4.096MHz Clock Input. The 4.096 MHz clock signal must be phase locked to the 16.384 MHz. clock. The falling edge of C4i is used to clock in the frame pulse (F0i

).

Output Enabl e (Input). When low, output data bus (serial or parallel) is actively driven. When set high, the output bus drivers are disabled. In serial to parallel mode, the outputs are disabled immediately after OE

is taken High. See Figures 6 and 21 for timing information

pertaining to parallel t o serial mode .

43 2/4S 2.048/4.096 Mbit/s S ele ct (Inpu t). Selects the data ra te for the time divisio n, multipl exed

serial streams. When tied low, the data rate is 2.048 Mbit/s. When tied high, the dat a rate is

4.096 Mbit/s.

44 MCA Mode Con trol -A (Inp ut). The device will perform a serial to parallel conversion when this

input is tied low. When the input is tied high, the device operates in the parallel to serial m ode.

45 IC Internal Connection. Must be tied to V

for normal device operation.

SS

46 IC Internal Connectio n. Should be left unconnected. 47 CFPo Connect Memo ry Fr am e Pulse (Outpu t). Framing signal wit h a nominal 8 kHz frequency;

goes low 71 (CKD=0) or 68 (CKD=1) C16 clock cycles before the frame boundary establishe d by F0 i

. The signal is used by the connection memory in a typical 1k or 2k switch configuration.

See Figure 15 for timing inform ati o n.

2-127

MT9085 CMOS

Pin Description (continued)

Pin # Name Description

48 DFPo Data Memory Frame Pulse (Output). Framing signal with nominal 4 kHz frequency; changes

state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i This signal is a complement of DFPo by SMXs (MT9080s) making up the Data Memory in a typical 1k or 2k switch configuration.

49 F0o Framing Type 0 Signal (Output). 8 kHz framing signal output by the PAC to indicate the

frame boundary synchronized to C16. This framing signal is aligned with C4o the PAC for use by other devices in a typical switch configuration. Refer to Figures 4 and 5 for functional timing information.

. See Figure 15 for timing information. The signal is used

and is output by

.

50 F0i

51 C16i 16 MHz Clock Input. The 16.384 MHz clock signal input at this pin must be phase-locked to

52 V 53 V 54 DFPo

55 C4o

56 C2o 2.048 MHz Clock Output. This is a 2.048 MHz clock signal derived from the 16 MHz master

57 NC No Connection . 58 V 59 MCB Mode Control-B (Input). This control input performs two different functions, depending on the

Framing Type 0 Signal (TTL compatib le inpu t ). This input signal establishes the frame boundary for the serial input/ou tput streams. The first falling edge of C4i edge of F0i

the 4.096 MHz clock input at C4i Ground.

SS

Supp ly Inpu t. +5V.

DD

Data Memory Frame Pulse (Output). 4 kHz frami ng signal; changes state 64 (CKD=0) or 65 (CKD=1) C16 clock cycles after the frame boundary established by F0i compleme nt of DFPo . See Figure 15. The signal is used by SMXs (MT9080s) making up the Data Mem or y in a typical 2k switch configurat ion.

4.096 MHz Clock Output. This is a 4.096 MHz clock signal derived from t he 16 MHz master clock input at C16. The falling edge of C4o pulse output at F0o

clock input. The rising edge of this clock signal occurs in the middle of the regenerated frame pulse output at F0o

Ground.

SS

state of MCA pin. In parallel to serial mode (MCA=1), MCB def ines which cloc k edge latches in the data. MCB=0 Data on the parallel bus is latched into the device with the every second falling

MCB=1 Data on the parallel bus is latched into the device wit h every alternate posit ive In serial to parallel mode (MCA=0), the MCB pin cont rols the state of the parallel bus d river as

follows: MCB=0 The output drivers are enabled for only half the timeslo t. The data is clocked

MCB=1 The parallel data bus output drivers are enabled for the duration of the channel

establishes the frame boundaries. Refer to Figure 13 for timi ng informat ion .

. See Figure 13 for timing informat ion .

occurs in the middle of the regenerated frame

. Refer to Figures 4 and 5 for functional timing informati on.

. Refer to Figures 4 and 5 for functional timing informat ion.

edge of C16. See Figure 6.

clock edge.

out on the first falling edge within the tim eslot and disabled on the next falling edge. See Figure 7.

timeslot (two C16 Clock Periods). The data is clocked out on the first positive edge within a timeslot and disabled on the last edge.

following the falling

. This signal is a

60-67 P0-P7 Parallel Input/Output Data Bus. This 8 bit data bus is an output in serial to parallel mo de

(MCA=0), and an input in parallel to serial mode (MCA= 1). Dat a is clocked in and out of the port by the C16 clock. The state of the CKD pin det erm ines the relat ive phase of the critical clock edges with respect to the frame pulse. All inputs/outputs have internal pullups. Refer to Figures 6 and 7 for functional timing inform ati on.

68 V

2-128

DD

Supply. +5V.

C4

F0

CMOS MT9085

512 C4 Cycles

S0-S31 2

/4S = 0

S0-S15

/4S = 1

2

C16i

C4o

C2o

F0o

Serial I/O 2 Mbit/s

01 310

01 2 3 630

Figure 3 - Serial Input/Output Functional Timing

Frame Boundary Established by F0i

Ch. 31 Bit 1

Ch. 31 Bit 0

Ch. 0 Bit 7

Ch. 0 Bit 6

Serial I/O 4 Mbit/S

C16i

C4o

C2o

F0o

Serial I/O 2 Mbit/s

Serial I/O 4 Mbit/S

Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5

Figure 4 - Chann el and Frame Alignment (CKD = 0)

Frame Boundary Established by F0i

Ch. 31 Bit 1

Ch. 63 Bit 2 Ch. 63 Bit 1 Ch. 63 Bit 0 Ch. 0 Bit 7 Ch. 0 Bit 6 Ch. 0 Bit 5

Ch. 31 Bit 0

Ch. 0 Bit 7

Ch. 0 Bit 6

Figure 5 - Chann el and Frame Alignment (CKD = 1)

2-129

MT9085 CMOS

A

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Frame Boundary established by F0i

C16i CKD=0

Serial Output S0-S31

Ch. 31, Bit 0 Ch. 1, Bit 7

64 Cycles

Ch. 0, Bit 7

Parallel Input MCB=0

OE

Parallel Input MCB=1

OE

CKD=1

Serial Output S0-S31

Parallel Input MCB=0

OE

Parallel Input MCB=1

A

C0S

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31

AAA

C1S

A

C0S

A

31

A

Ch. 31, Bit 0

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A

C0S

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1

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31

C1S

C0S

C1S

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1

31

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0

C1S

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2

0

1

C1S

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0

C1S

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C1S

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0

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C1S

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2

Ch. 0, Bit 7

C1S

1

C1S

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C

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1S1

C1S

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2

C1S

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2

3

C1S

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C1S

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2

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1S3

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C1S

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3

4

C1S

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3

C1S

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C2S

0

C2S

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0

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1

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C2S

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1

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C

2

Ch. 1, Bit 7

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C2S

0

C2S

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3

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C2S

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0

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1

AAA

OE

Notes: C

- on the parallel inputs indica tes d ata closed in with the edge shown will be clocked out on Seria l Stre am Y, Chann e l X.

XSY

Arrows in the row marked OE

indicate the clock edge which la tche s in the state of the OE pin. CXSY written below the arrow indicates the serial output channel affected by the OE serial output drivers for stream 1 during channel 1.

Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1)

2-130

C1S

1

C1S

2

C1S

3

C1S

4

C2S

1

signal. For example, the level on OE clocked in with edge marked C1S1 will enable or disable the