MITEL MT90826AL, MT90826AG Datasheet

MT90826

Quad Digital Switch

Advanced Information

Features

• 4,096 × 4,096 channel non-blocking switching at 8.192 or 16.384 Mb/s

• Per-channel variable or constant throughput delay

• Accept ST-BUS streams of 2.048Mb/s,

4.096Mb/s, 8.192Mb/s, or 16.384 Mb/s

• Split Rate mode allows mix of two bit rates and rate conversions

• Automatic frame offset delay measurement for ST-BUS input and output streams

• Per-stream frame delay offset programming

• Per-channel high impedance output control

• Bit Error Monitoring on selected ST-BUS input and output channels.

• Per-channel message mode

• Connection memory block programming

• IEEE-1149.1 (JTAG) Test Port

• 3.3V local I/O with 5V tolerant inputs and TTL compatible outputs

Applications

• Medium and large switching platforms

• CTI application

• Voice/data multiplexer

• Digital cross connects

• WAN access system

• Wireless base stations

DS5197 ISSUE 2 June 1999

Ordering Information

MT90826AL 160 Pin MQFP MT90826AG 160 Pin PBGA

-40 to +85 C

Description

The MT90826 Quad Digital Switch has a nonblocking s witch capacity of 4,096 x 4,096 channels at a serial bit rate of 8.192Mb/s or 16.384 Mb/s, 2,048 x 2,048 channels at 4.096Mb/s and 1024 x 1024 channels at 2.048Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control.

The per stream input and output delay control is particularly useful for managing large multi-chip switches with a distributed backplane.

Operating in Split Rate mode allows for switching between two groups of bit rate streams.

STi0/FEi0 STi1/FEi1

•

STi31/FEi31

PLLV

Serial

Parallel

Converter

TDI TDO IC1 RESETTCK TRST

TMS

Test Port

Multiple Buffer

Data Memory

Internal

Registers

Timing

Unit

F0i DS CS R/W A13-A0 DTA D15-D0

CLK

IC3PLLV

DT1 AT1IC2

Microprocessor Interface

Output

MUX

Connection

Memory

Figure 1 - Functional Block Diagram

ODE

Parallel

Serial

Converter

STo0 STo1

•

STo31

MT90826 CMOS Advanced Information

STo16

STo17

STo18

STo20

STo21

STi22/FEi22

STi23/FEi23

VSS

STi21/FEi21

STo19

STi20/FEi20

VDD

VSS

STi18/FEi18

STi19/FEi19

VSS

STi16/FEi16

STi17/FEi17

VSS

VDD

STo15

STo14

STo13

STo12

STi15/FEi15

STi14/FEi14

VSS

STi12/FEi12

STi13/FEi13

VSS

VDD

STo10

STo11

STo9

STo8

VSS

STi10/FEi10

STi11/FEi11

NC STo22 STo23

VSS

VDD STi24/FEi24 STi25/FEi25 STI26/FEi26 STi27/FEi27

VSS STo24 STo25 STo26 STo27

VSS

VDD STi28/FEi28 STi29/FEi29 STi30/FEi30 STi31/FEi31

VSS STo28 STo29 STo30 STo31

VSS

VDD

D0 D1 D2 D3 D4 D5 D6 D7

VSS

VDD

D8 NC NC

121

123

125

127

129

131

133

135

137

139

141

143

145

147

149

151

153

155

157

159

119

117

115

113

109111

107

105

103

160 Pin MQFP

28mm x 28mm

Pin Pitch 0.65mm

101

959799

93 89

87 8385 81

STi9/FEi9 STi8/FEi8 VDD VSS STo7 STo6 STo5 STo4 VSS STi7/FEi7 STi6/FEi6 STi5/FEi5 STi4/FEi4 VDD VSS STo3 STo2 STo1 STo0 VSS STi3/FEi3 STi2/FEi2 STi1/FEi1 STi0/FEi0 ODE VDD VSS CLK PLLVDD PLLGND DT1 AT1 F0i IC3 VSS IC2 RESET IC1 XTM2

D10

D11

D12

D13

D14

D15

DTA

VSS

VDD

171513119 25 27232119753 29 31

VSS

VDD

A10

A11

33 35 37 39

A12

A13

VSS

VDD

TMS

TDI

TDO

TCK

TRST

XTM1

Figure 2 - 160-Pin MQFP Pin Connections

Advanced Information CMOS MT90826

12345678910111213

STi26 STi24 STo20 STi22 STi20 STi18 STi16 STo15 ST013 STo10 STo8 STi10 STi9

STi27 STi25 STo21 STi23 STi21 STi19 STi17 STo14 STo12 STo11 STo9 STi11 STi8

STo26 STo25 STo23 STo19 STo18 STo17

STo22STo24STo27

VDD

STi28 NCSTi30

STi29 NCSTi31

STo28 STo29

STo30 STo31 D2

D1 D3

D5 D6

D10

D13

D9D8

D11

D14

D12

D15NCR/W

GND

VDD

GND

VDD

GND

VDD

GND

GND GNDGNDGNDGND

DTA CS A0 A3 A8A7 A11 TDI TRST

A1DS A2 A4 A5 A6 TMS

TOP VIEW

VDDVDDVDDGND

A10

STi13

STi14

VDDVDDVDDVDDVDDGND GND

VDD

GNDGNDGNDGND

VDD

GND

VDD

GND

VDD

PLLVDD

PLLGND

A12 A13

STo2

STo1 STi4STi5

STo0

XTM2

DT1

XTM1

IC1

STo5

STo7STi12STi15STo16

STo4

STo6STo3

STi6STi7

STi3

STi2

STi0STi1

ODEAT1

CLKF0i

IC2 IC3

RESET

TDO TCK

1 - A1 corner is identiﬁed by metallized markings.

23mm x 23mm

Ball Pitch 1.5mm

Figure 3 - 160-Pin PBGA Pin Connections

Pin Description

Pin # MQFP Pin # PBGA Name Description

12,22,33,54,

66,77,90,101,

112,125,136,

147,157

11,21,32,45, 53,60,65,71,

76,84,89,95, 100,106,111, 117,124,130, 135,141,146,

156

D5,D6,D7,D8,D9,

E4,E10,F4,

F10,G4,G10,

H4,J4,J10,K5,

K6,K7

D4,D10,E5,E6,E7

E8,E9,F5,F9,G5,

G9,H5,H9,H10,J5

J6,J7,J8,J9,K4

+3.3 Volt Power Supply

Ground

MT90826 CMOS Advanced Information

Pin Description (continued)

Pin # MQFP Pin # PBGA Name Description

34 N11 TMS Test Mode Select (3.3V Input with Internal pull-up):

JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up when not driven.

35 M11 TDI Test Serial Data In (3.3V Input with Internal pull-up):

JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven.

36 N12 TDO Test Serial Data Out (3.3V Output): JTAG serial data is

output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.

37 N13 TCK Test Cloc k (5V Tolerant Input): Provides the clock to the

JTAG test logic.

38 M12 TRST Test Reset (3.3V Input with internal pull-up):

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed low on power-up, or held low, to ensure that the device is in the normal functional mode.

40 K11 XTM1 PLL Test Access 1 (3.3V Input): Use for PLL testing

only. No connect for normal operation.

41 J11 XTM2 PLL Test Access 1 (3.3V Input): Use for PLL testing

only. No connect for normal operation.

42 L11 IC1 Internal Connection 1 (3.3V Input with internal pull-

down): Connect to VSS for normal operation.

43 M13 RESET Device Reset (5V Tolerant Input): This input (active

LOW) puts the device in its reset state which clears the device internal counters and registers.

44 L12 IC2 Internal Connection 2 (3.3V Input with internal pull-

down): Connect to VSS for normal operation. When IC3 pin is tied to 3.3V, this pin is used as the PLL bypass clock input for PLL testing only.

46 L13 IC3 Internal Connection 3 (3.3V Input with internal pull-

down): Connect to VSS for normal operation. When this pin is tied to 3.3V, it enables the PLL bypass mode for PLL testing only.

47 K12 F0i Master Frame Pulse (5V Tolerant Input): This input

accepts a 60ns wide negative frame pulse.

48 J12 AT1 Analog Test Access (Bidirectional):Use for PLL testing

only. No connect for normal operation.

49 H11 DT1 Digital Test Access Output (Output): Use for PLL

testing only. No connect for normal operation. 50 K10 PLLGND Phase Lock Loop Ground. 51 K9 PLLVDD Phase Lock Loop Power Supply: 3.3V

Advanced Information CMOS MT90826

Pin Description (continued)

Pin # MQFP Pin # PBGA Name Description

52 K13 CLK Master Clock (5V Tolerant Input): Serial clock for

shifting data in/out on the serial streams. This pin accepts a clock frequency of 8.192MHz or 16.384 MHz. The CPLL bit in the control register determines the usage of the clock frequency. See Table 6 for details.

55 J13 ODE Output Drive Enable (5V Tolerant Input): This is the

output-enable control pin for the STo0 to STo31 serial outputs. See Table 2 for details.

56 57 58

59 67-70 78,79 82,83 91-94

102-105 113-116 126-129 137-140

61-64 72-75 85-88 96-99

107-110 118,119 122,123 131-134 142-145

148-153 154,155

158

3-7 8,9

H13 H12 G13 G12

F13,F12,E13,E12

B13,A13 A12,B12

C11,C10,C9,C8

A7,B7,A6,B6 A5,B5,A4,B4 A2,B2,A1,B1

E2,F2,E1,F1

G11,F11,E11,D11

D13,C13,D12,C12

A11,B11,A10,B10

B9,A9,B8,A8

C7,C6,C5,C4

A3,B3

D3,C3 D2,C2,C1,D1 G1,G2,H1,H2

G3,J1,H3,J2,J3,K1,

K2,K3

L2,M1,M2,M3,N1,

N2,N3

STi0/FEi0,

STi1/FEi1 STi2/FEi2

STi3/FEi3 STi4-7/FEi4-7 STi8-9/FEi8-9

STi10-11/FEi10-11 STi12-15/FEi12-15 STi16-19/FEi16-19 STi20-23/FEi20-23 STi24-27/FEi24-27 STi28-31/FEi28-31

STo0 - 3 STo4 - 7

STo8 - 11

STo12 - 15

STo16 - 19 STo20, STo21 STo22, STo23

STo24 - 27

STo28 - 31

D0 - 5, D6,D7

D9 - 13

D14,D15

Serial Input Streams 0 to 31 and Frame Evaluation Inputs 0 to 31 (5V Tolerant Inputs): Serial data input

streams. These streams may have data rates of 2.048,

4.096, 8.192 or 16.384 Mb/s, depending upon the value programmed at bits DR0 - DR2 in the control register. In the frame evaluation mode, they are used as the frame evaluation inputs.

ST-BUS Output 0 to 31 (Three-state Outputs). Serial data output streams. These streams may have data rates of 2.048, 4.096, 8.192, or 16.384 Mb/s, depending upon the value programmed at bits DR0 - DR2 in the control register.

Data Bus 0 -15 (5V Tolerant I/O): These pins form the 16-bit data bus of the microprocessor port.

10 M4 DTA Data Transfer Acknowledgment (Three-state Output):

This output pulses low from tristate to indicate that a databus transfer is complete . A pull-up resistor is required to hold a HIGH level when the pin is tristated.

15 N5 DS Data Strobe (5V Tolerant Input): This active low input

works in conjunction with CS to enable the read and write operations.

14 N4 R/W Read/Write (5V Tolerant Input): This input controls the

direction of the data bus lines (D0-D15) during a microprocessor access.

13 M5 CS Chip Select (5V Tolerant Input): Active low input used

by a microprocessor to activate the microprocessor port.

16-20 23-31

1,2,39,80,81,120,

121,159,160

M6,N6,N7,M7,N8

N9,N10,M8,M9,L7

L8,M10,L9,A10

E3,F3,K8,

L3,L4,L5,L6

A0 - A4 A5-A13

Address 0 - 13 (5V Tolerant Input): These lines provide the A0 - A13 address lines when accessing the internal registers or memories.

NC No Connect

MT90826 CMOS Advanced Information

Device Overview

The MT90826 Quad Digital Switch is capable of switching up to 4,096 × 4,096 channels. The MT90826 is designed to switch 64 kbit/s PCM or N x 64k bit/s data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis.

The serial input streams of the MT90826 can have a bit rate of 2.048, 4.096, 8.192 or 16.384 Mbit/s and are arranged in 125µs wide frames, which contain 32, 64,128 or 256 channels, respectively. The data rates on input and output streams match. All inputs and outputs may be programmed to 2.048, 4.096 or

8.192 Mb/s. STi0-15 and STo0-15 may be set to

16.384 Mb/s. Combinations of two bit rates,N and

are provided. See Table 1.

By using Mitel’s message mode capability, the microprocessor can access input and output timeslots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS devices.

The frame offset calibration function allows users to measure the frame offset delay for streams STi0 to STi31. The offset calibration is activated by a frame evaluation bit in the frame evaluation register. The evaluation result is stored in the frame evaluation registers and can be used to program the input offset delay for individual streams using internal frame input offset registers.

The microport interface is compatible with Motorola non-multiplexed buses. Connection memory locations may be directly written to or read from; data memory locations may be directly read from. A DTA signal is provided to hold the bus until the asynchronous microport operation is queued into the device. For applications that require no wait states, indirect reading and writing may be used. Intermediary registers are directly programmed with the write data and address, or read address. The data in the intermediary registers is internally transferred synchronous with the operation of the internal state machines. Completion of the operation is indicated by a status register ﬂag.

Functional Description

A functional Block Diagram of the MT90826 is shown in Figure 1.

Data and Connection Memory

For all data rates, the received serial data is converted to parallel format by internal serial-toparallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the control register, the usable data memory may be as large as 4,096 bytes. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams.

Data to be output on the serial streams may come from either the data memory or connection memory.

Serial Interface Mode Input Stream Input Data Rate Output Stream Output Data Rate

8 Mb/s STi0-31 8 Mb/s STo0-31 8 Mb/s

16 Mb/s STi0-15 16 Mb/s STo0-15 16 Mb/s

4 Mb/s and 8 Mb/s STi0-15 4 Mbs/ STo0-15 4 Mb/s

STi15-31 8 Mb/s STo16-31 8 Mb/s

16 Mb/s and 8 Mb/s STi0-11 16 Mb/s STo0-11 16 Mb/s

STi12-19 8 Mb/s STo12-19 8 Mb/s

4 Mb/s STi0-31 4 Mb/s STo0-31 4 Mb/s

2 Mb/s and 4 Mb/s STi0-15 2 Mb/s STo0-15 2 Mb/s

STi16-31 4 Mb/s STo16-31 4 Mb/s

2 Mb/s STi0-31 2 Mb/s STo0-31 2 Mb/s

Table 1 - Stream Usage and External Clock Rates

Advanced Information CMOS MT90826

Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel timeslot. This allows enough time for memory access and parallel-to-serial conversion.

Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 18. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an STBUS output stream.

drivers and bit error test pattern enable. If an output channel is set to a high-impedance state by setting the OE bit to zero in the connection memory, the STBUS output will be in a high impedance state for the duration of that channel. In addition to the perchannel control, all channels on the ST-BUS outputs can be placed in a high impedance state by pulling the ODE input pin low and programming the output stand by (OSB) bit in the control register to low. This action overrides the individual per-channel programming by the connection memory bits. See Table 2 for detail.

The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The addressing of the device internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register.

Clock Timing Requirements

The master clock (CLK) frequency must be either at

8.192 or 16.384MHz for serial data rate of 2.048,

4.096, 8.192 and 16.384Mb/s; see Table 6 for the selections of the master clock frequency.

By having several output channels connected to the same input source channel, data can be broadcasted from one input channel to several output channels.

In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least signiﬁcant bits) of the connection memory content is transferred directly to the parallelto-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor.

The three most signiﬁcant bits of the connection memory controls the following for an output channel: message or connection mode, constant or variable delay mode, enables/tristate the ST-BUS output

ODE pin OSB bit in Control register OE bit in Connection Memory ST-BUS Output Driver

0 0 X High-Z X X 0 Per Channel High-Z

Switching Conﬁgurations

The MT90826 maximum non-blocking switching conﬁgurations is determined by the data rates selected for the serial inputs and outputs. The switching conﬁguration is selected by three DR bits in the control register. See Table 5 and Table 6.

8Mb/s mode (DR2=0, DR1=0, DR0=0) When the 8Mb/s mode is selected, the device is

conﬁgured with 32-input/32-output data streams each having 128 64Kbit/s channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels. Table 1 summarizes the switching conﬁgurations and the relationship between different serial data rates and the master clock frequencies.

1 0 1 Enable 0 1 1 Enable 1 1 1 Enable

Table 2 - Output High Impedance Control

MT90826 CMOS Advanced Information

16Mb/s mode (DR2=0, DR1=0, DR0 =1) When the 16Mb/s mode is selected, the device is

conﬁgured with 16-input/16-output data streams each having 256 64Kbit/s channels. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.

4Mb/s and 8Mb/s mode (DR2=0, DR1=1, DR0=0) When the 4Mb/s and 8Mb/s mode is selected, the

device is conﬁgured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 4Mb/s and STi16-31/STo16-31 have a data rate of 8Mb/s. This mode allows a maximum non-blocking capacity of 3,072 x 3,072 channels.

16Mb/s and 8Mb/s mode (DR2=0, DR1=1, DR0=1) When the 16Mb/s and 8Mb/s mode is selected, the

device is conﬁgured with 20-input/20-output data streams. STi0-11/STo0-11 have a data rate of 16Mb/ s and STi12-19/STo12-19 have a data rate of 8Mb/s. This mode allows a maximum non-blocking capacity of 4,096 x 4,096 channels.

4Mb/s mode (DR2=1, DR1=0, DR0=0) When the 4Mb/s mode is selected, the device is

conﬁgured with 32-input/32-output data streams each having 64 64Kbit/s channels. This mode allows a maximum non-blocking capacity of 2,048 x 2,048 channels.

2Mb/s and 4Mb/s mode (DR2=1, DR1=0, DR0=1) When the 2Mb/s and 4Mb/s mode is selected, the

device is conﬁgured with 32-input/32-output data streams. STi0-15/STo0-15 have a data rate of 2Mb/s and STi16-31/STo16-31 have a data rate of 4Mb/s. This mode allows a maximum non-blocking capacity of 1,536 x 1,536 channels.

2Mb/s mode (DR2=1, DR1=1, DR0 =0) When the 2Mb/s mode is selected, the device is

conﬁgured with 32-input/32-output data streams each having 32 64Kbit/s channels. This mode allows a maximum non-blocking capacity of 1,024 x 1,024 channels.

Serial Input Frame Alignment Evaluation

The MT90826 provides the frame evaluation inputs, FEi0 to FEi31, to determine different data input delays with respect to the frame pulse the frame evaluation input select bits (FE0 to FE4) of the frame alignment register (FAR), users can select one of the thirty-two frame evaluation inputs for the frame alignment measurement.

F0i. By using

The internal master clock, which has a ﬁxed relationship with the CLK and F0i depending upon the mode of operation, is used as the reference timing signal to determine the input frame delays. See Figure 4 for the signal alignments between the internal and the external master clocks.

A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the control register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started.

The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse (F0i). See Table 7 for the description of the frame alignment register.

Input Frame Offset Selection

Input frame offset selection allows the channel alignment of individual input streams, which operate at 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, to be shifted against the input frame pulse (F0i). The input offset selection is not available for streams operated at 2.048Mb/s. This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems.

Each input stream has its own delay offset value programmed by the input delay offset registers. Each delay offset register can control 4 input streams. There are eight delay offset registers (DOS0 to DOS7) to control 32 input streams. Possible adjustment can range up to +4.5 internal master clock periods forward with resolution of 1/2 internal master clock period. See Table 8 and Table 9 for frame input delay offset programming.

Output Advance Offset Selection

The MT90826 allows users to advance individual output streams up to 45ns with a resolution of 15ns when the device is in 8Mb/s, 16Mb/s, 4 and 8 Mb/s or 16 and 8 Mb/s mode. The output delay adjustment is useful in compensating for variable output delays caused by various output loading conditions. The frame output offset registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn bits.

Advanced Information CMOS MT90826

See Table 10 and Table 11 for the frame output offset programming.

Memory Block Programming

The MT90826 provides users with the capability of initializing the entire connection memory block in two frames. Bits 13 to 15 of every connection memory location will be programmed with the pattern stored in bits 13 to 15 of the control register.

The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the control register is set to high, the block programming data will be loaded into the bits 13 to 15 of every connection memory location. The other connection memory bits (bit 0 to 12) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero.

Bit Error Monitoring

Delay Through the MT90826

The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform timeslot interchange functions with different throughput delay capabilities on the per-channel basis. For voice application, select variable throughput delay to ensure minimum delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch.

The delay through the device varies according to the type of throughput delay selected by the TM bits in the connection memory.

Variable Delay Mode (TM1=0, TM0=0)

The delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams.

The MT90826 allows users to perform bit error monitoring by sending a pseudo random pattern to a selected ST-BUS output channel and receiving the pattern from a selected ST-BUS input channel. The pseudo random pattern is internally generated by the device with the polynomial of 215 -1.

Users can select the pseudo random pattern to be presented on a ST-BUS channel by programming the TM0 and TM1 bits in the connection memory. When TM0 and TM1 bits are high, the pseudo random pattern is output to the selected ST-BUS output channel. The pseudo random pattern is then received by a ST-BUS input channel which is selected using the BSA and BCA bits in the bit error rate input register (BISR). An internal bit error counter keeps track of the error counts which is then stored in the bit error count register (BECR).

The bit error test is enabled and disabled by the SBER bit in the control register. Setting the bit from zero to one initiates the bit error test and enables the internal bit error counter. When the bit is programmed from one to zero, the internal bit error counter transfers the error counts to the bit error count register.

In the control register, a zero to one transition of the CBER bit resets the bit error count register and the internal bit error counter.

Constant Delay Mode (TM1=1, TM0=0)

In this mode, frame integrity is maintained in all switching conﬁgurations by making use of a multiple data memory buffer.

Microprocessor Interface

The MT90826 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed buses. The required microprocessor signals are the 16-bit data bus (D0-D15), 14-bit address bus (A0A13) and 4 control lines (CS, DS, R/W and DTA). See Figure 14 for Motorola non-multiplexed microport timing.

The MT90826 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory, DRR and BECR registers which are read only.

For data memory read operations, two consecutive microprocessor cycles are required. The read address (A0-A13) should remain the same for the two consecutive read cycles. The data memory content from the ﬁrst read cycle should be ignored. The correct data memory content will be presented to the data bus (D0-D15) on the second read cycle.

+ 21 hidden pages