MITEL MT90823AB, MT90823AG, MT90823AL, MT90823AP Datasheet

MT90823

3V Large Digital Switch

Features

• 2,048 × 2,048 channel non-blocking switching at 8.192 Mb/s

• Per-channel variable or constant throughput delay

• Automatic identiﬁcation of ST-BUS/GCI interfaces

• Accept ST-BUS streams of 2.048, 4.096 or

8.192 Mb/s

• Automatic frame offset delay measurement

• Per-stream frame delay offset programming

• Per-channel high impedance output control

• Per-channel message mode

• Control interface compatible to Motorola non-multiplexed CPUs

• Connection memory block programming

• 3.3V local I/O with 5V tolerant inputs and TTL-compatible outputs

• IEEE-1149.1 (JTAG) Test Port

Applications

• Medium and large switching platforms

• CTI application

• Voice/data multiplexer

• Digital cross connects

• ST-BUS/GCI interface functions

• Support IEEE 802.9a standard

DS5064 ISSUE 3 January 2000

Ordering Information

MT90823AP 84 Pin PLCC MT90823AL 100 Pin MQFP MT90823AB 100 Pin LQFP MT90823AG 120 Pin PBGA

-40 to +85°C

Description

The MT90823 Large Digital Switch has a non-blocking switch capacity of: 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s; 1,024 x 1,024 channels at 4.096 Mb/s; and 512 x 512 channels at 2.048 Mb/s. The device has many features that are programmable on a per stream or per channel basis, including message mode, input offset delay and high impedance output control.

Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels.

In addition, the input stream can be individually calibrated for input frame offset using a dedicated pin.

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15

Parallel

Converter

CLK

Serial

Timing

Unit

F0i FE/ AS/ IM DS/

WFPS

HCLK

TMS

TDI TDO IC RESETTCK TRST

Multiple Buffer

Data Memory

ALE

Figure 1 - Functional Block Diagram

Test Port

Loopback

Internal

Registers

Microprocessor Interface

CS R/W

/WR

A7-A0

Output

MUX

Connection

Memory

D15-D8/

DTA

AD7-AD0

ODE

Parallel

Serial

Converter

CSTo

STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9 STo10 STo11 STo12 STo13 STo14 STo15

MT90823 CMOS

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8

STi9 STi10 STi11 STi12 STi13 STi14 STi15

F0i

FE/HCLK

VSS

CLK

VDD

ODE

STo0

STo1

STo2

STo3

STo4

STo5

STo6

STo7

VSS

VDD

STo8

STo9

STo10

STo11

STo12

STo13

STo14

STo15

VSS

8 6 4 2 84 82 80 78 76

31 55

36 38 40 42 44 46 48 50 52

84 PIN PLCC

VSS

CSTo DTA

D15 D14

D13 D12

D11 D10

D9 D8

VSS

VDD AD7

AD6 AD5

AD4 AD3

AD2 AD1 AD0 VSS

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8

STi9 STi10 STi11 STi12 STi13 STi14 STi15

F0i

FE/HCLK

VSS

CLK

TDO

STo14

TCK

TRST

WFPS

RESET

VSS

VDD

STo8

STo9

STo10

STo11

STo12

STo13

100 PIN MQFP

(14mm x 20mm x 2.75mm)

DS/RD

STo2

STo3

STo4

STo5

STo6

STo7

22 24 26 28 30

2018161412108642

TDI

TMS

STo15

VSS

98 99

W/RW

AS/ALE

ODE

STo0

STo1

VSS

CSTo

525456586062646668707274767880

DTA D15

D14 D13

D12 D11

D10 D9

D8 VSS

VDD AD7

AD6 AD5

AD4 AD3

AD2 AD1

AD0 VSS

VDD

TMS

TDI

TDO

TCK

TRST

WFPS

RESET

RD DS/

NCNCNC

W/RW

AS/ALE

Figure 2 - PLCC and MQFP Pin Connections

CMOS MT90823

12345678910111213

VSS

STi0

STi2

STi4

VSS

STi1

STi3

STi5

STo12

STo14

STo13

STo15

VSS VSSVDD

VDD

VSS

STo11

STo9STo10

STo8

VDD

STo7

VSS

STo6

STo4STo5

STo3

STo2

STo1

VDD

STo0

ODE

VSSVSS VSSVDD

VDD

VSS

DTA

D14

D12

VSSVSS

VSS

CSTo

D15

D13

TOP VIEW

VDD

STi6

STi7

VDD

D10

D11

PBGA

VSS

VDD

VSS

AD6

AD4

AD7

AD5

STi8

STi10

STi12

STi9

STi11

STi13

VSS

VDD

VSS

(23mm x 23mm x 2.13mm)

(Ball Pitch = 1.5mm)

VDD

STi14

STi15

VDD

AD2

AD3

F0i

FE/HCLK

VSS

VDDVDDVDDVDD VSS VSS

VSS

AD0VSS

AD1

VSS

TDI

WFPS

R/W/RW

AS/ALETCK

VSS

CLK

TDO A7

TMS

TRSTICRESET

A5A3

CSDS/RD IM

1 - A1 corner is identiﬁed by metallized markings.

NC NC

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8

STi9 STi10 STi11 STi12 STi13 STi14 STi15

F0i

FE/HCLK

VSS

CLK

VDD

NC NC

100

VSS

STo15

STo14

STo13

STo12

(14mm x 14mm x 1.4mm)

4 6 8 101214 161820 2224

STo8

STo9

STo10

STo11

100 PIN LQFP

(Pin Pitch = 0.50mm)

VDD

VSS

STo7

VSS

5456586062646668707274

ODE

STo0

STo1

STo2

STo3

STo4

STo5

STo6

NC CSTo

DTA D15

D14 D13

D12

D11 D10 D9

D8 VSS

VDD

AD7 AD6

AD5 AD4

AD3 AD2

AD1 AD0

VSS

TMS

TDI

TDO

TCK

TRST

WFPS

RESET

RD DS/

W/RW

AS/ALE

Figure 3 - PBGA and LQFP Pin Connections

MT90823 CMOS

Pin Description

Pin #

PLCC

100

MQFP

100

LQFP

120

BGA

Name Description

1, 11, 30, 54 64, 75

2, 32,635, 40,6737,

3 - 10 68-75 65 -72B6,A6,A5,B5,A4,

12 -2781-96 78 -93C1,C2,D1,D2,E1,

31, 41, 56, 66,

76, 99

28 97 94 L1 F0i Frame Pulse (5V Tolerant Input): When the WFPS

28, 38, 53, 63, 73,

64,98

A1,A2,A12,A13,

B1,B2,B7,B12, B13,C3,C5,C7,

C9,C11,E3,E11

G3,G11,J3,J11, L3,L5,L7,L9,L11, M2,M12,M13,N1

C4,C6,C8,C10,

D3,D11,F3,F11,

H3,H11,K3,K11,

L4,L6,L8,L10

B4,A3,B3

E2,F1,F2,G1,G2,

H1,H2,J1,J2,K1,

STo8 - 15 ST-BUS Output 8 to 15 (5V Tolerant Three-state

STi0 - 15 ST-BUS Input 0 to 15 (5V Tolerant Inputs): Serial

Ground.

+3.3 Volt Power Supply.

Outputs): Serial data Output stream. These streams

may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register.

data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0 - 1 in the IMS register.

pin is low, this input accepts and automatically identiﬁes frame synchronization signals formatted according to ST-BUS and GCI speciﬁcations. When the WFPS pin is high, this pin accepts a negative frame pulse which conforms to WFPS formats.

29 98 95 L2 FE/HCLK Frame Evaluation / HCLK Clock (5V Tolerant Input):

When the WFPS pin is low, this pin is the frame measurement input. When the WFPS pin is high, the HCLK (4.096MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode.

31 100 97 N1 CLK Clock (5V T olerant Input):Serial clock for shifting data

in/out on the serial streams (STi/o 0 - 15). Depending upon the value programmed at bits DR0 - 1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock.

33 6 3 N2 TMS Test Mode Select (3.3V Input with internal pull-up):

JTAG signal that controls the TAP controller state transitions.

34 7 4 M3 TDI Test Serial Data In (3.3V Tolerant Input with internal

pull-up): JTAG serial test instructions and data are shifted in on this pin.

35 8 5 N3 TDO Test Serial Data Out (3.3V Output): JTAG serial data

is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.

CMOS MT90823

Pin Description (continued)

Pin #

PLCC

36 9 6 M4 TCK Test Clock (5V Tolerant Input): Provides the clock to

37 10 7 N4 TRST Test Reset (3.3V Input with internal pull-up):

38 11 8 M5 IC Internal Connection (3.3V Input with internal

39 12 9 N5 RESET Device Reset (5V Tolerant Input): This input (active

100

MQFP

100

LQFP

120

BGA

Name Description

the JTAG test logic.

Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up, or held low, to ensure that the MT90823 is in the normal functional mode.

pull-down): Connect to VSS for normal operation. This pin must be low for the MT90823 to function normally and to comply with IEEE 1149 (JTAG) boundary scan requirements.

LOW) puts the MT90823 in its reset state to clear the device internal counters, registers and bring STo0 - 15 and microport data outputs to a high impedance state. The time constant for a power up reset circuit must be a minimum of ﬁve times the rise time of the power supply. In normal operation, the RESET pin must be held low for a minimum of 100nsec to reset the device.

40 13 10 M6 WFPS Wide Frame Pulse Select (5V Tolerant Input): When

1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS/GCI mode.

41 -4814-21 11 -

49 22 19 N11 DS/RD Data Strobe / Read (5V Tolerant Input): For Motorola

50 23 20 M10 R/W / WR Read/Write / Write (5V Tolerant Input): In the cases

N6,M7,N7,N8,

M8,N9,M9,N10

A0 - A7 Address 0 - 7 (5V Tolerant Input): When

non-multiplexed CPU bus operation is selected, these lines provide the A0 - A7 address lines to the internal memories.

multiplexed bus operation, this input is DS. This active high DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8-D15) as outputs.

of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0 - AD7, D8-D15) during a microprocessor access. For multiplexed bus operation, this input is WR. This active low input is used with RD to control the data bus (AD0 - 7) lines as inputs.

MT90823 CMOS

Pin Description (continued)

Pin #

PLCC

51 24 21 N12 CS Chip Select (5V T olerant Input):Active low input used

52 25 22 M11 AS/ALE Address Strobe or Latch Enable (5V T olerant Input):

53 26 23 N13 IM CPU Interface Mode (5V Tolerant Input): When IM is

100

MQFP

100

LQFP

120

BGA

Name Description

by a microprocessor to activate the microprocessor port of MT90823.

This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground.

high, the microprocessor port is in the multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode.

55 -6232-39 29 -

65 -7242-49 39 -

73 50 47 C12 DTA Data Transfer Acknowledgement (5V tolerant

74 55 48 C13 CST o Control Output (5V Tolerant Output).This is a 4.096,

76 57 54 B11 ODE Output Drive Enable (5V Tolerant Input): This is the

L12,L13,K12, K13,J12,J13,

H12,H13

G12,G13,F12,

F13,E12,E13,

D12,D13

AD0 - 7 Address/Data Bus 0 to 7 (5V Tolerant I/O): These

pins are the eight least signiﬁcant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port.

D8 - 15 Data Bus 8-15 (5V Tolerant I/O): These pins are the

eight most signiﬁcant data bits of the microprocessor port.

Three-state Output): Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated.

8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section.

output enable control for the STo0-15 serial outputs. When ODE input is low and the OSB bit of the IMS register is low, STo0-15 are in a high impedance state. If this input is high, the STo0-15 output drivers are enabled. However, each channel may still be put into a high impedance state by using the per channel control bit in the connection memory.

77 -8458-65 55 -62A11,B10,A10,B9,

A9,A8,B8,A7

STo0 - 7 Data Stream Output 0 to 7 (5V Tolerant Three-state

Outputs): Serial data Output stream. These streams have selectable data r ates of 2.048, 4.096 or 8.192 Mb/ s.

Pin Description (continued)

Pin #

PLCC

100

MQFP

100

LQFP

120

BGA

CMOS MT90823

Name Description

- 1 - 4, 27 -

30,

51 -

77 -

1 - 2,

24 -

27,

49 -

52,

74 -

77,

99 -

100

NC No connection.

Device Overview

The MT90823 Large Digital Switch is capable of switching up to 2,048 × 2,048 channels. The MT90823 is designed to switch 64 kb/s PCM or N x 64 kb/s data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis.

The serial input streams of the MT90823 can have a bit rate of 2.048, 4.096 or 8.192 Mbit/s and are arranged in 125µs wide frames, which contain 32, 64 or 128 channels, respectively. The data rates on input and output streams are identical.

By using Mitel’s message mode capability, the microprocessor can access input and output time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS devices. The MT90823 automatically identiﬁes the polarity of the frame synchronization input signal and conﬁgures its serial streams to be compatible to either ST-BUS or GCI formats.

Two different microprocessor bus interfaces can be selected through the Input Mode pin (IM): Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola multiplexed/non-multiplexed buses.

The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be programmed for individual streams using internal frame input offset registers, see Table 11.

The internal loopback allows the ST-BUS output data to be looped around to the ST-BUS inputs for diagnostic purposes.

Functional Description

A functional Block Diagram of the MT90823 is shown in Figure 1.

Data and Connection Memory

For all data rates, the received serial data is converted to parallel format by internal serial-to-parallel converters and stored sequentially in the data memory. Depending upon the selected operation programmed in the interface mode select (IMS) register, the useable data memory may be as large as 2,048 bytes. The sequential addressing of the data memory is performed by an internal counter, which is reset by the input 8 kHz frame pulse (F0i) to mark the frame boundaries of the incoming serial data streams.

Data to be output on the serial streams may come from either the data memory or connection memory. Locations in the connection memory are associated with particular ST-BUS output channels. When a channel is due to be transmitted on an ST-BUS output, the data for this channel can be switched either from an ST-BUS input in connection mode, or from the lower half of the connection memory in message mode. Data destined for a particular channel on a serial output stream is read from the data memory or connection memory during the previous channel time-slot. This allows enough time for memory access and parallel-to-serial conversion.

Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output

MT90823 CMOS

streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto an ST-BUS output stream.

By having several output channels connected to the same input source channel, data can be broadcasted from one input channel to several output channels.

In message mode, the microprocessor writes data to the connection memory locations corresponding to the output stream and channel number. The lower half (8 least signiﬁcant bits) of the connection memory content is transferred directly to the parallel-to-serial converter. This data will be output on the ST-BUS streams in every frame until the data is changed by the microprocessor.

The ﬁve most signiﬁcant bits of the connection memory controls the following for an output channel: message or connection mode; constant or variable delay; enables/tristate the ST-BUS output drivers; and, enables/disable the loopback function. In addition, one of these bits allows the user to control the CSTo output.

The MT90823 provides two different interface timing modes controlled by the WFPS pin. If the WFPS pin is low, the MT90823 is in ST-BUS/GCI mode. If the WFPS pin is high, the MT90823 is in the wide frame pulse (WFP) frame alignment mode.

In ST-BUS/GCI mode, the input 8 kHz frame pulse can be in either ST-BUS or GCI format. The MT90823 automatically detects the presence of an input frame pulse and identiﬁes it as either ST-BUS or GCI. In ST-BUS format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell, see Figure 11. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 12.

Wide Frame Pulse (WFP) Frame Alignment Timing

When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 kHz frame pulse is in ST-BUS format. The timing relationship between CLK, HCLK and the frame pulse is deﬁned in Figure

13.

If an output channel is set to a high-impedance state through the connection memory, the ST-BUS output

will be in a high impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS outputs can be placed in a high impedance state by either pulling the ODE input pin low or programming the output standby (OSB) bit in the interface mode selection register to low. This action overrides the individual per-channel programming by the connection memory bits.

The connection memory data can be accessed via the microprocessor interface through the D0 to D15 pins. The addressing of the device internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Tables 4, 6 and 7).

Serial Data Interface Timing

The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096, 8.192 or 16.384 MHz for serial data rate of

2.048, 4.096 or 8.192 Mb/s respectively. The input and output stream data rates will always be identical.

When the WFPS pin is high, the frame alignment evaluation feature is disabled, but the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams.

Switching Conﬁgurations

The MT90823 maximum non-blocking switching conﬁgurations is determined by the data rates selected for the serial inputs and outputs. The switching conﬁguration is selected by two DR bits in the IMS register. See Table 8 and Table 9.

2.048 Mb/s Serial Links (DR0=0, DR1=0) When the 2.048 Mb/s data rate is selected, the

device is conﬁgured with 16-input/16-output data streams each having 32 64 kb/s channels. This mode requires a CLK of 4.094 MHz and allows a maximum non-blocking capacity of 512 x 512 channels.

4.096 Mb/s Serial Links (DR0=1, DR1=0) When the 4.096 Mb/s data rate is selected, the

device is conﬁgured with 16-input/16-output data streams each having 64 64 kb/s channels. This

CMOS MT90823

mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels.

8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the

device is conﬁgured with 16-input/16-output data streams each having 128 64 kb/s channels. This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching conﬁgurations and the relationship between different serial data rates and the master clock frequencies.

Serial

Interface

Data Rate

2 Mb/s 4.096 512 x 512 4 Mb/s 8.192 1,024 x 1,024 8 Mb/s 16.384 2,048 x 2,048

Table 1- Switching Conﬁguration

Input Frame Offset Selection

Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). This feature is useful in compensating for variable path delays caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed switching systems.

Master Clock

Required

(MHz)

Matrix

Channel

Capacity

The SFE bit must be set to zero before starting a new measurement cycle.

In ST-BUS mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 10 and Figure 3 for the description of the frame alignment register.

This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VDD).

Memory Block Programming

The MT90823 provides users with the capability of initializing the entire connection memory block in two frames. Bits 11 to 15 of every connection memory location will be programmed with the pattern stored in bits 5 to 9 of the IMS register.

The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero.

Loopback Control

Each input stream can have its own delay offset value by programming the frame input offset (FOR) registers. Possible adjustment can range up to +4 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 4, Table 11 and Table 12 for delay offset programming.

Serial Input Frame Alignment Evaluation

The MT90823 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i.

A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the evaluation starts when the SFE bit in the IMS register is changed from low to high. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high. This signals that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register.

The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped backed internally to the ST-BUS input for diagnostic purposes.

If the LPBK bit is high, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., data from STon channelm routes to the STi n channelm internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero.

Delay Through the MT90823

The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice application, select variable throughput

MT90823 CMOS

delay to ensure minimum delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch.

The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory.

Variable Delay Mode (V/C bit = 0)

The delay in this mode is dependent only on the combination of source and destination channels. It is independent of input and output streams. The minimum delay achievable in the MT90823 is three time-slots. When the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same frame delay occurs if the input channel n is switched to output channel n+1 or n+2. When input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the MT90823 in the variable delay mode.

Constant Delay Mode (V/C bit = 1)

In this mode, frame integrity is maintained in all switching conﬁgurations by using a multiple data memory buffer. Input channel data written into the data memory buffers during frame n will be read out during frame n+2.

In the MT90823, the minimum throughput delay achievable in the constant delay mode is one frame. For example, in 2 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.

Microprocessor Interface

The MT90823 provides a parallel microprocessor interface for non-multiplexed or multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses.

If the IM pin is low, the MT90823 microprocessor interface assumes Motorola non-multiplexed bus mode. If the IM pin is high, the device microprocessor interface accepts two different timing modes (mode1 and mode2) which allows direct connection to multiplexed microprocessors.

The microprocessor interface automatically identiﬁes the type of microprocessor bus connected to the MT90823. This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is low at the falling edge of AS/ALE, then the mode 2 multiplexed bus timing is selected.

Delay for Variable Throughput Delay Mode

(m - output channel number)

Input Rate

m < n m = n, n+1, n+2 m > n+2

2.048 Mb/s 32 - (n-m) time-slots m-n + 32 time-slots m-n time-slots

4.096 Mb/s 64 - (n-m) time-slots m-n + 64 time-slots m-n time-slots

8.192 Mb/s 128 - (n-m) time-slots m-n + 128 time-slots m-n time-slots

Table 2 - Variable Throughput Delay Value

Input Rate

2.048 Mb/s 32 + (32 - n) + (m - 1) time-slots

4.096 Mb/s 64 + (64 - n) + (m- 1) time-slots

8.192 Mb/s 128 + (128 - n) + (m- 1) time-slots

Table 3 - Constant Throughput Delay Value

(n - input channel number))

Delay for Constant Throughput Delay Mode

(m - output channel number)

(n - input channel number))

CMOS MT90823

For multiplexed operation, the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/ Address latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W/WR), Chip select (CS) and Data transfer acknowledge (DTA) signals are required. See Figure 13 and Figure 14 for multiplexed parallel microport timing.

For the Motorola non-multiplexed bus, the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA) signals are required. See Figure 15 for Motorola nonmultiplexed microport timing.

The MT90823 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only.

Memory Mapping

The address bus on the microprocessor interface selects the MT90823 internal registers and memory. If the A7 address input is low, then the control (CR), interface mode selection (IMS), frame alignment (FAR) and frame input offset (FOR) registers are addressed by A6 to A0 as shown in Table 4.

If the A7 address input is high, then the remaining address input lines are used to select up to 128 memory subsection locations. The number selected corresponds to the maximum number of channels per input or output stream. The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories.

The control and IMS registers together control all the major functions of the device. The IMS register should be programmed immediately after system power-up to establish the desired switching conﬁguration (see “Serial Data Interface Timing” and “Switching Conﬁgurations” ).

an internal memory subsections corresponding to input or output ST-BUS streams.

The data in the IMS register consists of block programming bits (BPD0-BPD4), block programming enable bit (BPE), output standby bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0, DR1). The block programming and the block programming enable bits allows users to program the entire connection memory, (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all ST-BUS output drivers are enabled.

Connection Memory Control

The contents of the CSTo bit of each connection memory location are output on the CSTo pin once every frame. The CSTo pin is a 4.096, 8.192 or

16.384 Mb/s output carrying 512, 1,024 or 2,048 bits respectively. If the CSTo bit is set high, the corresponding bit on the CSTo output is transmitted high. If the CSTo bit is low, the corresponding bit on the CSTo output is transmitted low. The contents of the CSTo bits of the connection memory are transmitted sequentially via the CSTo pin and are synchronous with the data rates on the other ST-BUS streams.

The CSTo bit is output one channel before the corresponding channel on the ST-BUS. For example, in 2Mb/s mode, the contents of the CSTo bit in position 0 (STo0, CH0) of the connection memor y is output on the ﬁrst clock cycle of channel 31 via CSTo pin. The contents of the CSTo bit in position 32 (STo1, CH0) of the connection memor y is output on the second clock cycle of channel 31 via CSTo pin.

When either the ODE pin or the OSB bit is high, the OE bit of each connection memory location enables (if high) or disables (if low) the output drivers for an individual ST-BUS output stream and channel. Table 5 details this function.

The control register controls switching operations in the MT90823. It selects the internal memory locations that specify the input and output channels selected for switching.

The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). The memory block programming bit allows users to program the entire connection memory block, (see “Memory Block Programming” ). The memory select bit controls the selection of the connection memory or the data Memory. The stream address bits deﬁne

The connection memory message channel (MC) bit (if high) enables message mode in the associated ST-BUS output channel. When message mode is enabled, only the lower half (8 least signiﬁcant bits) of the connection memory is transferred to the ST-BUS outputs.

If the MC bit is low, the contents of the connection memory stream address bit (SAB) and channel address bit (CAB) deﬁnes the source information (stream and channel) of the time-slot that will be switched to the output.

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