MITEL MT9074AP, MT9074AL Datasheet

MT9074

T1/E1/J1 Single Chip Transceiver

Advance Information

Features

• Combined E1 (PCM 30) and T1 (D4/ESF) framer,
Line Interface Unit (LIU) and link controller with
optional digital framer only mode

• In T1 mode the LIU can recover signals attenuated
by up to 36 dB (6000 ft. of 24 AWG cable)

• In E1 mode the LIU can recover signals attenuated
by up to 36 dB (2000 m. of 0.65mm cable)

• Two HDLCs: FDL and channel 24 in T1 mode,
timeslot 0 (Sa bits) and timeslot 16 in E1 mode

• Two-frame elastic buffer in Rx & Tx (T1) directions

• Programmable transmit dela y through tr ansmit slip
buffer

• Low jitter DPLL for clock generation

• Enhanced alarms, performance monitoring and
error insertion functions

• Intel or Motorola non-multiplexed parallel
microprocessor interface

• ST-BUS 2.048 Mbit/s backplane bus for both data
and signaling

• Japan Telecom J1 Framing and Yellow Alarm

• Hardware data link access

• JTAG Boundary Scan

Applications

• E1/T1 add/drop multiplexers and channel banks

• CO and PBX equipment interfaces

• Primary Rate ISDN nodes

• Digital Cross-connect Systems (DCS)

DS5024 ISSUE 5 September 1999

Ordering Information

MT9074AP 68 Pin PLCC
MT9074AL 100 Pin MQFP

-40°C to 85°C

Description

The MT9074 is a single chip device, operable in
either T1 or E1 mode, integrating either an advanced
T1 (T1 mode) or PCM 30 (E1 mode) framer with a
Line Interface Unit (LIU).

The framer interfaces to a 2.048 Mbit/s backplane
providing selectable data link access with optional
HDLC controllers for either the FDL bits and channel
24 (T1 mode) or Sa bits and channel 16 (E1 mode).
The LIU interfaces the framer to T1 (T1 mode) or
PCM 30 (E1 mode) transformer-isolated four-wire
line with minimal external components required.

In T1 mode the MT9074 supports D4, ESF and SLC­96 formats, meeting the latest recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T1.403 and T1.408. In E1 mode the
MT9074 supports the latest ITU-T
Recommendations including G.703, G.704, G.706,
G.732, G.775, G.796, G.823 for PCM 30, and I.431
for ISDN primary rate. It also supports ETSI ETS 300
011, ETS 300 166 and ETS 300 233.

DSTi
CSTi

Tdi

Tdo

Tms
Tclk

Trst

IRQ

D7~D0

AC4

AC0

R/W/WR

CS

DS/RD

DSTo
CSTo

ST-BUS

Interface

ST Loop

IEEE

1149.1

Interface

Microprocessor

ST-BUS

Interface

RxDLCLK RxDL

TxDL TxDLCLK

Data Link,

HDLC0

HDLC1

Alarm Detection, 2 Frame Slip Buffer

Figure 1 - Functional Block Diagram

TxMF

Transmit Framing, Error,

Test Signal Generation and Slip Buffer

PL Loop

National

Bit Buffer

CAS

Buffer

Receive Framing, Performance Monitoring,

TxAO TxB TxA

DG Loop

RxFP

Pulse

Generator

Jitter Attenuator

& Clock Control

Recovery

Clock,Data

E1.5o

F0b C4bRxMF LOS

Line

Driver

RM

Loop

MT

Rx Equalizer

& Data Slicer

Loop

TTIP
TRING

S/FR
BS/LS

OSC1
OSC2

RTIP
RRING

1

MT9074 Advance Information

RESET

INT/

R/

W/WR

CS

IRQ

D0
D1
D2
D3

VSS

MOT
VDD

D4
D5
D6
D7

AC0

DSTo

DS/RD

DSTi

CSTi

CSTo

987654321
10
11
12
13
14
15
16
17
18

IC

19
20
21
22
23
24
25
26

27

282930313233343536373839404142

AC1

AC2

AC3

AC4

GNDARx

VDD

RTIP

VSS

OSC2

RRING

VDDArx

OSC1

VDD

VSS

VDD

TxDLICIC

TxLCLK

S/FR/C1.5i

68676665646362

TxA

TxB

VSS

RxDL

RxDCLK

TxMF

LOS

61
60

59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

43

RxMF

BS/LS

TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o

68 PIN PLCC

RESET

INT/

R/

NC
NC
CS

IRQ

D0
D1
D2
D3

VSS

IC
MOT
VDD

D4
D5
D6
D7

W/WR

AC0

NC

82

84

86

88

90

92

94

96

98

100

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

VSS

VDD

CSTo

CSTi

DSTo

DSTi

DS/RD

NC

NCNCNC

AC2

AC1

AC3

AC4

RTIP

GNDARx

OSC1

OSC2

RRING

VDARx

VSS

VDD

VDD

VSS

100 PIN MQFP (JEDEC MO-112)

FR/C1.5i

TXDL

S/

TxB

TxA

TCDLCK

22 24 26 28 30

2018161412108642

RXDL

RXDLCK

TxMF

RxMF

NC

BS/LS

LOS

IC

NC

IC

NCNCNC

NC

525456586062646668707274767880

50

48

46

44

42

40

38

36

34

32

NCNCNCNCNC

NC

NC
NC
TxAO
Trst
Tclk
Tms
Tdo
Tdi
GNDATX
TRING
TTIP
VDDATX
VDD
VSS
IC
RxFP
F0b
C4b
E1.5o/C1.5o
NC

Figure 2 - Pin Connections

2

Advance Information MT9074

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

1 66 OSC1 Oscillator Input. This pin is either connected via a 20.000 MHz crystal to OSC2

2 67 OSC2 Oscillator Output. Connect a 20.0 MHz crystal between OSC1 and OSC2. Not

368 VSSNegative Power Supply (Input). Digital ground.
469 VDDPositive Power Supply (Input). Digital supply (+5V ± 5%).
5 70 CSTo Control ST-BUS Output. CSTo carries serial streams for CAS and CCS

Name Description

where a crystal is used, or is directly driven when a 20.000 MHz. oscillator is
employed.

suitable for driving other devices.

respectively a 2.048 Mbit/s ST-BUS status stream which contains the 30 receive
signalling nibbles (ABCDZZZZ or ZZZZABCD). The most significant nibbles of
each ST-BUS time slot are valid and the least significant nibbles of each ST-BUS
time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set
to 1. If MSN=0, the position of the valid and tristated nibbles are reversed.

6 71 CSTi Control ST-BUS Input. CSTi carries serial streams for CAS and CCS respectively

a 2.048 Mbit/s ST-BUS control stream which contains the 30 transmit signalling
nibbles (ABCDXXXX or XXXXABCD) when RPSIG=0. When RPSIG=1 this pin
has no function. The most significant nibbles of each ST-BUS time slot are valid
and the least significant nibbles of each ST-B US time slot are ignored when control
bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the
valid and ignored nibbles is reversed.

7 72 DSTo Data ST-BUS Output. A 2.048 Mbit/s serial stream which contains the 24/30

PCM(T1/E1) or data channels received on the PCM 24/30 (T1/E1) line.

8 73 DSTi Data ST-BUS Input. A 2.048 Mbit/s serial stream which contains the 24/30 (T1/

E1)PCM or data channels to be transmitted on the PCM 24/30 (T1/E1)line.

974DS/RD Data/Read Strobe (Input).

In Motorola mode (DS), this input is the active low data strobe of the
microprocessor interface.
In Intel mode (RD), this input is the active low read strobe of the microprocessor
interface.

10 83 CS Chip Select (Input). This active low input enables the non-multiplexed parallel

microprocessor interface of the MT9074. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance
state.

11 84 RESET RESET (Input). This active low input puts the MT9074 in a reset condition. RESET

should be set to high for normal operation. The MT9074 should be reset after
power-up. The RESET pin must be held low for a minimum of 1µsec. to reset the
device properly.

12 85 IRQ Interrupt Request (Output). A low on this output pin indicates that an interrupt

request is presented. IRQ is an open drain output that should be connected to V
through a pull-up resistor. An active low CS signal is not required for this pin to
function.

13 -1686-89 D0 - D3 Data 0 to Data 3 (Three-state I/O). These signals combined with D4-D7 form the

bidirectional data bus of the microprocessor interface (D0 is the least significant
bit).

DD

3

MT9074 Advance Information

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

17 90 Vss Negative Power Supply (Input). Digital ground.
18 91 IC Internal Connection. Tie to Vss (ground) for normal operation.
19 92 INT/MOT Intel/Motorola Mode Selection (Input).A high on this pin configures the

20 93 VDD Positive Power Supply (Input). Digital supply (+5V± 5%).

21 -2494-97 D4 - D7 Data 4 to Data 7 (Three-state I/O). These signals combined with D0-D3 form the

25 98 R/W/WR Read/Write/Write Strobe (Input). In Motorola mode (R/W), this input controls the

Name Description

processor interface for the Intel parallel non-multiplexed bus type . A low configures
the processor interface for the Motorola parallel non-multiplexed type.

bidirectional data bus of the parallel processor interface (D7 is the most significant
bit).

direction of the data bus D[0:7] during a microprocessor access. When R/W is
high, the parallel processor is reading data from the MT9074. When low, the
parallel processor is writing data to the MT9074. For Intel mode (WR), this active
low write strobe configures the data bus lines as output.

26 -3099, 8-11 AC0 - AC4 Address/Control 0 to 4 (Inputs). Address and control inputs for the non-

multiplexed parallel processor interface. AC0 is the least significant input.

31 12 GND
32

33

34 15 VDD

35 16 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).
36 17 VSS Negative Power Supply (Input). Digital ground.
37 18 TxA Transmit A (Output). When the internal LIU is disabled (digital framer only

38 19 TxB Transmit B (Output). When the internal LIU is disabled and control bit NRZ=0,

13
14

RTIP

RRING

Receive Analog Ground (Input). Analog ground for the LIU receiver.

ARx

Receive TIP and RING (Input). Differential inputs for the receive line signal - must

be transformer coupled (See Figure 5). In digital framer mode these are TTL level
inputs that connect to the digital outputs of a receiver. If the receiver serial data
output is NRZ connect that output to RTIP. If the receiver data output is split phase
unipolar signal connect one signal to RTIP and the complementary signal to
RRING.

Receive Analog Power Suppl y (Input). Analog supply for the LIU receiv er (+5V±

ARx

5%).

mode), if control bit NRZ=1, and NRZ output data is clocked out on pin TxA with
the rising edge of C1.50 (TxB has no function when NRZ format is selected). If
NRZ=0, pins TxA and TxB are a complementary pair of signals that output digital
dual-rail clocked out with the rising edge of C1.50.

pins TxA and TxB are a complementary pair of signals that output digital dual-rail
data clocked out with the rising edge of C1.50.

39 20 RxDLCLK Data Link Clock (Output). A gapped clock signal derived from the extracted clock

from the line clock, available for an external device to clock in RxDL data (at 4, 8,
12, 16 or 20 kHz) on the rising edge.

40 21 RxDL Receive Data Link (Output). A serial bit stream containing received line data after

zero code suppression. This data is clocked out with the rising edge of E1.5o.

41 22 TxMF Transmit Multiframe Boundary (Input). An active low input used to set the

transmit multiframe boundary (CAS or CRC multiframe). The MT9074 will generate
its own multiframe if this pin is held high. This input is usually pulled high for most
applications.

4

Advance Information MT9074

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

42 23 RxMF Receive Multiframe Boundary (Output). An output pulse delimiting the received

43 24 BS/LS Bus/Line Synchronization Mode Selection (Input). If high, C4b and F0b will be

44 32 E1.5o/C1.5o 2.048 MHz in E1 mode or 1.544MHz in T1 mode, Extracted Clock (Output).

45 33 C4b 4.096 MHz System Clock (Input/Output). C4b is the clock for the ST-BUS

Name Description

multiframe boundary. The next frame output on the data stream (DSTo) is basic
frame zero on the T1 or PCM 30 link. In E1 mode this receive multiframe signal
can be related to either the receive CRC multiframe (page 01H, address 17H, bit 6,
MFSEL=1) or the receive signalling multiframe (MFSEL=0).

inputs; if low, C4b and F0b will be outputs.

If the internal L/U is enabled, this output is the clock extracted from the received
signal and used internally to clock in data received on RTIP and RRING. If the
internal LIU is disabled (digital framer mode), this output is a 1.544MHz clock
(T1) C1.5o or a 2.048 MHz clock C2o which clocks out the transmit digital data
TXA, TXB.

sections and transmit serial PCM data of the MT9074. In the free-run (S/FR=0) or
line synchronous mode (S/FR=1 and BS/LS=0) this signal is an output, while in
bus synchronous mode (S/FR=1) this signal is an input clock which is phase­locked to the extracted clock (E1.5o).

46 34 F0b Frame Pulse (Input/Output). This is the ST-BUS frame synchronization signal,

which delimits the 32 channel frame of CSTi, CSTo, DSTi, DSTo and the PCM30
link. In the free-run (S/FR=0) or line synchronous mode (S/FR=1 and BS/LS=0)
this signal is an output, while in the line synchrounous mode (S/FR=1 and BS/
LS=0) this signal is an input.

47 35 RxFP Receive Frame Pulse (Output). An 8kHz pulse signal, which is low for one

extracted clock period. This signal is synchronized to the receive DS1 or PCM 30
basic frame boundary.

48 36 IC Internal Connection. Must be left open for normal operation.
49 37 V
50 38 V
51 39 VDD

SS
DD

Negative Power Supply (Input). Digital ground.
Positive Power Supply (Input). Digital supply (+5V ± 5%).
Transmit Analog Power Supply (Input). Analog supply for the LIU transmitter

ATx

(+5V ± 5% 10%)).

52
53

54 42 GND

40
41

TTIP

TRING

ATx

Transmit TIP and RING (Outputs). Differential outputs for the transmit DS1 line

signal - must be transformer coupled (See Figure 5).

Transmit Analog Ground (Input). Analog ground for the LIU transmitter.
55 43 Tdi IEEE 1149.1 Test Data Input. If not used, this pin should be pulled high.
56 44 Tdo IEEE 1149.1 Test Data Output. If not used, this pin should be left unconnected.
57 45 Tms IEEE 1149.1 Test Mode Selection (Input). If not used, this pin should be pulled

high.

58 46 Tclk IEEE 1149.1 Test Clock Signal (Input). If not used, this pin should be pulled high.
59 47 Trst IEEE 1149.1 Reset Signal (Input). If not used, this pin should be held low.
60 48 TxAO Transmit All Ones (Input).High - TTIP, TRING will transmit data normally. Low -

TTIP, TRING will transmit an all ones signal.

5

MT9074 Advance Information

Pin Description

Pin #

68 Pin

PLCC

100 Pin

MQFP

61 57 LOS Loss of signal or synchronization (Output).When high, and LOS/LOF (page

62 58 IC Internal Connection. Tie to Vss (Ground) for normal operation.

59 NC No Connection. Leave open for normal operation.
63 60 IC Internal Connection. Tie to VSS (Ground) for normal operation.
64 61 TxDLCLK Transmit Data Link Clock (Output). A gapped clock signal derived from a gated

Name Description

02H address 13H bit 2) is zero, this signal indicates that the receive por tion of the
MT9074 is either not detecting an incoming signal (bit LLOS on page 03H address
18H is one) or is detecting a loss of basic frame alignment condition (bit SYNC on
page 03H address 10H is one). If LOS/LOF=1, a high on this pin indicates a loss of
signal condition.

2.048 Mbit/s clock for transmit data link at 4, 8, 12, 16 or 20 kHz. The transmit data
link data (TxDL) is clocked in on the rising edge of TxDLCLK. TxDLCLK can also
be used to clock DL data out of an external serial controller.

65 62 TxDL Transmit Data Link (Input). An input serial stream of transmit data link data at 4,

8, 12, 16 or 20 kbit/s.

66 63 S/FR/C1.5i Sychronous/Freerun Extracted Clock (Input): If low, and the internal LIU is

enabled, the MT9074 is in free run mode. Pins 45 C4b and 46 F0b are outputs
generating system clocks. Slips will occur in the receive slip buffer as a result of
any deviation between the MT9074's internal PLL (which is free - running) and the
frequency of the incoming line data. If high, and the internal LIU is enabled, the
MT9074 is in Bus or Line Synchronization mode depending on the BS/LS pin. If
the internal LIU is disabled, in digital framer mode, this pin (C1.5i) takes an input
clock 1.544Mhz (T1) / 2.048Mhz (E1) that clocks in the received digital data on
pins RTIP and RRING with its rising edge.

67 64 VDD Positive Power Supply (Input). Digital supply (+5V ± 5%).
68 65 VSS Negative Power Supply (Input). Digital ground.

Device Overview

The MT9074 in T1 mode operates as an advanced
T1 framer with an on-chip Line Interface Unit (LIU)
that meets or supports the recommendations
including ITU I.431, AT&T PUB43801, TR-62411,
ANSI T1.102, T.403 and T.408.

DS1 (T1 mode) or PCM 30 (E1 mode) transformer­isolated four wire line. The transmit portion of the
MT9074 LIU consists of a digital buffer, a digital-to­analog converter, and a differential line driver. The
receiver portion of the MT9074 LIU consists of an
input signal peak detector, an optional equalizer, a
smoothing filter, data and clock slicers and a clock
extractor.

The MT9074 in E1 mode operates as an advanced
PCM 30 framer with an on-chip Line Interface Unit
(LIU) that meets or supports the latest ITU-T
Recommendations for PCM 30 and ISDN primary
rate including G.703, G.704, G.706, G.775, G.796,
G.732, G.823 and I.431. It also meets or supports
the layer 1 requirements of ETSI ETS 300 011, ETS
300 166, ETS 300 233 and BS6450.

The Line Interface Unit (LIU) of the MT9074
interfaces the digital framer functions to either the

6

System timing may be slaved to the line, operated in
free-run mode or controlled by an external timing
source. In T1 mode the MT9074 contains a PLL
which always generates the transmit timing for the
LIU. In E1 mode the LIU also contains a Jitter
Attenuator (JA), which can be included in either the
transmit or receive path. The MT9074 will attenuate
jitter from 2.5 Hz and roll-off at a rate of 20 dB/
decade. The intrinsic jitter is less than 0.02 UI. The
PLL output (@1.544 MHz for T1 mode and @2.048
MHz for E1 mode) clocks out the transmit line data.

Advance Information MT9074

To accommodate some special applications, the
MT9074 also supports a digital framer only mode by
providing direct access to the transmit and receive
data in digital format, i.e. by-passing the analog LIU
front-end.

The digital portion of the MT9074 connects selected
channels of an incoming stream of time multiplexed

2.048 Mbit/s PCM channels to the transmit payload
of either the T1 or E1 trunk, while the receive
payload is connected to the ST-BUS 2.048 Mbit/s
backplane bus for both data and signalling with
channel times and the frame boundary synchronous
to the transmit side. Control, reporting and
conditioning of the line is implemented via a parallel
microprocessor interface.

The MT9074 has a comprehensive suite of status,
alarm, performance monitoring and reporting
features. These include counters for BPVs, CRC
errors, F-bit errors (T1 only), E-bit errors (E1 only),
errored frame alignment signals (E1 only), BERT,
OOF (T1 only), and RAI and continuous CRC errors
(E1 only). Also, included are transmission error
insertion for BPVs, CRC-6 errors (T1 only), CRC-4
errors (E1 only), framing bit errors (T1 only), frame
and non-frame alignment signal errors (E1 only),
payload errors and loss of signal errors. A built-in
PRBS generator (215 -1) can be connected to any
combination of outgoing channels; an equivalent
PRBS error detector can be independently
connected to any combination of receive channels.

calculation is performed as part of the framing
algorithm. In the transmit transparent mode, no
framing or signalling is imposed on the data transmit
from DSTi on the line. In addition, the MT9074
optionally allows the data link maintenance channel
to be modified and updates the CRC-4 remainder
bits to reflect the modification. All channel, framing
and signalling data passes through the device
unaltered. This is useful for intermediate point
applications of a PCM 30 link where the data link
data is modified, but the error information
transported by the CRC-4 bits must be passed to the
terminating end. In the receive transparent mode,
the received line data is channelled to DSTo with
framing operations disabled, consequently, the data
passes through the slip buffer and drives DSTo with
an arbitrary alignment.

In E1 mode the Sa bits can be accessed by the
MT9074 in the following three ways:

• Programming a register;

• Data link pins TxDL, RxDL, RxDLCLK and
TxDLCLK;

• HDLC Controller with a 128 byte FIFO.

A second HDLC Controller with a 128 byte FIFO is
available for connection to timeslot 16 in E1 mode.

Functional Description

MT9074 Line Interface Unit (LIU)

A complete set of loopbacks has been implemented,
which include digital, remote, ST-BUS, payload,
local, metallic and remote time slot.

The MT9074 also provides a comprehensive set of
maskable interrupts. Interrupt sources consist of
synchronization status, alarm status, counter
indication and overflow, timer status, slip indication,
maintenance functions and receive channel
associated signaling bit changes.

In T1 mode the framer operates in any one of the
framing modes: D4, SLC-96 and Extended
Superframe (ESF). The ESF FDL bits of the MT9074
can be accessed either through the data link pins
TxDL, RxDL, RxDLCLK and TxDLCLK, or through
internal registers for Bit Oriented Messages, or
through a built-in HDLC. A second HDLC may be
connected to DS1 channel 24 for the ISDN Primary
Rate signaling applications.

In E1 mode the MT9074 operates in either
termination or transparent modes selectable via
software control. In the termination mode the CRC-4

Receiver
The receiver portion of the MT9074 LIU consists of

an input signal peak detector, an optional equalizer
with two separate high pass sections, a smoothing
filter, data and clock slicers and a clock extractor.
Receive equalization gain can be set manually (i.e.,
software) or it can be determined automatically by
peak detectors.

The output of the receive equalizer is conditioned by
a smoothing filter and is passed on to the clock and
data slicer. The clock slicer output signal drives a
phase locked loop, which generates an extracted
clock (C1.50). This extracted clock is used to sample
the output of the data comparator

In T1 mode, the receiver portion of the LIU can
reliably recover clock and data from signals
attenuated by up to 36 dB @ 772 kHz (translates to
6000 ft. of PIC 24 AWG cable) and tolerate jitter to
the maximum specified by AT&T TR 62411 (see
Figure 3).

In E1 mode the receiver portion of the LIU can
reliably recover clock and data from signals

7

MT9074 Advance Information

attenuated by up to 36 dB @ 1024 kHz (translates to
2000 m. of PIC 0.65mm or 22 AWG cable) and
tolerate jitter to the maximum specified by ETS 300
011 (Figure 4).

The LOS output pin function is user selectable to
indicate any combination of loss of signal and/or loss
of basic frame synchronization condition.

The LLOS (Loss of Signal) status bit indicates when
the receive signal level is lower than the analog
threshold for at least 1 millisecond, or when more
than 192 consecutive zeros have been received. In
E1 mode the analog threshold is either of -20 dB or ­40 dB. For T1 mode the analog threshold is -40 dB.

In T1 mode, the receive LIU circuit requires a
terminating resistor of 100Ω across the device side
of the receive 1:1 transformer.

In E1 mode the receive LIU circuit requires a
terminating resistor of either 120Ω or 75Ω across the
device side of the receive1:1 transformer.

produce an analog signal, which is passed to the
complementary line drivers.

The complementary line drivers are designed to
drive a 1:2 step-up transformer (see Figure 5 for T1
mode and Figure 6 for E1 mode). A 0.68 uF
capacitor is required between the TTIP and the
transmit transformer. Resistors RT (as shown in
Figure 5) are for termination for transmit return loss.
The values of RT may be optimized for T1 mode, E1
120Ω lines, E1 75Ω lines or set at a compromise
value to serve multiple applications. Program the LIU
Control Word (address 1FH page 1) to adjust the
pulse amplitude accordingly.

Alternatively, the pulse level and shape may be
discretely programmed by writing to the Custom
Pulse Level registers (addresses 1CH to 1FH, page

2) and setting the Custom Transmit Pulse bit high (bit
3 of the Transmit Pulse Control Word). In this case
the output of each of the registers directly drives the
D/A converter going to the line driver. Tables 1 and 2
show recommended transmit pulse amplitude
settings.

The jitter tolerance of the clock extractor circuit
exceeds the requirements of TR 62411 in T1 mode
(see Figure 3) and G.823 in E1 mode (see Figure 4).

Transmitter
The transmit portion of the MT9074 LIU consists of a

high speed digital-to-analog converter and
complementary line drivers.

When a pulse is to be transmitted, a sequence of
digital values (dependent on transmit equalization)
are read out of a ROM by a high speed clock. These
values drive the digital-to-analog converter to

Peak to Peak

Jitter Amplitude

(log scale)

138UI
100UI

28UI
10UI

In T1 mode, the template for the transmitted pulse
(the DSX-1 template) is shown in Figure 7. The
nominal peak voltage of a mark is 3 volts. The ratio
of the amplitude of the transmit pulses generated by
TTIP and TRING lie between 0.95 and 1.05.

In E1 mode, the template for the transmitted pulse,
as specified in G.703, is shown in Figure 8. The
nominal peak voltage of a mark is 3 volts for 120 Ω
twisted pair applications and 2.37 volts for 75 Ω coax
applications. The ratio of the amplitude of the
transmit pulses generated by TTIP and TRING lie
between 0.95 and 1.05.

1.0UI

0.4UI

Jitter Frequency

0.1Hz

1.0Hz

10Hz 1.0kHz 10kHz 100kHz

4.9Hz

100Hz

(log scale)

Figure 3 - Input Jitter Tolerance as Recommended by TR-62411 (T1)

8

Advance Information MT9074

Peak to Peak

Jitter Amplitude

(log scale)

18UI

MT9074

Tolerance

1.5UI

0.2UI

1.667Hz 20Hz 2.4kHz 18kHz 100kHz

Jitter Frequency

(log scale)

Figure 4 - Input Jitter Tolerance as recommended by ETSI 300 011 (E1)

Name Functional Description

TXL2-0 Transmit Line Build Out 2 - 0. Setting these bits shapes the transmit pulse as detailed in

the table below:
TXL2 TXL1 TXL0 Line Build Out
0 0 0 0 to 133 feet/ 0 dB
0 0 1 133 to 266 feet
0 1 0 266 to 399 feet
0 1 1 399 to 533 feet
1 0 0 533 to 655 feet
1 0 1 -7.5 dB
1 1 0 -15 dB
1 1 1 -22.5 dB
After reset these bits are zero.

Table 1 - Transmit Line Build Out (T1)

TTIP

TRING

RTIP

RRING

0.68uF

RT

RT

1:2

+5V

1:1

100 Ω

Figure 5 - Analog Line Interface (T1)

Fuse

Tx

Fuse

RT: 2.4 Ω

Fuse

Fuse

Rx

9

MT9074 Advance Information

Name Functional Description

TX2-0 Transmit pulse amplitude. Select the TX2 –TX0 bits according to the line type, value of

termination resistors (RT), and transformer turns ratio used
TX2 TX1 TX0 Line Impedance(Ω) RT(Ω) Transformer Ratio
0 0 0 120 0 1:2
0 0 1 120 0 1:1
0 1 0 120 15 1:2
0 1 1 120 / 75 12.1 1:2
1 0 0 75 0 1:2
1 0 1 75 0 1:1
1 1 1 75 9.1 1:2
1 1 1 75 / 120 12.1 1:2
After reset these bits are zero.

Table 2 -Transmit Pulse Amplitude (E1)

TTIP

TRING

RTIP

RRING

0.68uF

+5V

T

R

T

1:2

R

1:1

120 Ω /

75 Ω

Figure 6 - Analog Line Interface (E1)

Fuse

Fuse

Fuse

Fuse

Tx

RT: Termination resis­tor. Please check Table

2 for specific resistor
values.

Rx

10

Advance Information MT9074

1.20

1.05

0.95

0.90

0.80

0.50

0.05
0

NORMALIZED AMPLITUDE

-0.05

-0.26

-0.45

Time (Nanoseconds)

Time U.I.

Normalized Amplitude

Time (Nanoseconds)

Time U.I.

Normalized Amplitude

0

0.15

0.23

0.34

0.46

0.61

0.77

-0.39

-0.27

-0.23

--0.12

--0.15
Time, in unit intervals (UI)

0.27

0.93

1.16

Figure 7 - Pulse Template (T1.403) (T1)

-499 -253 -175 -175 -78 0 175 220 499 752 --- ---

-.77 -.39 -.27 -.27 -.12 0 .27 .34 .77 1.16 --- --­.05 .05 .8 1.2 1.2 1.05 1.05 -.05 .05 .05 --- ---

Table 3 - Maximum Curve for Figure 7

-499 -149 -149 -97 0 97 149 149 298 395 603 752

-.77 -.23 -.23 -.15 0 .15 .23 .23 .46 .61 .93 1.16

-.05 -.05 .5 .9 .95 .9 .5 -.45 -.45 -.26 -.05 -.05

Table 4 - Minimum curve for Figure 7

Note: One Unit Interval = 648 nanoseconds

11

MT9074 Advance Information

Percentage of
Nominal Peak
Voltage

120

269nS

110
100

90
80

50

20

-10

-20

244nS

194nS

0

Nominal Pulse

219nS
488nS

Figure 8 Pulse Template (G.703)(E1)

20 Mhz Clock

The MT9074 requires a 20 Mhz clock. This may
provided by a 50 ppm oscillator as per Figure 9.

+5V

OSC1

OSC2

20MHz

OUT

Vdd

GND

.1µF

(open)

Figure 9 - Clock Oscillator Circuit

Alternatively, a crystal oscillator may be used. A
complete oscillator circuit made up of a crystal,
resistors and capacitors is shown in Figure 10. The
crystal specification is as follows.

Frequency: 20MHz
Tolerance: 50ppm
Oscillation Mode: Fundamental
Resonance Mode: Parallel
Load Capacitance: 32pF
Maximum Series Resistance: 35

Ω

Approximate Drive Level: 1mW

20MHz

OSC1

56pF

1MΩ

OSC2

Note: the 1µH inductor is optional

39pF

1µH*

100Ω

Figure 10 - Crystal Oscillator Circuit

12

Advance Information MT9074

dB

-0.5

0

-20 dB/decade

JITTER ATTENUATION (dB)

19.5

10 40 400 10K

Frequency (Hz)

Figure 11- TR 62411 Jitter Attenuation Curve

Phase Lock Loop (PLL)

The MT9074 contains a PLL, which can be locked to
either an input 4.096 Mhz clock or the extracted line
clock.The PLL will attenuate jitter from less than

2.5 Hz and roll-off at a rate of 20 dB/decade. Its
intrinsic jitter is less than 0.02 UI. The PLL will meet
the jitter transfer characteristics as specified by ATT
document TR 62411 and the relevant
recommendations as shown in Figure 11.

Clock Jitter Attenuation Modes

MT9074 has three basic jitter attenuation modes of
operation, selected by the BS/LS and S/FR control
pins. Referring to the mode names given in Table 5
the basic operation of the jitter attenuation modes
are:

• System Bus Synchronous Mode.

• Line Synchronous Mode.

• Free-run mode.

In System Bus Synchronous mode pins C4b and F0b
are always configured as inputs, while in the Line
Synchronous and Free-Run modes C4b and F0b are
configured as outputs.

In

System Bus Synchronous

is applied to C4b. The applied clock is dejittered by

mode an external clock

Mode Name BS/LS S/FR Note

System Bus

Synchronous

Line Synchronous 0 1 PLL locked to E1.5o.

Free-Run x 0 PLL free - running.

1 1 PLL locked to C4b.

Table 5 - Selection of clock jitter attenuation

modes using the M/S and MS/FR pins

the internal PLL before being used to synchronize
the transmitted data. The clock extracted (with no
jitter attenuation performed) from the receive data
can be monitored on pin E1.5o.

In

Line Synchronous

mode, the clock extracted from
the receive data is dejittered using the internal PLL
and then output on pin C4b. Pin E1.5o provides the
extracted receive clock before it has been dejittered.
The transmit data is synchronous to the clean
receive clock.

In

Free-Run

mode the transmit data is synchronized
to the internally generated clock. The internal clock
is output on pin C4b. The clock signal extracted from
the receive data is not dejittered and is output
directly on E1.5o.

Depending on the mode selection above, the PLL
can either attenuate transmit clock jitter or the
receive clock jitter. Table 5 shows the appropriate
configuration of each control pin to achieve the

13

MT9074 Advance Information

appropriate mode and Jitter attenuation capability of
the MT9074

The Digital Interface

T1 Digital Interface

In T1 mode DS1 frames are 193 bits long and are
transmitted at a frame repetition rate of 8000 Hz,
which results in an aggregate bit rate of 193 bits x
8000/sec= 1.544 Mbits/sec. The actual bit rate is

1.544 Mbits/sec +/-50 ppm optionally encoded in
B8ZS format. The Zero Suppression control register
(page 1, address 15H,) selects either B8ZS
encoding, forced one stuffing or alternate mark
inversion (AMI) encoding. Basic frames are divided
into 24 time slots numbered 1 to 24. Each time slot is
8 bits in length and is transmitted most significant bit
first (numbered bit 1). This results in a single time
slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.

It should be noted that the Mitel ST-BUS has 32
channels numbered 0 to 31. When mapping to the
DS1 payload only the first 24 time slots and the last
(time slot 31, for the overhead bit) of an ST-BUS are
used (see Table 6). All unused channels are tristate.

When signalling information is written to the MT9074
in T1 mode using ST-BUS control links (as opposed
to direct writes by the microport to the on - board
signaling registers), the CSTi channels
corresponding to the selected DSTi channels
streams are used to transmit the signalling bits.

The most significant bit of an eight bit ST-BUS
channel is numbered bit 7 (see Mitel Application
Note MSAN-126). Therefore, ST-BUS bit 7 is
synonymous with DS1 bit 1; bit 6 with bit 2: and so
on.

Frame and Superframe Structure in T1 mode

Multiframing
In T1 mode, DS1 trunks contain 24 bytes of serial

voice/data channels bundled with an overhead bit.
The frame overhead bit contains a fixed repeating
pattern used to enable DS1 receivers to delineate
frame boundaries. Overhead bits are inserted once
per frame at the beginning of the transmit frame
boundary. The DS1 frames are further grouped in
bundles of frames, generally 12 (for D4 applications)
or 24 frames (for ESF - extended superframe
applications) deep. Table 7 and 8 illustrate the D4
and ESF frame structures respectively.

For D4 links the frame structure contains an
alternating 101010... pattern inserted into every
second overhead bit position. These bits are
intended for determination of frame boundaries, and
they are referred to as Ft bits. A separate fixed
pattern, repeating every superframe, is interleaved
with the Ft bits. This fixed pattern (001110), is used
to delineate the 12 frame superframe. These bits are
referred to as the Fs bits. In D4 frames # 6 and #12,
the LSB of each channel byte may be replaced with
A bit (frame #6) and B bit (frame #12) signalling
information.

For ESF links the 6 bit framing pattern 001011,

Since the maximum number of signalling bits
associated with any channel is 4 (in the case of
ABCD), only half a CSTi channel is required for
sourcing the signaling bits. The choice of which half
of the channel to use is selected by the control bit
MSN (page 01H address 14H). The same control bit
selects which half of the CSTo channel will contain
receive signaling information (the other nibble in the
channel being tristate). Unused channels are tristate.

DS1 Timeslots 12345678910111213141516
Voice/Data Channels

(DSTi/o and CSTi/o)
Ds1 Timeslots 17 18 19 20 21 22 23 24 -------­Voice/Data Channels

(DSTi/o and CSTi/o)

0123456779101112131415

16 17 18 19 20 21 22 23 24x25x26x27x28x29x30x31

Table 6 - STBUS vs. DS1 to Channel Relationship(T1)

inserted into every 4th overhead bit position, is used
to delineate both frame and superframe boundaries.
Frames #6, 12, 18 and 24 contain the A, B, C and D
signalling bits, respectively. A 4 kHz data link is
embedded in the overhead bit position, interleaved
between the framing pattern sequence (FPS) and the
transmit CRC-6 remainder (from the calculation done
on the previous superframe), see Table 8.

S
bit

14

Advance Information MT9074

The SLC-96 frame structure is similar to the D4
frame structure, except a facility management
overlay is superimposed over the erstwhile Fs bits,
see Table 9.

The protocol appropriate for the application is
selected via the Framing Mode Selection Word,
address 10H of Master Control page 1. In T1 mode
MT9074 is capable of generating the overhead bit
framing pattern and (for ESF links) the CRC
remainder for transmission onto the DS1 trunk. The
beginning of the transmit multiframe may be
determined by any of the following criteria:

(i)It may free - run with the internal multiframe
counters;

(ii)The multiframe counters may be reset with the
external hardware pin TxMF. If this signal is not
synchronous with the current transmit frame count it
may cause the far end to go temporarily out of sync.

(iii) Under software control (by setting the TxSYNC
bit in page 01 address 12H) the transmit multiframe
counters will be synchronized to the framing pattern
present in the overhead bits multiplexed into channel
31 bit 0 of the incoming 2.048 Mb/s digital stream
DSTi. Note that the overhead bits extracted from the
receive signal are multiplexed into outgoing DSTo
channel 31 bit 0.

(iv) In SLC - 96 mode the transmit frame counters
synchronize to the framing pattern clocked in on the
TXDL input.

Frame # Ft Fs Signalling

11
20
30
40
51
61A
70
81

91
10 1
11 0
12 0 B

Table 7 - D4 Superframe Structure(T1)

Frame # FPS FDL CRC Signalling

1X
2 CB1
3X
40
5X
6 CB2 A
7X
80

9X
10 CB3
11 X
12 1 B
13 X
14 CB4
15 X
16 0
17 X
18 CB5 C
19 X
20 1
21 X
22 CB6
23 X
24 1 D

Table 8 - ESF Superframe Structure (T1)

15

MT9074 Advance Information

Frame # Ft Fs Notes Frame # Ft Fs Notes Frame # Ft Fs Notes

1 1 25 1 C 49 1
2 0 R 26 X o 50 S S = Spoiler Bits
30 e270 n510
40s28Xc52S
51 y291 e531
6 0 n 30 X n 54 C C = Maintenance Field Bits
70 c310 t550
81h32Xr56C

91 r331 a571
10 1 o 34 X t 58 C
11 0 n 35 0 o 59 0
12 1 i 36 X r 60 A A = Alarm Field Bits
13 1 z 37 1 61 1
14 0 a 38 X F 62 A
15 0 t 39 0 i 63 0
16 0 i 40 X e 64 L L = Line Switch Field Bits
17 1 o 41 1 l 65 1
18 0 n 42 X d 66 L
19 0 43 0 67 0
20 1 d 44 X B 68 L
21 1 a 45 1 i 69 1
22 1 t 46 X t 70 L
23 0 a 47 0 s 71 0
24 1 48 S 72 S S = Spoiler Bits

Table 9 - SLC-96 Framing Structure(T1)

E1 Digital Interface

PCM 30 (E1) basic frames are 256 bits long and are
transmitted at a frame repetition rate of 8000 Hz,
which results in an aggregate bit rate of 256 bits x
8000/sec = 2.048 Mbits/sec. The actual bit rate is

2.048 Mbits/sec +/-50 ppm encoded in HDB3 format.
The HDB3 control bit (page 01H, address 15H, bit 5)
selects either HDB3 encoding or alternate mark
inversion (AMI) encoding. Basic frames are divided
into 32 time slots numbered 0 to 31, see Figure 34.
Each time slot is 8 bits in length and is transmitted
most significant bit first (numbered bit 1). This results
in a single time slot data rate of 8 bits x 8000/sec. =
64 kbits/sec.

It should be noted that the Mitel ST-BUS also has 32
channels numbered 0 to 31, but the most significant
bit of an eight bit channel is numbered bit 7 (see
Mitel Application Note MSAN-126). Therefore, ST­BUS bit 7 is synonymous with PCM 30 bit 1; bit 6
with bit 2: and so on (Figure 34).

PCM 30 time slot 0 is reserved for basic frame
alignment, CRC-4 multiframe alignment and the
communication of maintenance information. In most
configurations time slot 16 is reserved for either
Channel Associated Signalling (CAS or ABCD bit
signalling) or Common Channel Signalling (CCS).
The remaining 30 time slots are called channels and
carry either PCM encoded voice signals or digital
data. Channel alignment and bit numbering is
consistent with time slot alignment and bit
numbering. However, channels are numbered 1 to 30
and relate to time slots as per Table 10.

PCM 30
Timeslots

Voice/Data
Channels
(DSTi/o
and
CSTi/o)

Table 10 - STBUS vs. PCM-30 to Channel

0 1,2,3...15 16 17,18,19,... 31

0 1,2,3...15 16 17,18,19,... 31

Relationship(E1)

16

Advance Information MT9074

a

Basic Frame Alignment

PCM 30 Channel Zero

12345678

01ASa4Sa5Sa6Sa7S

01ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

01ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

11ASa4Sa5Sa6Sa7S

1ASa4Sa5Sa6Sa7S

1

1ASa4Sa5Sa6Sa7S

2

a8

a8

a8

a8

a8

a8

a8

a8

Time slot 0 of every basic frame is reserved for basic
frame alignment and contains either a Frame
Alignment Signal (FAS) or a Non-Frame Alignment
Signal (NFAS). FAS and NFAS occur in time slot zero
of consecutive basic frames as shown in Table 12.
Bit two is used to distinguish between FAS (bit two =

0) and NFAS (bit two = 1).

Basic frame alignment is initiated by a search for the
bit sequence 0011011 which appears in the last
seven bit positions of the FAS, see the Frame
Algorithm section. Bit position one of the FAS can be
either a CRC-4 remainder bit or an international
usage bit.

Bits four to eight of the NFAS (i.e., Sa4 - Sa8) are
additional spare bits which may be used as follows:

•Sa4 to Sa8 may be used in specific point-to-point
applications (e.g. transcoder equipments
conforming to G.761).

•Sa4 may be used as a message-based data link
for operations, maintenance and performance
monitoring.

•Sa5to Sa8 are for national usage.

CRC

CRC

Frame/

Type

0/FAS C10011011
1/NFAS
2/FAS C20011011
3/NFAS
4/FAS C30011011
5/NFAS

Sub Multi Frame 1

6/FAS C40011011
7/NFAS
8/FAS C10011011
9/NFAS
10/FAS C20011011
11/NFAS
12/FAS C30011011
13/NFAS E

Sub Multi Frame 2

14/FAS C40011011
15/NFAS E

Table 11 - FAS and NFAS Structure

A maintenance channel or data link at 4,8,12,16,or
20 kHz for selected Sa bits is provided by the
MT9074 in E1 mode to implement these functions.
Note that for simplicity all Sa bits including Sa4 are
collectively called national bits throughout this
document.

Bit three (designated as “A”), the Remote Alarm
Indication (RAI), is used to indicate the near end
basic frame synchronization status to the far end of a
link. Under normal operation, the A (RAI) bit should
be set to 0, while in alarm condition, it is set to 1.

Bit position one of the NFAS can be either a CRC-4
multiframe alignment signal, an E-bit or an
international usage bit. Refer to an approvals
laboratory and national standards bodies for specific
requirements.

indicates position of CRC-4 multiframe alignment sign

CRC-4 Multiframing in E1 mode

The primary purpose for CRC-4 multiframing is to
provide a verification of the current basic frame
alignment, although it can also be used for other
functions such as bit error rate estimation. The CRC­4 multiframe consists of 16 basic frames numbered 0
to 15, and has a repetition rate of 16 frames X 125
microseconds/frame = 2 msec.

CRC-4 multiframe alignment is based on the 001011
bit sequence, which appears in bit position one of the
first six NFASs of a CRC-4 multiframe.

The CRC-4 multiframe is divided into two
submultiframes, numbered 1 and 2, which are each
eight basic frames or 2048 bits in length.

The CRC-4 frame alignment verification functions as
follows. Initially, the CRC-4 operation must be
activated and CRC-4 multiframe alignment must be
achieved at both ends of the link. At the local end of
a link, all the bits of every transmit submultiframe are
passed through a CRC-4 polynomial (multiplied by
X4 then divided by X4 + X + 1), which generates a
four bit remainder. This remainder is inserted in bit

17

MT9074 Advance Information

position one of the four FASs of the following
submultiframe before it is transmitted (see Table 12).

The submultiframe is then transmitted and, at the far
end, the same process occurs. That is, a CRC-4
remainder is generated for each received
submultiframe. These bits are compared with the bits
received in position one of the four FASs of the next
received submultiframe. This process takes place in
both directions of transmission.

When more than 914 CRC-4 errors (out of a possible

1000) are counted in a one second interval, the
framing algorithm will force a search for a new basic
frame alignment. See Frame Algorithm section for
more details.

The result of the comparison of the received CRC-4
remainder with the locally generated remainder will
be transported to the far end by the E-bits.
Therefore, if E1 = 0, a CRC-4 error was disco vered in
a submultiframe 1 received at the far end; and if E2 =
0, a CRC-4 error was discovered in a submultiframe
2 received at the far end. No submultiframe
sequence numbers or re-transmission capabilities
are supported with layer 1 PCM 30 protocol. See
ITU-T G.704 and G.706 for more details on the
operation of CRC-4 and E-bits.

There are two CRC multiframe alignment algorithm
options selected by the AUTC control bit (address
10H, page 01H). When AUTC is zero, automatic
CRC-to-non-CRC interworking is selected. When
AUTC is one and ARAI is low, if CRC-4 multiframe
alignment is not found in 400 msec, the transmit RAI
will be continuously high until CRC-4 multiframe
alignment is achieved.

The control bit for transmit E bits (TE, address 11H
of page 01H) will have the same function in both
states of AUTC. That is, when CRC-4
synchronization is not achieved the state of the
transmit E-bits will be the same as the state of the
TE control bit. When CRC-4 synchronization is
achieved the transmit E-bits will function as per ITU­T G.704. Table 12 outlines the operation of the
AUTC, ARAI and TALM control bits of the MT9074.

CAS Signalling Multiframing in E1 mode

The purpose of the signalling multiframing algorithm
is to provide a scheme that will allow the association
of a specific ABCD signalling nibble with the
appropriate PCM 30 channel. Time slot 16 is
reserved for the communication of Channel
Associated Signalling (CAS) information (i.e., ABCD
signalling bits for up to 30 channels). Refer to ITU-T

AUTC ARAI TALM Description

0 0 X Automatic CRC-interworking is activated. If no valid CRC MFAS is being

received, transmit RAI will flick er high with e very reframe (8msec.), this cycle
will continue for 400 msec., then transmit RAI will be low continuously. The
device will stop searching for CRC MFAS, continue to transmit CRC-4
remainders, stop CRC-4 processing, indicate CRC-to-non-CRC operation
and transmit E-bits to be the same state as the TE control bit (page 01H,

address 16H).
0 1 0 Automatic CRC-interworking is activated. Transmit RAI is low continuously.
0 1 1 Automatic CRC-interworking is activated. Transmit RAI is high continuously.
1 0 X Automatic CRC-interworking is de-activated. If no valid CRC MFAS is being

received, transmit RAI flickers high with every reframe (8 msec.), this cycle

continues for 400 msec, then transmit RAI becomes high continuously. The

device continues to search for CRC MFAS and transmit E-bits are the same

state as the TE control bit. When CRCSYN = 0, the CRC MFAS search is

terminated and the transmit RAI goes low.
1 1 0 Automatic CRC-interworking is de-activated. Transmit RAI is low

continuously.
1 1 1 Automatic CRC-interworking is de-activated. Transmit RAI is high

continuously.

18

Table 12 - Operation of AUTC, ARAI and TALM Control Bits (E1 Mode)

Advance Information MT9074

G.704 and G.732 for more details on CAS
multiframing requirements.

A CAS signalling multiframe consists of 16 basic
frames (numbered 0 to 15), which results in a
multiframe repetition rate of 2 msec. It should be
noted that the boundaries of the signalling
multiframe may be completely distinct from those of
the CRC-4 multiframe. CAS multiframe alignment is
based on a multiframe alignment signal (a 0000 bit
sequence), which occurs in the most significant
nibble of time slot 16 of basic frame 0 of the CAS
multiframe. Bit 6 of this time slot is the multiframe
alarm bit (usually designated Y). When CAS
multiframing is acquired on the receive side, the
transmit Y-bit is zero; when CAS multiframing is not
acquired, the transmit Y-bit is one. Bits 5, 7 and 8
(usually designated X) are spare bits and are
normally set to one if not used.

Time slot 16 of the remaining 15 basic frames of the
CAS multiframe (i.e., basic frames 1 to 15) are
reserved for the ABCD signalling bits for the 30
payload channels. The most significant nibbles are
reserved for channels 1 to 15 and the least
significant nibbles are reserved for channels 16 to

30. That is, time slot 16 of basic frame 1 has ABCD
for channel 1 and 16, time slot 16 of basic frame 2
has ABCD for channel 2 and 17, through to time slot
16 of basic frame 15 has ABCD for channel 15 and

30.

MT9074 Access and Control

The Control Port Interface

The control and status of the MT9074 is achieved
through a non-multiplexed parallel microprocessor
port. The parallel port may be configured for
Motorola style control signals (by setting pin INT/
MOT low) or Intel style control signals (by setting pin
INT/MOT high).

Control and Status Register Access

The controlling microprocessor gains access to
specific registers of the MT9074 through a two step
process. First, writing to the Command/Address
Register (CAR) selects one of the 15 pages of
control and status registers (CAR address: AC4 = 0,
AC3-AC0 = don't care, CAR data D7 - D0 = page
number). Second, each page has a maximum of 16
registers that are addressed on a read or write to a
non-CAR address (non-CAR: address AC4 = 1, AC3­AC0 = register address, D7-D0 = data). Once a page
of memory is selected, it is only necessary to write to
the CAR when a different page is to be accessed.
See the AC Electrical Characteristics section.

Please note that for microprocessors with read/write
cycles less than 200 ns, a wait state or a dummy
operation (for C programming) between two

Page Address

D7 - D

0

00000001 (01H) Master
00000010 (02H) R/W
00000011 (03H) Master
00000100 (04H) R/W
00000101 (05H) Per Channel Transmit Signalling R/W CSTi
00000110 (06H) Per Channel Transmit Signalling R/W CSTi
00000111 (07H) Per Time Slot Control - - ­00001000 (08H) Per Time Slot Control R/W - - ­00001001 (09H) Per Channel Receive Signalling R/W CSTo
00001010 (0AH) Per Channel Receive Signalling R/W CSTo
00001011 (0BH) HDLC0 Control and Status R/W --­00001011 (0CH) HDLC1 Control and Status R/W ---

Control

Status

Register Description

Table 13 - Page Summary

Processor

Access

R/W

R

ST-BUS

Access

- - -

- - -

19

MT9074 Advance Information

successive read/write operations to the HDLC FIFO
is required.

Table 13 associates the MT9074 control and status
pages with access and page descriptions.

Identification Code

The MT9074 shall be identified by the code
10101111, read from the identification code status
register (page 03H, address 1FH).

ST-BUS Streams

In T1 mode, there is one control and one status ST­BUS stream that can be used to program / access
channel associated signalling nibbles. CSTo contains
the received channel associated signalling bits, and
for those channels whose Per Time Slot Control word
bit 1 "RPSIG" is set low, CSTi is used to control the
transmit channel associated signalling. The DSTi
and DSTo streams contain the transmit and receive
voice and digital data. Only 24 of the 32 ST-BUS
channels are used for each of DSTi, DSTo, CSTi and
CSTo. In each case individual channel mapping is as
illustrated in Table , “Table 6 - STBUS vs. DS1 to
Channel Relationship(T1),” on page 14.

In E1 mode, the ST-BUS stream can also be used to
access channel associated signalling nibbles. CSTo
contains the received channel associated signalling
bits (e.g., ITU-T R1 and R2 signalling),and for those
channels whose Per Time Slot Control word bit 1
"RPSIG" is set low, CSTi is used to control the
transmit channel associated signalling. The DSTi
and DSTo streams contain the transmit and receive
voice and digital data.

Only 30 of the 32 ST-BUS channels are used for
each of DSTi, DSTo, CSTi and CSTo. In each case
individual channel mapping is as illustrated in Table
10 Time slot to Channel Relationship.

Reset Operation (Initialization)

The MT9074 can be reset using the hardware
RESET pin (see pin description for external reset
circuit requirements) for T1 and (pin 11 in PLCC, pin
84 in MQFP) or the software reset bit RST (page 1H,
address 1AH) for E1/T1. When the device emerges
from its reset state it will begin to function with the
default settings described in Table 14 (T1) and Table
15 (E1), all control registers default to 00H. A reset
operation takes 1 full frame (125 us) to complete.

Function Status

Mode D4

Loopbacks Deactivated

SLC-96 Deactivated

Zero Coding Deactivated

Line Codes Deactivated

Data Link Serial Mode

Signalling CAS Registers

AB/ABCD Bit

Debounce

Interrupts masked

Error Insertion Deactivated

HDLC0,1 Deactivated
Counters Cleared

Transmit Data All Ones

Table 14 - Reset Status(T1)

Function Status

Mode Termination

Loopbacks Deactivated

Transmit FAS Cn0011011

Transmit non-FAS 1/Sn1111111

Transmit MFAS (CAS) 00001111

Data Link Deactivated

CRC Interworking Activated

Signalling CAS Registers

ABCD Bit Debounce Deactivated

Interrupts Masked

RxMF Output Signalling Multiframe

Error Insertion Deactivated

HDLCs Deactivated

Counters Cleared

Transmit Data All Ones

Table 15 - Reset Status(E1)

Deactivated

Transmit Data All Ones (TxAO)
Operation

The TxAO (Transmit all ones) pin allows the PRI
interface to transmit an all ones signal from the point
of power-up without writing to any control registers.
During this time the IRQ pin is tristated. After the
interface has been initialized normal operation can
take place by making TxAO high.

20

Advance Information MT9074

Data Link Operation

Data Link Operation in E1 mode

In E1 mode MT9074 has a user defined 4, 8, 12, 16
or 20 kbit/s data link for transport of maintenance
and performance monitoring information across the
PCM 30 link. This channel functions using the Sa bits
(Sa4~Sa8) of the PCM 30 timeslot zero non-frame
alignment signal (NFAS). Since the NFAS is
transmitted every other frame - a periodicity of 250
microseconds - the aggregate bit rate is a multiple of
4 kb/s. As there are five Sa bits independently
available for this data link, the bit rate will be 4, 8, 12,
16 or 20 kb/s, depending on the bits selected for the
Data Link (DL).

The Sa bits used for the DL are selected by setting
the appropriate bits, Sa4~Sa8, to one in the Data Link
Select Word (page 01H, address 17H, bits 4-0).
Access to the DL is provided by pins TxDLCLK,
TxDL, RxDLCLK and RxDL, which allow easy
interfacing to an external controller.

Data Link Operation in T1 mode

SLC-96 and ESF protocol allow for carrier messages
to be embedded in the overhead bit position. The
MT9074 provides 3 separate means of controlling
these data links. See Data Link and Rx Equalization
Control Word - address 12H, page 1H.

• The data links (transmit and receive) may be
sourced (sunk) from an external controller using
dedicated pins on the MT9074 in T1 mode (enabled
by setting the bit 7 - EDL of the Data link Control
Word).

• Bit - Oriented Messages may be transmit and
received via a dedicated TxBOM register (page 1H,
address 13H) and a RxBOM (page 3H, address
15H). Transmission is enabled by setting bit 6 ­BIOMEn in the Data link Control Word. Bit - oriented
messages may be periodically interrupted (up to
once per second) for a duration of up to 100
milliseconds. This is to accommodate bursts of
message - oriented protocols. See Table 16 for
message structure.

Data to be transmit onto the line in the Sa bit position
is clocked in from the TxDL pad (pin 65 in PLCC, pin
62 in MQFP) with the clock TxDLCLK (pin 64 in
PLCC, pin 61 in MQFP). Although the aggregate
clock rate equals the bit rate, it has a nominal pulse
width of 244 ns, and it clocks in the TxDL as if it were
a 2.048 Mb/s data stream. The clock can only be
active during bit times 4 to 0 of the STBUS frame.
The TxDL input signal is clocked into the MT9074 by
the rising edge of TxDLCLK. If bits are selected to be
a part of the DL, all other programmed functions for
those Sa bit positions are overridden.

The RxDLCLK signal (pin 39 in PLCC, pin 20 in
MQFP) is derived from the receive extracted clock
and is aligned with the receive data link output RxDL.
The HDB3 decoded receive data, at 2.048 Mbit/s, is
clocked out of the device on pin RxDL (pin 40 in
PLCC, pin 21 in MQFP). In order to facilitate the
attachment of this data stream to a Data Link
controller, the clock signal RxDLCLK consists of
positive pulses, of nominal width of 244 ns, during
the Sa bit cell times that are selected for the data
link. Again, this selection is made by programming
address 17H of master control page 01H. No DL
data will be lost or repeated when a receive frame
slip occurs. See the AC Electrical Characteristics for
timing requirements.

• An internal HDLC controller may be attached to the
data link.

External Data Link

In T1 mode MT9074 has two pairs of pins (TxDL and
TxDLCLK, RxDL and RxDLCLK) dedicated to
transmitting and receiving bits in the selected
overhead bit positions. Pins TxDLCLK and RxDLCLK
are clock outputs available for clocking data into the
MT9074 (for transmit) or exter nal device (for receive
information). Each clock operates at 4 Khz. In the
SLC-96 mode the optional serial data link is
multiplexed into the Fs bit position. In the ESF mode
the serial data link is multiplexed into odd frames, i.e.
the FDL bit positions.

Bit - Oriented Messaging

In T1 mode MT9074 Bit oriented messaging may be
selected by setting bit 6 (BIOMEn) in the Data Link
Control Word (page 1H, address 12H). The transmit
data link will contain the repeating serial data stream
111111110xxxxxx0 where the byte 0xxxxxx0
originates from the user programmed register
"Transmit Bit Oriented Message" - page 1H address
13H. The receive BIOM register "Receive Bit
Oriented Message" - page 3H, address 15H, will
contain the last received valid message (the
0xxxxxx0 portion of the incoming serial bit stream).
To prevent spurious inputs from creating false

21

MT9074 Advance Information

Octet # 8 7 6 54321Content

1 F L A G 01111110
2 S A P I C / R EA 00111000 or

00111010
3 T E I EA 00000001
4 C O N T R O L 00000011
5 G3LVG4U1U2G5SLG6t0
6FESELBG1RG2NmNIt0
7 G3LVG4U1U2G5SLG6t0-1
8FESELBG1RG2NmNIt0-1
9 G3LVG4U1U2G5SLG6t0-2

10 FE SE LB G1 R G2 Nm NI t0-2
11 G3 LV G4 U1 U2 G5 SL G6 t0-3
12 FE SE LB G1 R G2 Nm NI t0-3
13 F C S VARIABLE
14

Table 16 - Message Oriented Performance Report Structure (T1.403 and T1.408)

Note: ADDRESS INTERPRETATION

00111000 SAPI = 14, C/R = 0 (CI) EA = 0

00111010 SAPI = 14, C/R = 1(Carrier) EA = 0
00000001 TEI = 0, EA =1

CONTROL INTERPRETATION

00000011 Unacknowledged Information Transfer

ONE SECOND REPORT INTERPRETATION

G1 = 1 CRC Error Event =1

G2 =1 1 < CRC Error Event < 5
G3 =1 5 < CRC Error Event < 10
G4 =1 10 < CRC Error Event < 100
G5 =1 100 < CRC Error Event < 319
G6 =1 CRC Error Event > 320
SE = 1 Severely - Errored Framing Event >=1
FE = 1 Frame Synchronization Bit Error Event >=1
LV = 1 Line code Violation Event >=1
SL = 1 Slip Event >=1
LB = 1 Payload Loopback Activated
U1,U2 = 0 Under Study for sync.
R = 0 Reserved - set to 0
NmNI = 00, 01, 10, 11 One Second Module 4 counter

FCS INTERPRETATION

VARIABLE CRC16 Frame Check Sequence

22

Advance Information MT9074

messages, a new message must be present in 7 of
the last 10 appropriate byte positions before being
loaded into the receive BIOM register. When a new
message has been received, a maskable interrupt
(maskable by setting bit 1 low in Interrupt Mask Word
Three - page 1H, address 1EH) may occur.

Dual HDLC

MT9074 has two embedded HDLC controllers
(HDLC0, HDLC1) each of which includes the
following features:

• Independent transmit and receive FIFO's;

• Receive FIFO maskable interrupts for nearly
full (programmable interrupt levels) and
overflow conditions;

• Transmit FIFO maskable interrupts for
nearly empty (programmable interrupt
levels) and underflow conditions;

• Maskable interrupts for transmit end-of­packet and receive end-of-packet;

• Maskable interrupts for receive bad-frame
(includes frame abort);

• Transmit end-of-packet and frame-abort
functions.

mode. It should be noted that the AIS16S function
will always be active and the TAIS16 (page 01H,
address 11h) function will override all other transmit
signalling.

HDLC1 can be selected by setting the control bit
HDLC1. When this bit is zero all interrupts from
HDLC1 are masked.

HDLC Description

The HDLC handles the bit oriented packetized data
transmission as per X.25 level two protocol defined
by ITU-T. It provides flag and abort sequence
generation and detection, zero insertion and
deletion, and Frame Check Sequence (FCS)
generation and detection. A single byte, dual byte
and all call address in the received frame can be
recognized. Access to the receive FCS and inhibiting
of transmit FCS for terminal adaptation are also
provided. Each HDLC controller has a 128 byte deep
FIFO associated with it. The status and interrupt
flags are programmable for FIFO depths that can
vary from 16 to 128 bytes in steps of 16 bytes. These
and other features are enabled through the HDLC
control registers on page 0BH and 0CH.

HLDC0 Functions

In T1 mode ESF Data Link (DL) can be connected to
internal HDLC0, operating at a bit rate of 4 kbits/sec.
HDLC0 can be activated by setting the control bit 5,
address 12H in Master Control Page 0. Interrupts
from HDLC0 are masked when it is disconnected.

In E1 mode when connected to the Data Link (DL)
HDLC0 will operate at a selected bit rate of 4, 8, 12,
16 or 20 kbits/sec. HDLC0 can be selected by setting
the control bit HDLC0 (page 01H, address 12H).
When this bit is zero all interrupts from HDLC0 are
masked. For more information refer to following
sections.

HDLC1 Functions

In T1 mode DS1 channel 24 can be connected to
HDLC1, operating at 56 or 64 Kb/s. HDLC1 can be
activated by setting the control bit HDLC1 (page
01H, address 12H). Setting control bit H1R64
(address 12 H on page 01H) high selects 64 Kb/s
operation for HDLC1. Setting this bit low selects 56
Kb/s for HDLC1. Interrupts from HDLC1 are masked
when it is disconnected.

In E1 mode this controller may be connected to time
slot 16 under Common Channel Signalling (CCS)

HDLC Frame structure

In T1 mode or E1 mode a valid HDLC frame begins
with an opening flag, contains at least 16 bits of
address and control or information, and ends with a
16 bit FCS followed by a closing flag. Data formatted
in this manner is also referred to as a “packet”. Refer
to Table 17: HDLC Frame Format

Flag (7E) Data Field FCS Flag (7E)

One Byte

01111110

Table 17 - HDLC Frame Format

All HDLC frames start and end with a unique flag
sequence “01111110”. The transmitter generates
these flags and appends them to the packet to be
transmitted. The receiver searches the incoming
data stream for the flags on a bit- by-bit basis to
establish frame synchronization.

The data field consists of an address field, control
field and information field. The address field consists
of one or two bytes directly following the opening
flag. The control field consists of one byte directly
following the address field. The information field
immediately follows the control field and consists of

n Bytes

n ≥ 2

Two

Bytes

One Byte

01111110

23

MT9074 Advance Information

N bytes of data. The HDLC does not distinguish
between the control and information fields and a
packet does not need to contain an infor mation field
to be valid.

The FCS field, which precedes the closing flag,
consists of two bytes. A cyclic redundancy check
utilizing the CRC-CCITT standard generator
polynomial “X16+X12+X5+1” produces the 16-bit
FCS. In the transmitter the FCS is calculated on all
bits of the address and data field. The complement
of the FCS is transmitted, most significant bit first, in
the FCS field. The receiver calculates the FCS on
the incoming packet address, data and FCS field and
compares the result to “F0B8”. If no transmission
errors are detected and the packet between the flags
is at least 32 bits in length then the address and data
are entered into the receive FIFO minus the FCS
which is discarded.

Data Transparency (Zero Insertion/Deletion)

Transparency ensures that the contents of a data
packet do not imitate a flag, go-ahead, frame abort
or idle channel. The contents of a transmitted frame,
between the flags, is examined on a bit-by-bit basis
and a 0 bit is inserted after all sequences of 5
contiguous 1 bits (including the last five bits of the
FCS). Upon receiving five contiguous 1s within a
frame the receiver deletes the following 0 bit.

Invalid Frames

Frame Abort

The transmitter will abort a current packet by
substituting a zero followed by seven contiguous 1s
in place of the normal packet. The receiver will abort
upon reception of seven contiguous 1s occurring
between the flags of a packet which contains at least
26 bits.

Note that should the last received byte before the
frame abort end with contiguous 1s, these are
included in the seven 1s required for a receiver
abort. This means that the location of the abort
sequence in the receiver may occur before the
location of the abort sequence in the originally
transmitted packet. If this happens then the last data
written to the receive FIFO will not correspond
exactly with the last byte sent before the frame abort.

Interframe Time Fill and Link Channel States

When the HDLC transmitter is not sending packets it
will wait in one of two states

• Interframe Time Fill state: This is a
continuous series of flags occurring between
frames indicating that the channel is active
but that no data is being sent.

• Idle state: An idle Channel occurs when at
least 15 contiguous 1s are transmitted or
received.

In both states the transmitter will exit the wait state
when data is loaded into the transmitter FIFO.

A frame is invalid if one of the following four
conditions exists (Inserted zeros are not part of a
valid count):

• If the FCS pattern generated from the
received data does not match the “F0B8”
pattern then the last data byte of the packet
is written to the received FIFO with a ‘bad
packet’ indication.

• A short frame exists if there are less than 25
bits between the flags. Short frames are
ignored by the receiver and nothing is written
to the receive FIFO.

• Packets which are at least 25 bits in length
but less than 32 bits between the flags are
also invalid. In this case the data is written to
the FIFO but the last byte is tagged with a
“bad packet” indication.

• If a frame abort sequence is detected the
packet is invalid. Some or all of the current
packet will reside in the receive FIFO,
assuming the packet length before the abort
sequence was at least 26 bits long.

Go-Ahead

A go ahead is defined as the pattern "011111110"
(contiguous 7Fs) and is the occurrence of a frame
abort sequence followed by a zero, outside of the
boundaries of a normal packet. Being able to
distinguish a proper (in packet) frame abort
sequence from one occurring outside of a packet
allows a higher level of signalling protocol which is
not part of the HDLC specifications.

HDLC Functional Description

The HDLC transceiver can be reset by either the
power reset input signal or by the HRST Control bit
in the test control register (software reset). When
reset, the HDLC Control Registers are cleared,
resulting in the transmitter and receiver being
disabled. The Receiver and Transmitter can be
enabled independent of one another through Control
Register 1. The transceiver input and output are
enabled when the enable control bits in Control
Register 1 are set. Transmit to receive loopback as

24

Advance Information MT9074

well as a receive to transmit loopback are also
supported. Transmit and receive bit rates and
enables can operate independently. In MT9074 the
transceiver can operate at a continuous rate
independent of RXcen and TXcen (free run mode) by
setting the Frun bit of Control Register 1.

Received packets from the serial interface are
sectioned into bytes by an HDLC receiver that
detects flags, checks for go-ahead signals, removes
inserted zeros, performs a cyclical redundancy
check (CRC) on incoming data, and monitors the
address if required. Packet reception begins upon
detection of an opening flag. The resulting bytes are
concatenated with two status bits (RQ9, RQ8) and
placed in a receiver first-in-first-out (Rx FIFO); a
buffer register that generates status and interrupts
for microprocessor read control.

In conjunction with the control circuitry, the
microprocessor writes data bytes into a Tx buffer
register (Tx FIFO) that generates status and
interrupts. Packet transmission begins when the
microprocessor writes a byte to the Tx FIFO. Two
status bits are added to the Tx FIFO for transmitter
control of frame aborts (FA) and end of packet (EOP)
flags. Packets have flags appended, zeros inserted,
and a CRC, also referred to as frame checking
sequence (FCS), added automatically during serial
transmission. When the Tx FIFO is empty and
finished sending a packet, Interframe Time Fill bytes
(continuous flags (7E hex)), or Mark Idle (continuous
ones) are transmitted to indicate that the channel is
idle.

HDLC Transmitter

Following initialization and enabling, the transmitter
is in the Idle Channel state (Mark Idle), continuously
sending ones. Interframe Time Fill state (Flag Idle) is
selected by setting the Mark idle bit in Control
Register 1 high. The Transmitter remains in either of
these two states until data is written to the Tx FIFO.
Control Register 1 bits EOP (end of packet) and FA
(Frame Abort) are set as status bits before the
microprocessor loads 8 bits of data into the 10 bit
wide FIFO (8 bits data and 2 bits status). To change
the tag bits being loaded in the FIFO, Control
Register 1 must be written to before writing to the
FIFO. However, EOP and FA are reset after writing to
the TX FIFO. The Transmit Byte Count Register may
also be used to tag an end of packet. The register is
loaded with the number of bytes in the packet and
decrements after every write to the Tx FIFO. When a
count of one is reached, the next byte written to the
FIFO is tagged as an end of packet. The register
may be made to cycle through the same count if the

packets are of the same length by setting Control
Register 2 bit Cycle.

If the transmitter is in the Idle Channel state when
data is written to the Tx FIFO, then an opening flag is
sent and data from Tx FIFO follows. Otherwise, data
bytes are transmitted as soon as the current flag byte
has been sent. Tx FIFO data bytes are continuously
transmitted until either the FIFO is empty or an EOP
or FA status bit is read by the transmitter. After the
last bit of the EOP byte has been transmitted, a 16­bit FCS is sent followed by a closing flag. When
multiple packets of data are loaded into Tx FIFO,
only one flag is sent between packets.

Frame aborts (the transmission of 7F hex), are
transmitted by tagging a byte previously written to
the Tx FIFO. When a byte has an FA tag, then an FA
is sent instead of that tagged byte. That is, all bytes
previous to but not including that byte are sent. After
a Frame Abort, the transmitter returns to the Mark
Idle or Interframe Time Fill state, depending on the
state of the Mark idle control bit.

Tx FIFO underrun will occur if the FIFO empties and
the last byte did not have either an EOP or FA tag. A
frame abort sequence will be sent when an underrun
occurs.

Below is an example of the transmission of a three
byte packet (’AA’ ’03’ ’77’ hex) (Interframe time fill).
TXcen can be enabled before or after this sequence.

(a) Write ’04’hex to Control Register 1

-Mark idle bit set

(b) Write ’AA’ hex to TX FIFO

-Data byte

(c) Write ’03’hex to TX FIFO

-Data byte

(d) Write ’34’hex to Control Register 1

-TXEN; EOP; Mark idle bits set

(e) Write ’77’hex to TX FIFO

-Final data byte

The transmitter may be enabled independently of the
receiver. This is done by setting the TXEN bit of the
Control Register. Enabling happens immediately
upon writing to the register. Disabling using TXen will
occur after the completion of the transmission of the
present packet; the contents of the FIFO are not
cleared. Disabling will consist of stopping the
transmitter clock. The Status and Interrupt Registers
may still be read and the FIFO and Control Registers
may be written to while the transmitter is disabled.
The transmitted FCS may be inhibited using the Tcrci
bit of Control Register 2. In this mode the opening

25

MT9074 Advance Information

flag followed by the data and closing flag is sent and
zero insertion still included, but no CRC. That is, the
FCS is injected by the microprocessor as part of the
data field. This is used in V.120 terminal adaptation
for synchronous protocol sensitive UI frames.

HDLC Receiver

After initialization and enabling, the receiver clocks in
serial data, continuously checking for Go-aheads (0
1111 1110), flags (0111 1110), and Idle Channel
states (at least fifteen ones). When a flag is
detected, the receiver synchronizes itself to the
serial stream of data bits, automatically calculating
the FCS. If the data length between flags after zero
removal is less than 25 bits, then the packet is
ignored so no bytes are loaded into Rx FIFO. When
the data length after zero removal is between 25 and
31 bits, a first byte and bad FCS code are loaded into
the Rx FIFO (see definition of RQ8 and RQ9 below).
For an error-free packet, the result in the CRC
register should match the HEX pattern of ’F0B8’
when a closing flag is detected.

If address recognition is required, the Receiver
Address Recognition Registers are loaded with the
desired address and the Adrec bit in the Control
Register 1 is set high. Bit 0 of the Address Registers
is used as an enable bit for that byte, thus allowing
either or both of the first two bytes to be compared to
the expected values. Bit 0 of the first byte of the
address received (address extension bit) will be
monitored to determine if a single or dual byte
address is being received. If this bit is 0 then a two
byte address is being received and then only the first
six bits of the first address byte are compared. An all
call condition is also monitored for the second
address byte; and if received the first address byte is
ignored (not compared with mask byte). If the
address extension bit is a 1 then a single byte
address is being received. In this case, an all call
condition is monitored for in the first byte as well as
the mask byte written to the comparison register and
the second byte is ignored. Seven bits of address
comparison can be realized on the first byte if this is
a single byte address by setting the Seven bit of
Control Register 2.

The following two Status Register bits (RQ8 and
RQ9) are appended to each data byte as it is written
to the Rx FIFO. They indicate that a good packet has
been received (good FCS and no frame abort), or a
bad packet with either incorrect FCS or frame abort.
The Status and Interrupt Registers should be read
before reading the Rx FIFO since status and
interrupt information correspond to the byte at the
output of the FIFO (i.e. the byte about to be read).
The Status Register bits are encoded as follows:

RQ9 RQ8 Byte status
1 1 last byte (bad packet)
0 1 first byte
1 0 last b yte (good packet)
0 0 packet byte

The end-of-packet-detect (EOPD) interrupt indicates
that the last byte written to the Rx FIFO was an EOP
byte (last byte in a packet). The end-of-packet-read
(EopR) interrupt indicates that the byte about to be
read from the Rx FIFO is an EOP byte (last byte in a
packet). The Status Register should be read to see if
the packet is good or bad before the byte is read.

A minimum size packet has an 8-bit address, an 8-bit
control byte, and a 16-bit FCS pattern between the
opening and closing flags (see Section 9.3.2). Thus,
the absence of a data transmission error and a frame
length of at least 32 bits results in the receiver
writing a valid packet code with the EOP byte into Rx
FIFO. The last 16 bits before the closing flag are
regarded as the FCS pattern and will not be
transferred to the receiver FIFO. Only data bytes
(Address, Control, Information) are loaded into the
Rx FIFO.

In the case of an Rx FIFO overflow, no clocking
occurs until a new opening flag is received. In other
words, the remainder of the packet is not clocked into
the FIFO. Also, the top byte of the FIFO will not be
written over. If the FIFO is read before the reception
of the next packet then reception of that packet will
occur. If two beginning of packet conditions
(RQ9=0;RQ8=1) are seen in the FIFO, without an
intermediate EOP status, then overflow occurred for
the first packet.

The receiver may be enabled independently of the
transmitter. This is done by setting the RXEN bit of
Control Register 1. Enabling happens immediately
upon writing to the register. Disabling using RXEN
will occur after the present packet has been
completely loaded into the FIFO. Disabling can occur
during a packet if no bytes have been written to the
FIFO yet. Disabling will consist of disabling the
internal receive clock. The FIFO, Status, and
Interrupt Registers may still be read while the
receiver is disabled. Note that the receiver requires a
flag before processing a frame, thus if the receiver is
enabled in the middle of an incoming packet it will
ignore that packet and wait for the next complete
one.

The receive CRC can be monitored in the Rx CRC
Registers. These registers contain the actual CRC
sent by the other transmitter in its original form; that
is, MSB first and bits inverted. These registers are

26

Advance Information MT9074

updated by each end of packet (closing flag)
received and therefore should be read when an end
of packet is receiv ed so that the next packet does not
overwrite the registers.

Slip Buffers

Slip Buffer in T1 mode

In T1 mode MT9074 contains two sets of slip buffers,
one on the transmit side, and one on the receive
side. Both sides may perform a controlled slip. The
mechanisms that govern the slip function are a
function of backplane timing and the mapping
between the ST-BUS channels and the DS1
channels. The slip mechanisms are different for the
transmit and receive slip buffers. The extracted 1.544
Mhz clock (E1.5o) and the internally generated
transmit 1.544 Mhz clock are distinct. Slips on the
transmit side are independent from slips on the
receive side.

The transmit slip buffer has data written to it from the
near end 2.048 Mb/s stream. The data is clocked out
of the buffer using signals derived from the transmit

1.544 Mhz clock. The transmit 1.544 Mhz clock is
always phase locked to the DSTi 2.048 Mb/s stream.
If the system 4.096 Mhz clock (C4b) is internally
generated (pin BS/LS low), then it is hard locked to

the 1.544 Mhz clock. No phase drift or wander can
exist between the two signals - therefore no slips will
occur. The delay through the transmit elastic buffer is
then fixed, and is a functions of the relative mapping
between the DSTi channels and the DS1 timeslots.
These delays vary with the position of the channel in
the frame. For example, DS1 timeslot 1 sits in the
elastic buffer for approximately 1 usec and DS1
timeslot 24 sits in the elastic buffer for approximately
32 usec.

If the system 4.096 Mhz clock (C4b) is externally
generated (pin BS/LS high), the transmit 1.544 Mhz
clock is phase locked to it, but the PLL is designed to
filter jitter present in the C4b clock. As a result phase
drift will result between the two signals. The delay
through the transmit elastic buffer will vary in
accordance with the input clock drift, as well as being
a function of the relative mapping between the DSTi
channels and the DS1 timeslots. If the read pointers
approach the write pointers (to within approximately
1 usec) or the delay through the transmit buffer
exceeds 218 usecs a controlled slip will occur. The
contents of a single frame of DS1 data will be
skipped or repeated; a maskable interrupt (masked
by setting bit 1 - TxSLPI high in Interrupt Mask Word
Zero - page 1H, address 1bH) will be generated, and
the status bit TSLIP (page 3H, address 17H) of MSB
Transmit Slip Buffer register will toggle. The direction
of the slip is indicated by bit 6 of the same register

0 uS

Write

Pointer

Read Pointer

221 uS

512 Bit

188 uS

Read Vectors
Minimum Delay

Write Vectors

Read Vectors - Maximum Delay

Elastic

Store

129 uS

Read Pointer

4 uS

Frame 0 Frame 1

Read Pointer

92 uS

Wander Tolerance

62 uS

92 uS

96 uS

Read Pointer

Frame 0 Frame 1

Frame 0 Frame 1

Figure 12 - Read and write pointers in the transmit slip buffers

27

MT9074 Advance Information

(TSLPD). The relative phase delay between the
system frame boundary and the transmit elastic
frame read boundary is measured every frame and
reported in the Transmit Slip Buffer Delay register­(page 3H, address 17H). In addition the relative
offset between these frame boundaries may be
programmed by writing to this register. Every write to
Transmit Elastic Buffer Set Delay Word resets the
transmit elastic frame count bit TxSBMSB (address
17H, page 3H). After a write the delay through the
slip buffer is less than 1 frame in duration. Each write
operation will result in a disturbance of the transmit
DS1 frame boundary, causing the far end to go out of
sync. Writing BC (hex) into the TxSBDLY register
maximizes the wander tolerance before a controlled
slip occurs. Under normal operation no slips should
occur in the transmit path. Slips will only occur if the
input C4b clock has excess wander, or the Transmit
Elastic Buffer Set Delay Word register is initialized
too close to the slip pointers after system
initialization.

The two frame receive elastic buffer is attached
between the 1.544 Mbit/s DS1 receive side and the

2.048 Mbit/s ST-BUS side of the MT9074. Besides
performing rate conversion, this elastic buffer is
configured as a slip buffer which absorbs wander
and low frequency jitter in multi-trunk applications.
The received DS1 data is clocked into the slip buffer
with the E1.5o clock and is clocked out of the slip
buffer with the system C4b clock. The E1.5o
extracted clock is generated from, and is therefore
phase-locked with, the receive DS1 data. In the case
of Internal mode (pin BS/LS set low) operation, the
E1.5o clock may be phase-loc k ed to theC4b clock by
an internal phase locked loop (PLL). Therefore, in a
single trunk system the receive data is in phase with
the E1.5o clock, the C4b clock is phase locked to the
E1.5o clock, and the read and write positions of the
slip buffer track each other.

tolerance). The MT9074 will allow 92 usec (140 UI,
DS1 unit intervals) of wander and low frequency jitter
before a frame slip will occur.

When the C4b and the E1.5o clocks are not phase­locked, the rate at which data is being written into the
slip buffer from the DS1 side may differ from the rate
at which it is being read out onto the ST-BUS. If this
situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full DS1 frame is either repeated or lost. All frame
slips occur on frame boundaries.

The minimum delay through the receive slip buffer is
approximately 1 usec and the maximum delay is
approximately 249 uS. Figure 13 illustrates the
relationship between the read and write pointers of
the receive slip buffer (contiguous time slot
mapping). Measuring clockwise from the write
pointer, if the read page pointer comes within 8 usec
of the write page pointer a frame slip will occur,
which will put the read page pointer 157 usec from
the write page pointer. Conversely, if the read page
pointer moves more than 249 usec from the write
page pointer, a slip will occur, which will put the read
page pointer 124 usec from the write page pointer.
This provides a worst case hysteresis of 92 usec
peak = 142 U.I.

The RSLIP and RSLPD status bits (page 3H,
address 13H, bits 7 and 6 respectively) give
indication of a receive slip occurrence and direction.
A maskable interrupt RxSLPI (page 1H, address
1BH, bit 0 - set high to mask) is also provided. RSLIP
changes state in the event of a slip. If RSLPD=0, the
slip buffer has overflowed and a frame was lost; if
RSLPD=1, an underflow condition occurred and a
frame was repeated

In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network synchronizer, which will function as
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the DS1 signals from the network are
synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the C1.50
clocks of non-synchronized trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus. Network standards state that, within
limits, trunk interfaces must be able to receive error­free data in the presence of jitter and wander (refer
to network requirements for jitter and wander

28

Slip Buffer in E1 mode

In E1 mode in addition to the elastic buffer in the jitter
attenuator(JA), another elastic buffer (two frames
deep) is present, attached between the receive side
and the ST-BUS (or GCI Bus) side of the MT9074 in
E1 mode. This elastic buffer is configured as a slip
buffer which absorbs wander and low frequency jitter
in multi-trunk applications. The received PCM 30
data is clocked into the slip buffer with the E1.5o
clock and is clocked out of the slip buffer with the
C4b clock. The E1.5o extracted clock is generated
from, and is therefore phase-locked with, the receive
PCM 30 data. In normal operation, the C4b clock will
be phase-locked to the E1.5o clock by a phase
locked loop (PLL). Therefore, in a single trunk

Advance Information MT9074

system the receive data is in phase with the E1.5o
clock, the C4b clock is phase-locked to the E1.5o
clock, and the read and write positions of the slip
buffer will remain fixed with respect to each other.

In a multi-trunk slave or loop-timed system (i.e.,
PABX application) a single trunk will be chosen as a
network synchronizer, which will function as
described in the previous paragraph. The remaining
trunks will use the system timing derived from the
synchronizer to clock data out of their slip buffers.
Even though the PCM 30 signals from the network
are synchronous to each other, due to multiplexing,
transmission impairments and route diversity, these
signals may jitter or wander with respect to the
synchronizing trunk signal. Therefore, the E1.5o
clocks of non-synchronizer trunks may wander with
respect to the C1.50 clock of the synchronizer and
the system bus.

Network standards state that, within limits, trunk
interfaces must be able to receive error-free data in
the presence of jitter and wander (refer to network
requirements for jitter and wander tolerance). The
MT9074 will allow a maximum of 26 channels (208
UI, unit intervals) of wander and low frequency jitter
before a frame slip will occur.

The minimum delay through the receive slip buffer is
approximately two channels and the maximum delay
is approximately 60 channels (see Figure 14).

When the C4b and the E1.5o clocks are not phase­locked, the rate at which data is being written into the
slip buffer from the PCM 30 side may differ from the
rate at which it is being read out onto the ST-BUS. If
this situation persists, the delay limits stated in the
previous paragraph will be violated and the slip
buffer will perform a controlled frame slip. That is, the
buffer pointers will be automatically adjusted so that
a full PCM 30 frame is either repeated or lost. All
frame slips occur on PCM 30 frame boundaries.

Two status bits, RSLIP and RSLPD (page03H,
address13H) give indication of a slip occurrence and
direction. RSLIP changes state in the event of a slip.
If RSLPD=0, the slip buffer has overflowed and a
frame was lost; if RSLPD=1, an underflow condition
occurred and a frame was repeated. A maskable
interrupt SLPI (page 01H, address 1BH) is also
provided.

Figure 14 illustrates the relationship between the
read and write pointers of the receive slip buffer.
Measuring clockwise from the write pointer, if the
read pointer comes within two channels of the write
pointer a frame slip will occur, which will put the read
pointer 34 channels from the write pointer.
Conversely, if the read pointer moves more than 60

Write

Pointer

Read Pointer

249 uS

512 Bit

188 uS

Read Pointer

Read Vectors
Minimum Delay

Write Vectors

Read Vectors - Maximum Delay

Elastic

Store

157 uS

0 uS

Read Pointer

Frame 0 Frame 1

Read Pointer

32 uS

62 uS

92 uS

124 uS

Frame 0 Frame 1

XXX XXX

92 uS

Wander Tolerance

Frame 0 Frame 1

XXX XXX

Figure 13 - Read and write pointers in the receive slip buffers

29

MT9074 Advance Information

channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 channels peak (26 channels peak-to-peak) or a
wander tolerance of 208 UI.

Framing Algorithm

Frame Alignment in T1 Mode

In T1 mode MT9074 will synchronize to DS1 lines
formatted with either the D4 or ESF protocol. In
either mode the framer maintains a running 3 bit
history of received data for each of the candidate bit
positions. Candidate bit positions whose incoming
patterns fail to match the predicted pattern (based on
the 3 bit history) are winnowed out. If, after a 10 bit
history has been examined, only one candidate bit
position remains within the framing bit period, the
receive side timebase is forced to align to that bit
position. If no candidates remain after a 10 bit
history, the process is re-initiated. If multiple
candidates exist after a 24 bit history timeout period,
the framer forces the receive side timebase to
synchronize to the next incoming valid candidate bit
position. In the event of a reframe, the framer starts
searching at the next bit position over. This prevents
persistent locking to a mimic as the controller may
initiate a software controlled reframe in the event of
locking to a mimic.

multiframer alignment is forced at the same time as
terminal frame alignment. If only Ft bits are checked,
multiframe alignment is forced separately, upon
detection of the Fs bit history of 00111 (for normal
D4 trunks) or 000111000111 (for SLC-96 trunks).
For D4 trunks, a reframe on the multiframe alignment
may be forced at any time without affecting terminal
frame alignment.

In ESF mode the circuit will optionally confirm the
CRC-6 bits before forcing a new frame alignment.
This is programmed by setting control bit CXC high
(bit 5 of the Framing Mode Select Word, page 1H,
address 10H). A CRC-6 confirmation adds a
minimum of 6 milliseconds to the reframe time. If no
CRC-6 match is found after 16 attempts, the framer
moves to the next valid candidate bit position
(assuming other bit positions contain a match to the
framing pattern) or re-initiates the whole framing
procedure (assuming no bit positions have been
found to match the framing pattern).

The framing circuit is off - line. During a reframe, the
rest of the circuit operates synchronous with the last
frame alignment. Until such time as a new frame
alignment is achieved, the signalling bits are frozen
in their states at the time that frame alignment was
lost, and error counting for Ft, Fs, ESF framing
pattern or CRC-6 bits is suspended.

Frame Alignment in E1 mode

Under software control the framing criteria may be
tuned (see Framing Mode Select Register, page 1H,
address 10H). Selecting D4 framing invites a further
decision whether or not to include a cross check of
Fs bits along with the Ft bits. If Fs bits are checked
(by setting control bit CXC high - bit 5 of the Framing
Mode Select Word, page 1H, address 10H),

Write

Read Pointer

60 CH 2 CH

512 Bit

47 CH 15 CH

Read Pointer

Elastic

Store

34 CH 28 CH

Pointer

Read Pointer

Read Pointer

In E1 mode MT9074 contains three distinct framing
algorithms: basic frame alignment, signalling
multiframe alignment and CRC-4 multiframe
alignment. Figure 17 is a state diagram that
illustrates these algorithms and how they interact.

13 CH

Wander Tolerance

26 Channels

-13 CH

30

Figure 14 - Read and Write Pointers in the Slip Buffers