MITEL MT90500AL Datasheet

MT90500

Multi-Channel ATM AAL1 SAR

Features

• AAL1 Segmentation and Reassembly device compatible with Structured Data Transfer (SDT) as per ANSI T1.630 and ITU I.363 standards

• Transports 64kbps and N x 64kbps trafﬁc over ATM AAL1 cells (also over AAL5 or AAL0)

• Simultaneous processing of up to 1024 bidirectional Virtual Circuits

• Flexible aggregation capabilities (Nx64) to allow any combination of 64 kbps channels while maintaining frame integrity (DS0 grooming)

• Support for clock recovery - Adaptive Clock Recovery, Synchronous Residual Time Stamp (SRTS), or external

• Primary UTOPIA port (Level 1, 25 MHz) for connection to external PHY devices with data throughput of up to 155 Mbps

• Secondary UTOPIA port for connection to an external AAL5 SAR processor, or for chaining multiple MT90500 devices

• 16-bit microprocessor port, conﬁgurable to Motorola or Intel timing

• TDM bus provides 16 bidirectional serial TDM

DS5171 ISSUE 4 April 1999

Ordering Information

MT90500AL 240 Pin Plastic QFP

-40 to +85 C

streams at 2.048, 4.096, or 8.192 Mbps for up to 2048 TDM 64 kbps channels

• Compatible with ST-BUS, MVIP, H-MVIP and SCSA interfaces

• Supports master and slave TDM bus clock operation

• Loopback function at TDM bus interface

• Local TDM bus provides clocks, input pin and output pin for 2.048 Mbps operation

• Master clock rate up to 60 MHz

• Dual rails (3.3V for power minimization, 5V for standard I/O)

• IEEE1149 (JTAG) interface

To/From External PHY

From External ATM SAR

Main UTOPIA Interface

Secondary UTOPIA Interface

UTOPIA

MUX

UTOPIA

UTOPIA Module

Lookup

Tables

Boundary Scan

Control Structures

and Circular Buffers

External Memory Controller

AAL1

SAR

AAL1

SAR

JTAG

Interface

TX / RX

External Synchronous SRAM

TDM Module

TDM Bus

Interface

Internal

TDM

Frame Buffer

Microprocessor

16-bit Microprocessor Address

and Data Buses

TDM

Clock Logic

Clock

Recovery

Registers

Interface

TDM Bus 16 Lines 2048 x 64 kbps (max.)

Local TDM Bus 32 x 64 kbps in

32 x 64 kbps out Clock Signals

Figure A - MT90500 Block Diagram

MT90500

Applications

• B-ISDN (Broadband ISDN) systems requiring ﬂexible N x 64kbps transport

• Connecting TDM backplane to TDM backplane over ATM network (GO-MVIP MC4, or other)

• Systems requiring ANSI T1.630 Structured Data Transfer services for 1 to 122 TDM channels per VC

• Systems requiring ITU-T I.363.1 circuit transport over Structured Data Transfer for 1 to 96 TDM channels per VC

• Systems requiring AF-VTOA-0078.000 (ATM Forum CES v2.0) “Logical Nx64 Basic Service”

• Systems requiring AF-VTOA-0083.000 Voice and Telephony over ATM (CBR-AAL5).

• Mapping between CBR-AAL0, CBR-AAL5, and AAL1

• Mapping between CBR partially-ﬁlled cells and full cells

• Mapping between CBR single-voice cells and Nx64 cells

• ATM uplink for expansion of COs, PBXs, or open switching platforms using an adjunct ATM switch

• ATM Public Network access for PBX or CO

• ATM Edge Switches and CPE IntegratedAccess over ATM

• TDM trafﬁc transfer over an asynchronous cell bus

• Systems requiring Nx64 over CBR-AAL5.

Description

The MT90500 Multi-Channel AAL1 SAR is a highly integrated solution which allows systems based on a telecom bus to be interfaced to ATM networks using ATM Adaptation Layer 1 (AAL1), ATM Adaptation Layer 5 (AAL5) and ATM Adaptation Layer 0 (AAL0). The MT90500 can be connected directly to a ST-BUS time division multiplexed (TDM) backplane containing up to 1024 full duplex 64kbps channels. Up to 1024 bi-directional ATM VC connections can be simultaneously processed by the MT90500 AAL1 SAR device.

On the synchronous TDM bus side, the MT90500 device interfaces with sixteen bidirectional ST-BUS serial links operating at 2.048, 4.096 or 8.192 Mbps. TDM bus compatibility with MVIP-90, H-MVIP, and SCSA interfaces is also provided.

On the ATM interface side, the MT90500 device meets the ATM Forum standard UTOPIA Bus Level

1. This supports connection to a range of standard physical layer (PHY) transceivers.

The MT90500 provides a built-in UTOPIA multiplexer which allows external ATM cells to be multiplexed with internally-generated cells in the transmit direction. This feature can be used to connect another MT90500 (to expand the TDM bandwidth of the system to 4096 TDM channels), or to connect an external AAL5 SAR (to multiplex non-CBR ATM cell trafﬁc with the MT90500 CBR stream).

Primary

Off-the-shelf

ATM PHY

Device

16-bit CPU port for internal register and external memory programming

CPU

UTOPIA Port

Off-the-shelf SAR Device

(AAL5)

Local Memory

MT90500 AAL1 SAR

Secondary UTOPIA Port

External Synchronous SRAM

TDM Data, Clock and Sync Lines

MVIP-90 H-MVIP ST-BUS SCSA

IDL

Figure B - MT90500 Device Application Block Diagram

MT90500

Table of Contents

1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.3 ATM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2 Serial TDM Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 CBR ATM Cell Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5 UTOPIA Interface and Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.8 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.1 Module Level Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.2 TX_SAR Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.3 RX_SAR Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.4 UTOPIA Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.5 TDM Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.8.6 Timing Module Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9.1 RX_SAR Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9.2 TDM Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.9.3 Timing Recovery Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1 TDM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1 TDM Clock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1.1 TDM Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.1.2 REF8KCLK Selection Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.1.1.3 Main TDM Bus Timing and Clock Generation Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1.4 TDM Clock Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1.5 Clock Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.2 TDM Interface Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.1 Main TDM Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.2 TDM Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.3 Per-channel Output Enable Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.4 Local Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1.2.5 Local Bus Data Transfer Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.3 TDM Data to External Memory Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.1.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.3.2 Transmit Circular Buffer Control Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.1.3.3 Transmit Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.4 External Memory to TDM Data Output Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.1.4.2 External Memory to Internal Memory Control Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2 External Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.3 TX_SAR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3.1 TX_SAR Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3.1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.3.1.2 Supported ATM Cell Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

4.3.1.3 Transmit Event Scheduler Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3.1.3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3.1.3.2 Fixed TDM Payload Schedulers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.3.1.3.3 AAL1 Long/Short Schedulers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3.1.3.4 Other Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

MT90500

4.3.2 TX_SAR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.3.2.1 Transmit Event Schedulers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

4.3.2.2 Transmit Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.3.3 Non-CBR Data Cell Transmission Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

4.4 The RX_SAR Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.4.1 RX_SAR Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.4.2 RX_SAR Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.4.2.1 RX_SAR Control Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

4.4.2.2 RX_SAR Error Counter and Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

4.4.2.3 Receive Overruns and Underruns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

4.4.2.4 Lost Cell Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.5 UTOPIA Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.5.1 UTOPIA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

4.5.2 Cell Transmission and Mux Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.5.3 Receive Cell Selection Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

4.5.4 Non-CBR Data Cell Reception Ability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4.6 Clock Recovery from ATM Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.6.1 Adaptive Clock Recovery Sub-Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

4.6.2 SRTS Clock Recovery Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4.6.2.1 Transmit SRTS Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

4.6.2.2 Receive SRTS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

4.7 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.7.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.7.2 A Programming Example - How to Set Up a VC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.7.3 Microprocessor Access and Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.8 Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.8.1 Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

4.8.2 JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.8.3 Boundary Scan Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

4.8.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5.1 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5.1.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

5.1.2 Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

5.1.3 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

5.2 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5.2.1 Microprocessor Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5.2.2 TX_SAR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.2.3 RX_SAR Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.2.4 UTOPIA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

5.2.5 TDM Interface and Clock Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.2.6 TDM Time Slot Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

6. Electrical Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

6.1 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

6.2 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

6.2.1 Main TDM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

6.2.2 Local TDM Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120

6.2.3 CPU Interface - Accessing Registers and External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

6.2.4 Interface with External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

6.2.5 UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

6.2.5.1 Primary UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

6.2.5.2 Secondary UTOPIA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

6.2.6 SRTS User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

6.2.7 Message Channel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

6.2.8 Boundary-Scan Test Access Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

7. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

7.1 Board Level Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

MT90500

7.2 System Level Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

7.3 TDM Clock Recovery Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.3.2 SRTS Clock Recovery Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.3.3 Free-running Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.4 External Memory Space and Bandwidth Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

7.4.1 External Memory Space Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

7.4.2 Memory Structure Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.4.3 External Memory Bandwidth Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

7.5 CBR Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

7.6 Other Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154

7.6.1 Payload Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.6.2 TDM Switching and Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

7.6.3 DS0 Trunking, or Dynamic TDM channel re-mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.6.4 SCSA Message Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

8. Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

MT90500

List of Figures

Figure 1 - MT90500 Block Diagram...................................................................................................................12

Figure 2. Pin Connections................................................................................................................................26

Figure 3 - TDM Clock Selection and Generation Logic.....................................................................................29

Figure 4 - TDM Frame Buffer to External Memory Transfer..............................................................................33

Figure 5 - Transmit Circular Buffer Control Structure........................................................................................34

Figure 6 - External Memory to TDM Frame Buffer Transfer..............................................................................35

Figure 7 - External Memory to Internal Memory Control Structure....................................................................37

Figure 8 - Memory Read Pipeline Length..........................................................................................................38

Figure 9 - Logical Byte Address vs. Physical Address and Memory Banks......................................................39

Figure 10 - Read / Write Turnaround Cycles.......................................................................................................40

Figure 11 - Read / Read Turnaround Cycles.......................................................................................................41

Figure 11 - Read / Write turnaround Cycles........................................................................................................41

Figure 12 - AAL1 ATM Cell Format.....................................................................................................................42

Figure 13 - Partially-Filled AAL1 and CBR-AAL0 Cell Formats...........................................................................43

Figure 14 - CBR-AAL5 Cell Format....................................................................................................................44

Figure 15 - Transmit Event Scheduler.................................................................................................................49

Figure 17 - Transmit Control Structure Format (CBR-AAL5)...............................................................................50

Figure 16 - Transmit Control Structure Format (AAL1 & CBR-AAL0) .................................................................51

Figure 18 - a: Sample Three-Channel Transmit Control Structure (AAL1/CBR-AAL0).......................................53

Figure 18 - b: Sample One-Channel Transmit Control Structure (CBR-AAL5) ...................................................53

Figure 19 - Overview of CBR Data Transmission Process..................................................................................54

Figure 20 - VC Pointer For Scheduler-Controlled Non-CBR Data Cell ...............................................................55

Figure 21 - Transmit Non-CBR Data Cell Structure Format................................................................................56

Figure 22 - RX_SAR Control Structure................................................................................................................58

Figure 23 - Overrun and Underrun Situations.....................................................................................................60

Figure 24 - MT90500 Daisy Chain Example........................................................................................................62

Figure 25 - Mux and Internal FIFO Sub-Module Block Diagram .........................................................................63

Figure 26 - Receive Cell Selection Process........................................................................................................65

Figure 27 - MT90500 Cell Receive Process........................................................................................................66

Figure 28 - Look-up Table Non-CBR Data Entry.................................................................................................67

Figure 29 - Received Non-CBR Data Cell Internal Format..................................................................................68

Figure 30 - Overview of CBR Data Reception Process.......................................................................................69

Figure 31 - Adaptive Clock Recovery Sub-Module (Simplified Functional Block Diagram).................................70

Figure 32 - Timing Reference Cell Processing State Machine............................................................................71

Figure 33 - Transmit SRTS Operation.................................................................................................................73

Figure 34 - Receive SRTS Operation..................................................................................................................74

Figure 35 - Clock Recovery Using SRTS Method (Hardware)............................................................................75

Figure 36 - Clock Recovery Using SRTS Method (CPU)....................................................................................76

Figure 37 - A Typical JTAG Test Connection......................................................................................................79

Figure 38. MT90500 Interrupt Structure.............................................................................................................81

Figure 39 - Nominal TDM Bus Timing...............................................................................................................114

Figure 40 - Main TDM Bus Output Clocking Parameters - Positive Frame Pulse.............................................115

Figure 41 - Main TDM Bus Output Clocking Parameters - Negative Frame Pulse ...........................................115

Figure 42 - Main TDM Bus - Serial Output Timing............................................................................................116

Figure 43 - Main TDM Bus - 2/4 Sampling........................................................................................................118

Figure 44 - Main TDM Bus - 3/4 Sampling........................................................................................................118

Figure 45 - Main TDM Bus - 4/4 Sampling........................................................................................................119

Figure 46 - Local TDM Bus Output Parameters - Positive Frame Pulse...........................................................121

MT90500

Figure 47 - Local TDM Bus Output Parameters - Negative Frame Pulse ........................................................ 121

Figure 48 - Local TDM Bus - Positive Frame Pulse, 2/4 Sampling .................................................................. 122

Figure 49 - Local TDM Bus - Negative Frame Pulse, 3/4 Sampling................................................................. 123

Figure 50 - Local TDM Bus - Negative Frame Pulse, 4/4 Sampling................................................................. 123

Figure 51 - Intel CPU Interface Timing - Read Access..................................................................................... 124

Figure 52 - Intel CPU Interface Timing - Write Access..................................................................................... 125

Figure 53 - Motorola CPU Interface Timing - Read Access ............................................................................. 126

Figure 54 - Motorola CPU Interface Timing - Write Access.............................................................................. 127

Figure 55 - External Memory Interface Timing - Read Cycle ........................................................................... 129

Figure 56 - External Memory Interface Timing - Write Cycle............................................................................ 130

Figure 57 - Primary UTOPIA Bus - Transmit Timing........................................................................................ 131

Figure 58 - Primary UTOPIA Bus - Receive Timing......................................................................................... 132

Figure 59 - Secondary UTOPIA Interface......................................................................................................... 133

Figure 60 - SRTS User Interface Timing.......................................................................................................... 134

Figure 61 - Message Channel Timing .............................................................................................................. 135

Figure 62 - MT90500 Device Application Block Diagram................................................................................. 137

Figure 63 - UTOPIA Bus Interconnections for Two MT90500s and an AAL5 SAR.......................................... 139

Figure 64 - The MT90500 within a LAN Hub.................................................................................................... 141

Figure 65 - Using the MT90500 with External SAR and ATM Links in a LAN Environment............................. 142

Figure 66 - Access Product using Internal High Speed Cell Bus on the Backplane......................................... 142

Figure 67 - TDM Traffic Transport Over a Cell Bus.......................................................................................... 143

Figure 68 - Connecting CTI Platforms to ATM LANs........................................................................................ 143

Figure 69 - The GO-MVIP, PC-ATM Bus Standard Architecture...................................................................... 144

Figure 70 - SRTS Clocking Application............................................................................................................ 146

Figure 71 - TDM Payload Switching................................................................................................................. 154

Figure 72 - TDM-to-TDM Loopback/Switching................................................................................................. 155

Figure 73 - SCSA Message Bus Application................................................................................................... 156

MT90500

List of Tables

Table 1 - Primary UTOPIA Bus Pins................................................................................................................19

Table 2 - Secondary UTOPIA Bus Pins...........................................................................................................20

Table 3 - Microprocessor Bus Interface Pins...................................................................................................20

Table 4 - External Memory Interface Pins........................................................................................................21

Table 5 - Master Clock, Test, and Power Pins.................................................................................................22

Table 6 - TDM Port Pins...................................................................................................................................23

Table 7 - Reset State of I/O and Output Pins...................................................................................................24

Table 8 - Pinout Summary................................................................................................................................25

Table 9 - Memory Size Combinations..............................................................................................................39

Table 10 - Effect of PSEL Field on P-byte Generation.......................................................................................53

Table 11 - Register Summary ............................................................................................................................82

Table 12 - Main Control Register .......................................................................................................................84

Table 13 - Main Status Register.........................................................................................................................84

Table 14 - Window to External Memory Register - CPU....................................................................................85

Table 15 - Read Parity Register.........................................................................................................................85

Table 16 - Memory Configuration Register ........................................................................................................86

Table 17 - TX_SAR Control Register.................................................................................................................87

Table 18 - TX_SAR Status Register...................................................................................................................87

Table 19 - TX_SAR Scheduler Base Register ...................................................................................................88

Table 20 - TX_SAR Frame End Register...........................................................................................................88

Table 21 - TX_SAR End Ratio Register.............................................................................................................88

Table 22 - TX_SAR Control Structure Base Address Register..........................................................................89

Table 23 - Transmit Data Cell FIFO Base Address Register .............................................................................89

Table 24 - Transmit Data Cell FIFO Write Pointer Register...............................................................................89

Table 25 - Transmit Data Cell FIFO Read Pointer Register...............................................................................90

Table 26 - RX_SAR Control Register.................................................................................................................91

Table 27 - RX_SAR Status Register..................................................................................................................92

Table 28 - RX_SAR Misc. Event ID Register.....................................................................................................92

Table 29 - RX_SAR Misc. Event Counter Register............................................................................................92

Table 30 - RX_SAR Underrun Event ID Register...............................................................................................93

Table 31 - RX_SAR Underrun Event Counter Register .....................................................................................93

Table 32 - RX_SAR Overrun Event ID Register.................................................................................................93

Table 33 - RX_SAR Overrun Event Counter Register .......................................................................................93

Table 34 - UTOPIA Control Register..................................................................................................................94

Table 35 - UTOPIA Status Register...................................................................................................................94

Table 36 - VPI / VCI Concatenation Register.....................................................................................................95

Table 37 - VPI Match Register...........................................................................................................................95

Table 38 - VPI Mask Register ............................................................................................................................95

Table 39 - VCI Match Register...........................................................................................................................95

Table 40 - VCI Mask Register............................................................................................................................96

Table 41 - VPI Timing Register..........................................................................................................................96

Table 42 - VCI Timing Register..........................................................................................................................96

Table 43 - Lookup Table Base Address Register...............................................................................................96

Table 44 - Receive Data Cell FIFO Base Address Register ..............................................................................97

Table 45 - Receive Data Cell FIFO Write Pointer Register................................................................................97

Table 46 - Receive Data Cell FIFO Read Pointer Register................................................................................97

Table 47 - TDM Interface Control Register ........................................................................................................98

Table 48 - TDM Interface Status Register..........................................................................................................99

MT90500

Table 49 - TDM I/O Register........................................................................................................................... 100

Table 50 - TDM Bus Type Register................................................................................................................. 101

Table 51 - Local Bus Type Register................................................................................................................ 102

Table 52 - TDM Bus to Local Bus Transfer Register....................................................................................... 102

Table 53 - Local Bus to TDM Bus Transfer Register....................................................................................... 103

Table 54 - TX Circular Buffer Control Structure Base Register....................................................................... 103

Table 55 - External to Internal Memory Control Structure Base Register....................................................... 103

Table 56 - TX Circular Buffer Base Address Register..................................................................................... 104

Table 57 - TDM Read Underrun Address Register......................................................................................... 104

Table 58 - TDM Read Underrun Count Register............................................................................................. 104

Table 59 - Clock Module General Control Register......................................................................................... 104

Table 60 - Clock Module General Status Register.......................................................................................... 105

Table 61 - Master Clock Generation Control Register .................................................................................... 106

Table 62 - Master Clock / CLKx2 Division Factor............................................................................................ 107

Table 63 - Timing Reference Processing Control Register............................................................................. 107

Table 64 - Event Count Register..................................................................................................................... 108

Table 65 - CLKx1 Count - Low Register.......................................................................................................... 108

Table 66 - CLKx1 Count - High Register......................................................................................................... 108

Table 67 - DIVX Register ................................................................................................................................ 109

Table 68 - DIVX Ratio Register....................................................................................................................... 109

Table 69 - SRTS Transmit Gapping Divider Register ..................................................................................... 109

Table 70 - SRTS Transmit Byte Counter Register.......................................................................................... 110

Table 71 - SRTS Receive Gapping Divider Register ...................................................................................... 110

Table 72 - SRTS Receive Byte Counter Register........................................................................................... 110

Table 73 - Output Enable Registers................................................................................................................ 111

Table 74 - Absolute Maximum Ratings ........................................................................................................... 112

Table 75 - Recommended Operating Conditions............................................................................................ 112

Table 76 - DC Characteristics......................................................................................................................... 112

Table 77 - Main TDM Bus Output Clock Parameters...................................................................................... 114

Table 78 - Main TDM Bus Data Output Parameters ....................................................................................... 116

Table 79 - Main TDM Bus Input Clock Parameters......................................................................................... 117

Table 80 - Main TDM Bus Input Data Parameters.......................................................................................... 117

Table 81 - Local TDM Bus Clock Parameters................................................................................................. 120

Table 82 - Local TDM Bus Data Output Parameters....................................................................................... 120

Table 83 - Local TDM Bus Data Input Parameters ......................................................................................... 122

Table 84 - Intel Microprocessor Interface Timing - Read Cycle Parameters................................................... 124

Table 85 - Intel Microprocessor Interface Timing - Write Cycle Parameters................................................... 125

Table 86 - Motorola Microprocessor Interface Timing - Read Cycle Parameters ........................................... 126

Table 87 - Motorola Microprocessor Interface Timing - Write Cycle Parameters............................................ 127

Table 88 - MCLK - Master Clock Input Parameters ........................................................................................ 128

Table 89 - External Memory Interface Timing - Clock Parameters ................................................................. 128

Table 90 - External Memory Interface Timing - Read Cycle Parameters........................................................ 128

Table 91 - External Memory Interface Timing - Write Cycle Parameters........................................................ 128

Table 92 - Primary UTOPIA Interface Parameters - Transmit......................................................................... 131

Table 93 - Primary UTOPIA Interface Parameters - Receive.......................................................................... 132

Table 94 - Secondary UTOPIA Parameters Timing........................................................................................ 133

Table 95 - SRTS Interface Parameters........................................................................................................... 134

Table 96 - Message Channel Parameters....................................................................................................... 134

Table 97 - Boundary-Scan Test Access Port Timing ...................................................................................... 136

Table 98 - MT90500 Connections to 18-bit Synchronous SRAM.................................................................... 138

MT90500

Table 99 - MT90500 Connections to 32/36-bit Synchronous SRAM................................................................138

Table 100 - MT90500 UTOPIA Signal Directions...............................................................................................140

Table 101 - Recommended TDM Channel Numbers for SRTS VCs .................................................................145

Table 102 - Limits on CDV on Receive SRTS VC..............................................................................................146

Table 103 - Summary of External Memory Structures .......................................................................................149

MT90500

1. Introduction

1.1 Functional Overview

The Mitel MT90500 Multi-Channel AAL1 SAR bridges a standard isochronous TDM (Time Division Multiplexed) backplane to a standard ATM (Asynchronous Transfer Mode) bus. On the TDM bus side, the MT90500 can interface to 16 bidirectional TDM bus links operating at 2.048, 4.096 or 8.192 Mbps (compatible with MVIP / HMVIP, SCSA and Mitel ST-BUS). On the ATM interface side, the MT90500 provides the UTOPIA bus standardized by the ATM Forum. The device provides the AAL1 Structured Data Transfer (referred to as SDT from now on in this document) and pointerless Structured Data Transfer mappings deﬁned by ANSI T1.6301993 and ITU-T I.363. In addition, the MT90500 provides CBR (Constant Bit Rate) mapping of TDM to AAL0, and to AAL5 (CBR-AAL5). In all data transfer for mats, the user simply ports the T1/E1, T3/E3, etc. trafﬁc onto the TDM backplane before applying it to the MT90500. As well, the device also suppor ts TDM clock recovery using adaptive, SRTS, or external clock recovery.

In the receive direction, ATM cells with VCs destined for the MT90500 are extracted from the UTOPIA bus and sent toward the TDM interface. In the transmit direction, the MT90500 provides multiplexing capabilities at the UTOPIA interf ace to allo w the use of an external AAL5 SAR device, or multiple MT90500 devices. This is useful when CBR data and VBR/ABR/UBR data trafﬁc must be transmitted from the local node on the same physical link. As well, the ability to multiplex internal AAL1 cells with external AAL5 cells can be used to interleave associated signalling cells and control messages with the AAL1 CBR trafﬁc.

The MT90500 also offers some internal support for non-CBR data trafﬁc. If the application's signalling (nonCBR) data throughput is not high, the MT90500 can transmit and receive AAL5 (or other non-CBR data) to / from a pair of FIFOs. This requires the microprocessor to perform SAR functions via software, but may remove the requirement for an external data SAR. Alternatively, if standard AAL5 signalling is not required by the system, the user can use some TDM channels for HDLC or proprietary signalling.

Segmentation and reassembly of TDM data to / from ATM cells is highly ﬂexible. The MT90500 allows the user to select one or more TDM channels to be carried on an ATM logical connection with associated VPI/VCI. The number of TDM channels (1 to 122), the VPI/VCI, the data transfer method (SDT or pointerless Structured Data Transfer), cell partial-ﬁll level, and the AAL (AAL1, CBR-AAL5, or CBR-AAL0) are all programmable. The time slot assignment circuit has 64 kbps granularity and allows a group of TDM channels to be carried on a single ATM logical channel (channel grooming). There is no limitation for distributing n x 64 channels on the TDM bus (i.e. TDM channels on a given VC can be concatenated or dispersed anywhere on the 16 serial data streams).

Up to 1024 bidirectional virtual circuits (VCs) can be handled simultaneously by the internal AAL1 processors. At the maximum TDM rate of 8.192 Mbps, up to 2048 input/output 64 kbps channels are available (1024 bidirectional TDM channels). If the ATM VCs are carrying multiple TDM channels (n x 64), less VCs will be created. The user is given the ability to ﬂexibly deﬁne which 64 kbps channels will be converted into ATM VCs. It should be noted that since the MT90500’s serial TDM port is fully bidirectional, the ATM logical connections can be deﬁned as full duplex channels (e.g. voice conversation) or one-way connections (e.g. video playback). Using the full duplex capabilities, up to 1024 simultaneous phone calls could be handled by the MT90500.

The MT90500 allows the user to scale the size of the external synchronous memory to suit the application. The external memory’s size is inﬂuenced by the number of vir tual circuits required, the number of TDM channels being handled, and the amount of cell delay variation (CDV) tolerance required for the receive VCs. Userdeﬁned lookup tables, data cell FIFOs, and multiple event schedulers also inﬂuence the amount of external memory required.

The MT90500 supports two clocking schemes on the TDM bus: clock master and clock slave. In clock master, the MT90500 drives the clocks onto the TDM backplane (the TDM clock is recovered from an incoming ATM VC, or from an external source). In clock slave mode, the MT90500 receives its 8 kHz framing and clocks (4.096, 8.192 or 16.384 MHz) from the TDM backplane, and times its internal functions from that.

Figure 1 on page 12 shows the MT90500 block diagram. The Applications section of this document illustrates several connectivity options with external PHY and SAR devices.

MT90500

To/From External PHY

From External SAR

Main UTOPIA Interface

Secondary UTOPIA Interface

MT90500

TX UTOPIA

MUX

UTOPIA

BLOCK

UTOPIA Module

VC Look-up

Tables

AAL1

SAR

TX / RX Control

Circular Buffers

External Memory

Controller

AAL1

SAR

Structures and

Internal

TDM

Frame

Buffer

External Synchronous SRAM

TDM Module

TDM Bus

Interface

Logic

TDM Clock

Logic

Clock

Recovery

Registers

TDM Bus 16 lines 2048 x 64kbps (max.)

Local TDM Bus 32 x 64 kbps in / 32 x 64 kbps out

Clock Signals

Boundary-

Scan Logic

JTAG Interface

Microprocessor Interface Logic

16-bit Microprocessor Interface

Figure 1 - MT90500 Block Diagram

1.2 Reference Documents

MT90500 Programmer’s Manual. MSAN-171 - TDM Clock Recovery from CBR-over-ATM Links Using the MT90500. ITU-T Rec. I.363.1, “B-ISDN ATM Adaptation Layer Speciﬁcation: Type 1 AAL,” 08/1996. ANSI T1.630, “Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and

Speciﬁcation,” 1993. AF-PHY-0017, “UTOPIA, An ATM-PHY Interface Speciﬁcation: Level 1, Version 2.01,” March 21, 1994. AF-VTOA-0078.000, “Circuit Emulation Service Interoperability Speciﬁcation, Version 2.0,” Jan. 1997. AF-VTOA-0083.000, “Voice and Telephony Over ATM to the Desktop Speciﬁcation, Version 2.0,” May 1997. M. Noorchasm

Forum Contribution 95-1454.

et al.

, “Buffer Design for Constant Bit Rate Services in Presence of Cell Delay Variation,” ATM

Paul E. Fleischer and Chi-Leung Lau, “Synchronous Residual Time Stamp f or Timing Reco very in a Broadband Network,” United States Patent 5,260,978, Nov. 1993.

IEEE Std. 1149.1a-1993, “IEEE Standard Test Access Port and Boundary Scan Architecture.”

1.3 ATM Glossary

MT90500

AAL -

applications into the size and format of an ATM cell.

AAL0 - native ATM cell transmission; proprietary protocol featuring 5-byte header and 48-byte user payload. AAL1 - ATM Adaptation Layer used for the transport of constant bit rate, time-dependent trafﬁc (e.g. voice,

video); requires transfer of timing infor mation between source and destination; maximum of 47-bytes of user data permitted in payload as an additional header byte is required to provide sequencing information.

AAL5 - ATM Adaptation Layer usually used for the transport of variable bit rate, delay-tolerant data trafﬁc and signalling which requires little sequencing or error-detection support.

ANSI T1.630 - American National Standards Institute speciﬁcation: Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Services Functionality and Speciﬁcation.

Asynchronous - 1. Not synchronous; not periodic. 2. The temporal property of being sourced from independent timing references. Asynchronous signals have different frequencies, and no ﬁxed phase relationship. 3. In telecom, data which is not synchronized to the public network clock. 4. The condition or state when an entity is unable to determine, prior to its occurrence, exactly when an event will transpire.

ATM length cells; asynchronous in the sense that the recurrence of cells containing information from an individual user is not necessarily periodic. (While ATM cells are transmitted synchronously to maintain clock between sender and receiver, the sender transmits data cells when it has something to send and transmits empty cells when idle, and is not limited to transmitting data ever y Nth cell.)

Cell - ﬁxed-size information package consisting of 53 bytes (octets) of data; of these, 5 bytes represent the cell header and 48 bytes carry the user payload and required overhead.

ATM Adaptation Layer

; standardized protocols used to translate higher layer services from multiple

Asynchronous Transfer Mod

e; a method in which information to be transferred is organized into ﬁxed-

CBR control and strict performance parameters. Used for services such as voice, video, or circuit emulation.

CDV results from buffering and cell scheduling.

CES characteristics of a constant bit rate, dedicated-bandwidth circuit (e.g. T1).

CLP with CLP = 1 can be discarded in a congestion situation.

CSI using SDT, indicates the presence of a pointer byte; used to transport RTS values in odd-numbered cells using

SRTS for clock recovery. GFC -

default value is “0000”, meaning that GFC protocol is not enforced. HEC -

check for an error and correct the contents of the header; CRC algorithm allows for single-error correction and multiple-error detection.

I.363 - ITU-T Recommendation specifying the AALs for B-ISDN (Broadband ISDN). Isochronous - The temporal property of an event or signal recurring at known periodic time intervals (e.g. 125

µs). Isochronous signals are dependent on some uniform timing, or carry their own timing information embedded as part of the signal. Examples are DS-1/T1, E1 and TDM in general. From the root words, “iso” meaning equal, and “chronous” meaning time.

Constant Bit Rate

Cell Delay Variation

Circuit Emulation Service

Cell Loss Priority

; an ATM service category supporting a constant or guaranteed rate, with timing

; a QoS parameter that measures the peak-to-peak cell delay through the network;

; ATM Forum service providing a virtual circuit which emulates the

; a 1-bit ﬁeld in the ATM cell header that corresponds to the loss priority of a cell; cells

Convergence Sublayer Indication

Generic Flow Control

Header Error Control

; 4-bit ﬁeld in the ATM header used for local functions (not carried end-to-end);

; using the ﬁfth octet in the ATM cell header, ATM equipment (usually the PHY) may

bit in the AAL1 header byte; when present in an even-numbered cell

OAM bit indicates if the ATM cell carries management information such as fault indications.

Plesiochronous - The temporal property of being arbitrarily close in frequency to some deﬁned precision. Plesiochronous signals occur at nominally the same rate, any var iation in rate being constrained within speciﬁc limits. Since they are not identical, over the long ter m they will be skewed from each other. This will force a

Operations, Administration and Maintenance

; MSB within the PTI ﬁeld of the ATM cell header which

MT90500

switch to occasionally repeat or delete data in order to handle buffer underﬂow or overﬂow. (In telecommunications, this is known as a frame slip).

PHY physical interfaces that interconnect the various ATM devices.

PTI information or user data; LSB indicates that a AAL5 cell is the ﬁnal cell in a frame.

QoS VC (e.g cell delay var iation; cell transfer delay, cell loss ratio).

RTS SAR -

reassembling, at the destination, these cells back into infor mation frames; lower sublayer of the AAL which inserts data from the information frames into cells and then adds the required header, trailer, and/or padding bytes to create 48-byte payloads to be transmitted to the ATM layer.

SDT -

are segmented into cells for transfer and additional overhead bytes (pointers) are used to indicate structure boundaries within cells (therefore aiding clock recover y).

SN misinserted ATM cells.

SNP which are designed to provide error-correction on the SN.

SRTS source clock and the network reference clock (time stamps) are transmitted to allow reconstruction of the source clock. The destination reconstructs the source clock based on the time stamps and the network reference clock. (Note that the same network reference clock is required at both ends.)

Physical Layer

Payload Type Identiﬁer

Quality of Service

Residual Time Stamp

; bottom layer of the ATM Reference Model; provides ATM cell transmission over the

; 3-bit ﬁeld in the ATM cell header - MSB indicates if the cell contains OAM

; ATM performance parameters that characterize the transmission quality over a given

; see SRTS.

Segmentation and Reassembly

Structured Data Transfer

Sequence Number

; 4-bit ﬁeld in the AAL1 header byte used as a sequence counter for detecting lost or

Sequence Number Protection

; format used within AAL1 for blocks consisting of N * 64 kbps channels; blocks

; 4-bit ﬁeld in the AAL1 header byte consisting of a CRC and a parity bit

Synchronous Residual Time Stamp;

; method of partitioning, at the source, frames into ATM cells and

method for clock recovery in which difference signals between a

SSRAM Synchronous - 1. The temporal property of being sourced from the same timing reference. Synchronous

signals have the same frequency, and a ﬁxed (often implied to be z ero) phase offset. 2. A mode of transmission in which the sending and receiving terminal equipment are operating continually at the same rate and are maintained in a desired phase relationship by an appropriate means.

UDT -

structure boundaries (e.g. circuit emulation); term used within ANSI standard - not explicitly stated in ITU. UTOPIA -

connectivity between ATM components. VC -

devices; provides sequential, unidirectional transport of ATM cells. Also VCI -

virtual channel (VC) within a vir tual path (VP) that carr ies a particular cell. VP -

channels (VC). VPI -

belongs. VTOA -

interoperability with existing N-ISDN and PBX services.

Glossary References:

The ATM Glossary The ATM Forum Glossary ATM and Networking Glossary Mitel Semiconductor Glossary of Telecommunications Terms

Synchronous Static RAM.

Unstructured Data Transfer

Universal Test and Operations Physical Interface for ATM;

Virtual Channel;

Virtual Channel Identiﬁer ;

Virtual Path;

Virtual Path Identiﬁer;

one of several logical connections deﬁned within a virtual path (VP) between two ATM

16-bit value in the ATM cell header that provides a unique identiﬁer for the

a unidirectional logical connection between two ATM devices; consists of a set of virtual

8-bit value in the ATM cell header that indicates the virtual path (VP) to which a cell

Voice and Telephony over ATM;

- ATM Year 97 - Version 2.1, March 1997

- May 1997 (http://www.techguide.com/comm/index.html)

; format used within AAL1 for transmission of user data without regard for

a PHY-level interface to provide

Virtual Circuit.

intended to provide voice connectivity to the desktop, and to provide

- May 1995.

2. Features

2.1 General

The MT90500 device external interfaces are:

• TDM (Time Division Multiplexed) bus composed of 16 serial streams running at up to 8.192 Mbps ,

plus related clocks and control signals, conﬁgurable by software. This interface also includes various signals for TDM clock signal generation. This bus carries telecom or other data in N x 64 kbps streams.

• Local serial TDM bus interface (a TDM input pin, a TDM output pin, and clocks).

• A primary UTOPIA bus running at up to 25 MHz, suitable for connection to a 25 Mbps or 155 Mbps

PHY device.

• A secondary UTOPIA bus, f or connection of an optional external SAR (e.g. data) device running at

up to 25 MHz. In this case, the MT90500 device emulates a PHY device for the external SAR.

• A synchronous 36-bit wide memory interface running at up to 60 MHz.

• A 16-bit microprocessor interface used for device conﬁguration, status, and control.

• Signals for general clocking, reset, and JTAG boundary-scan.

MT90500

2.2 Serial TDM Bus

•

Compatible with ST-BUS, MVIP, H-MVIP, IDL, and SCSA interfaces.

• Provides 16 bidirectional serial streams that can operate at TDM data rates of 2.048, 4.096 or

8.192 Mbps for up to 2048 TDM 64 kbps channels (1024 bidirectional DS0 channels: supports 32 E1 framers, or 42 T1 framers, or 10 J2 framers).

• Serial TDM bus clocking schemes: TDM timing bus slav e (MT90500 sla v ed to TDM bus), TDM tim-

ing bus master (MT90500 drives clocks onto TDM bus - freerun, or synchronized to 8 kHz reference) and TDM bus master-alternate (MT90500 slaved to TDM bus, but ready to switch to 8 kHz reference).

• Additional Local TDM Bus interface (2.048 Mbps) allows local TDM devices to access the main

TDM bus.

2.3 CBR ATM Cell Processor

•

Independent Segmentation and Reassembly blocks for receive and transmit (RX_SAR and TX_SAR) support CBR (Constant Bit Rate) transport of half- or full-duplex TDM channels.

• Compatible with “Structured Data Transfer (SDT) services” as per ANSI T1.630 standard for 1 to

122 TDM channels per VC.

• Compatible with ITU-T I.363.1 “circuit transport” of 8 kHz structured data using Structured Data

Transfer (SDT) for 1 to 96 TDM channels per VC (using buffer-ﬁll level monitoring).

• Compatible with ITU-T I.363.1 “voiceband signal transport.”

• Compatible with AF-VTOA-0078.000 “N x 64 Basic Ser vice” (non-CAS) Circuit Emulation (using

buffer-level monitoring, rather than lost cell insertion).

• Compatible with AF-VTOA-0078.000 for SDT of partially-ﬁlled AAL1 cells with N-channel struc-

tures (where N does not exceed the value of the partial-ﬁll).

• AAL1 SAR-PDU Header processing (AAL1 Sequence Number checking).

• Supports up to 1024 bidirectional VCs (virtual circuits) simultaneously.

• Supports up to 1024 transmit TDM channels and 1024 receive TDM channels simultaneously.

• Supports CBR-AAL0 (48 byte cell payload).

• Supports CBR-AAL5 as per AF-VTOA-0083.000, also supports Nx64 trunking over CBR-AAL5.

MT90500

• Supports partially-ﬁlled cells (AAL1, CBR-AAL5, and CBR-AAL0).

• User-deﬁned, per-VC, Cell Delay Variation tolerance: 8 to 128 ms buffer size (up to 64 ms CDV).

• Handles TDM channels at 64 kbps granularity.

• Each individual VC can be composed of N x 64 kbps wideband channels (N = 1, 2, ..., 122).

• Flexible aggregation capability (N x 64 kbps) maintains frame integrity, while allowing any combi-

nation of 64 kbps channels (DS0 grooming).

• Supports “multi-casting” of one TDM DS0 input channel to multiple Transmit ATM VCs, and of one

Receive ATM DS0 to multiple TDM outputs.

• A VC can contain any combination of TDM channels from any combination of TDM streams

(Nx64) and maintain frame integrity for those channels.

• Supports several 8 kHz synchronisation operations: synchronized to external 8 kHz reference,

synchronized to network clock, and synchronized to timing derived from an ATM VC (including ITU-T I.363.1 Adaptive and SRTS clock recovery mechanisms).

2.4 External Memory Interface

•

To implement SAR functions and buffers, the MT90500 device uses external Synchronous SRAM.

• External Synchronous SRAM size is chosen by user, and depends on Cell Delay Variation (CDV)

and the number of simultaneous 64 kbps channels handled. The amount of Synchronous SRAM is scalable to suit the application, and may range from 128 Kbytes to 2,048 Kbytes.

2.5 UTOPIA Interface and Multiplexer

•

UTOPIA Level 1 compatible 8-bit bus, running at up to 25 Mbyte/s, for connection to PHY devices with data throughput of up to 155 Mbps.

• Transmit multiplexer mixes cells from TX_SAR and Secondary UTOPIA port, suppor ting another

MT90500, and/or an external SAR device (e.g. AAL5) connected to a single PHY device.

• Programmable multiplexer priority gives internally generated AAL1 cells equal, or higher, priority

than cells coming from Secondary UTOPIA port.

• Supports non-CBR data cells and OAM cells destined for microprocessor with Receive and Trans-

mit Data Cell FIFOs.

• Flexible receive cell handling: AAL1 (as well as CBR-AAL0 and CBR-AAL5) cells are sent to the

TDM port; data cells (non-CBR data and OAM cells) are sent to the Receive Data Cell FIFO; cells with unrecognized VCs may be queued or ignored.

• Cell reception based on look-up-table allows ﬂexible VC assignment for CBR VCs (allows non-

contiguous VC assignment).

• Programmable VPI/VCI Match and Mask ﬁltering reduces unnecessary look-up-table accesses.

2.6 Microprocessor Interface

•

16-bit microprocessor port, conﬁgurable to Motorola or Intel timing.

• Programmable interrupts for control and statistics.

• Allows access to internal registers for initialization, control, and statistics.

• Allows access to external SSRAM for initialization, control, and observation.

2.7 Miscellaneous

•

Master clock rate up to 60 MHz.

• Dual rails (3.3V for power minimization, 5V for standard I/O).

• Loopback function provided at the TDM interface.

MT90500

• IEEE 1149 (JTAG) Boundary-Scan Test Access Port for testing board-level interconnect.

• Packaging: 240-pin PQFP.

2.8 Interrupts

The MT90500 provides a wide variety of interrupt source bits, allowing for easy monitoring of MT90500 operation. All interrupt source bits, including the module level interrupt bits, have an associated mask bit which enables or disables assertion of the interrupt pin. This enables the user to tailor the interrupt pin activity to the application. Interrupt source bits are set regardless of the state of the associated mask bit, so even source bits which are disabled from causing an interrupt pin assertion may be polled by the CPU by reading the appropriate register.

2.8.1 Module Level Interrupts

The following interrupt bits are used to indicate which MT90500 circuit module is the source of the interrupt. They are set when one or more interrupt source bits in the particular circuit module is set. The CPU can ﬁnd the source of an interrupt by reading the register containing these bits and then reading the indicated module’s interrupt register.

• TX_SAR Module Interrupt

• RX_SAR Module Interrupt

• UTOPIA Module Interrupt

• TDM Module Interrupt

• Timing (TDM Clock Generation) Module Interrupt

2.8.2 TX_SAR Interrupts

•

Transmit Non-CBR Data Cell FIFO Overrun Interrupt

• Scheduler error (Indicates that the TX_SAR has too heavy a work load.)

2.8.3 RX_SAR Interrupts

•

AAL1-byte Parity Error Interrupt

• AAL1-byte CRC Error Interrupt

• AAL1-byte Sequence Number Error Interrupt

• Pointer-byte Parity Error Interrupt

• Pointer-byte Out of Range Error Interrupt

• Underrun Error Interrupt

• Overrun Error Interrupt

• Miscellaneous Counter Rollover Interrupt

• Underrun Counter Rollover Interrupt

• Overrun Counter Rollover Interrupt

2.8.4 UTOPIA Interrupts

•

Receive Non-CBR Data Cell FIFO Overrun Interrupt

• RX UTOPIA Module Internal FIFO Overrun Interrupt

• Receive Non-CBR Data Cell FIFO Receive Cell Interrupt

2.8.5 TDM Interrupts

•

Clock Absent Interrupt

• Clock Fail Interrupt

• TDM Out of Bandwidth Interrupt

MT90500

• TDM Read Underrun Error Interrupt

• TDM Read Underrun Counter Rollover Interrupt

2.8.6 Timing Module Interrupts

•

8 kHz Reference Failure Interrupt

• SRTS TX Underrun Interrupt

• SRTS TX Overrun Interrupt

• SRTS RX Underrun Interrupt

• SRTS RX Overrun Interrupt

• Adaptive Clock Loss of Timing Reference Cell Interrupt

• Adaptive Clock Loss of Synchronization Interrupt

2.9 Statistics

The MT90500 provides a number of statistics to allow monitoring of the MT90500. These statistics generally parallel the operation of some of the interrupt source bits. The counters (except the Timing Recovery counters) also set rollover interrupt source bits when they reach their terminal counts and return to zero.

2.9.1 RX_SAR Statistics

•

Miscellaneous Event Counter: This 16-bit register’s value is incremented each time a (maskselected) miscellaneous error occurs.

• AAL1-byte Parity Error

• AAL1-byte CRC Error

• AAL1 Sequence Number Error

• Pointer-byte Parity Error

• Pointer-byte Out of Range Error

• Miscellaneous Event ID Register: The address of the RX Control Structure that caused the last

miscellaneous error.

• Underrun Count: This 16-bit register’s value is incremented each time a CBR Receive Underrun

occurs.

• Underrun ID Number: The address of the RX Control Structure that caused the last underrun

error.

• Overrun Count: This 16-bit register is incremented each time a CBR Receive Overrun occurs.

• Overrun ID Number: The address of the RX Control Structure that caused the last overrun error.

2.9.2 TDM Statistics

•

TDM Read Underrun Time Slot Stream. Contains the time slot and stream on which the last TDM read underrun was detected.

• TDM Read Underrun Counter. Each time a TDM read underrun occurs, this register’s value is

incremented.

2.9.3 Timing Recovery Statistics

•

Event Counter: Counts the reception of timing reference cells or 8 kHz markers.

• CLKx1 Counter: 24-bit counter which keeps a running count of TDM byte-periods.

MT90500

3. Pin Descriptions

I/O types are: Output (O), Input (I), Bidirectional (I/O), Power (PWR), or Ground (GND). Input pad types are: TTL, CMOS, Differential, or Schmitt. The notations “PU” and “PD” are used, respectively,

to indicate that a pad has an internal pullup or pulldown resistor. TTL (5V) inputs are pulled-up to the 5V rail, CMOS (3.3V) inputs are pulled-up to the 3.3V rail. These weak internal resistors should not be relied upon for fast data transitions. The 3.3V CMOS inputs have a switching threshold of 1.6V, and tolerate input levels of up to 5V; therefore they are 5V TTL compatible (with the exception of the TRISTATE pin, which is not 5V tolerant).

Output pad types are generally described by voltage and current capability. Output types used are: 3.3V, 4mA; 5V, 4mA; 5V, 12mA; and open-drain. A notation of “SR” indicates that the pad is slew-rate limited. 3.3V CMOS outputs will satisfy 5V TTL input thresholds at the rated current.

Table 1 - Primary UTOPIA Bus Pins

Pin # Pin Name I/O Type Description

49, 48, 47, 46,

45, 44, 39, 38

52 PTXSOC O 5V, 4mA Primary UTOPIA transmit start of cell signal. Asserted by the MT90500 when

51 PTXEN O 5V, 4mA Primary UTOPIA transmit data enable. Active LOW signal asserted by the

53 PTXCLAV I TTL PU Primary UTOPIA transmit cell available indication signal. For cell level flow

82 PTXCLK I/O TTL PU /

50 PTXPAR O 5V, 4mA Primary UTOPIA transmit parity. This signal is the odd parity bit over

57, 58, 59, 62,

63, 64, 65, 66

56 PRXSOC I TTL PU Primary UTOPIA receive start of cell signal. Asserted by the PHY when

55 PRXEN I TTL PU Primary UTOPIA bus data enable. Active LOW signal normally asserted by the

54 PRXCLAV I TTL PU Primary UTOPIA receive cell available indication signal. For cell level flow control,

79 PRXCLK I TTL PU Primary UTOPIA bus receive clock. This clock, which can run at up to 25 MHz, is

Refer to Figure 63 on page 139 for implementation details regarding the interface between two MT90500s and an external AAL5 SAR.

PTXDATA[7:0] O 5V, 4mA Primary UTOPIA transmit data bus. Byte-wide data driven from MT90500 to PHY

device. Bit 7 is the MSB.

PTXDATA[7:0] contains the first valid byte of the cell.

MT90500 during cycles when PTXDATA[7:0] contains valid cell data.

control, PTXCLAV is asserted by the PHY to indicate to the MT90500 that the PHY can accept the transfer of a complete cell.

Primary UTOPIA transmit clock. Data transfer & synchronization clock provided by

5V, 4mA

PRXDATA[7:0] I TTL PU Primary UTOPIA receive data bus. Byte-wide data driven from the PHY to the

the MT90500 to the PHY for transmitting data on PTXDATA[7:0]; software configurable (in Main Control Register at 0000h) to run at up to 25 MHz. Note that this pin should be configured as an output for exact compliance with UTOPIA Level 1, V2.01.

PTXDATA[7:0].

MT90500. PRXDATA[7] is the MSB.

PRXDATA[7:0] contains the first valid byte of a cell.

secondary SAR to indicate that PRXDATA[7:0], PRXSOC, and PRXCLAV will be sampled at the end of the next clock cycle. If no secondary SAR is used, ground this pin at the MT90500 and PHY devices. Note that the UTOPIA standard permits this signal to be permanently asserted (see UTOPIA Level 1, V2.01, footnote 6).

PRXCLAV is asserted by the PHY to indicate it has a complete cell available for transfer to the RX UTOPIA port.

provided by the secondary SAR device. If no secondary SAR is used, connect to PTXCLK (this will provide exact compliance with the UTOPIA Level 1, V2.01 specification).

MT90500

Table 2 - Secondary UTOPIA Bus Pins

Pin # Pin Name I/O Type Description

70, 71, 72, 73,

74, 75, 76, 77

69 STXSOC I TTL PU Secondary UTOPIA transmit start of cell signal. Asserted by the external SAR

68 STXEN I TTL PU Secondary UTOPIA transmit data enable. Active LOW signal asserted by the

67 STXCLAV O 5V, 4mA Secondary UTOPIA transmit cell available indication signal. For cell level flow

85 STXCLK I TTL PU Secondary UTOPIA transmit clock, which can run at up to 25 MHz. Data transfer &

Note: MT90500 Secondary UTOPIA port emulates a PHY device for connection to an external SAR (ATM-layer device). Refer to Figure 63 on page 139 for implementation details regarding the interface between the MT90500 and an external AAL5 SAR.

STXDATA[7:0] I TTL PU Secondary UTOPIA transmit data bus. Byte-wide data driven from the external

SAR to the MT90500. Bit 7 is the MSB.

device when STXDATA[7:0] contains the first valid byte of the cell.

external SAR during cycles when STXDATA[7:0] contains valid cell data.

control, STXCLAV is asserted by the MT90500 to indicate to the external SAR that the MT90500 can accept the transfer of a complete cell.

synchronization clock provided by the external SAR to the MT90500 for transmitting data over STXDATA[7:0].

Table 3 - Microprocessor Bus Interface Pins

Pin # Pin Name I/O Type Description

37 Intel/Motorola I TTL PU Intel interface (1) / Motorola interface (0)

36 IC I TTL PU Internal connection (must be HIGH). 203 CS I TTL PU Active LOW chip select signal. 237 WR/R\W I TTL PU Active LOW Write Strobe (Intel) / Read-Write (Motorola). 239 RD/DS I TTL PU Active LOW Read Strobe (Intel) / Active LOW Data Strobe (Motorola). 238 RDY/DTACK O 5V, 4mA Ready (Intel) / Data Transfer Acknowledge (Motorola). Acts as active LOW

pseudo-open-drain in Motorola mode (DTACK, see Figure 53 on page 126). Acts as normal output in Intel mode, high impedance when CS is HIGH (RDY).

84 INT O 5V, 4mA SR

(Open-Drain)

223, 222, 219, 218, 217, 216, 215, 214, 212, 211, 210, 209, 208, 206, 205,

204 184 AEM I TTL PU Access External Memory - CPU accesses external memory when HIGH

185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196,

198, 199, 202

Note: MT90500 TTL inputs are pulled up to the 5 Volt rail. See Table 76 on page 112.

D[15:0] I/O TTL PU /

5V, 4mA SR

A[15:1] I TTL PU CPU Address lines A15-A1.

Active LOW interrupt line.

CPU data bus.

(internal memory and registers when LOW).

All microprocessor accesses to the device are word-wide, but addresses in this document are given as byte-addresses. The virtual A[0] bit selects between high and low bytes in a word.

MT90500

Table 4 - External Memory Interface Pins

Pin # Pin Name I/O Type Description

98 MEMCLK O 3.3V, 4mA Memory Clock. Internally connected to MCLK.

147 MEM_CS0L O 3.3V, 4mA Active LOW memory chip select signal. This chip select is used in all memory

modes. When there are two chips per bank, MEM_CS0L is associated with MEM_DAT[15:0] of Bank 0.

176 MEM_CS0H O 3.3V, 4mA Active LOW memory chip select signal. This chip select is used when there

are two 16-bit memory chips per bank. MEM_CS0H is associated with MEM_DAT[31:16] of Bank 0.

148 MEM_CS1L O 3.3V, 4mA Active LOW memory chip select signal. This chip select is used when there

are two banks and two chips per bank. MEM_CS1L is associated with MEM_DAT[15:0] of Bank 1.

177 MEM_CS1H O 3.3V, 4mA Active LOW memory chip select signal. This chip select is used when there

are two banks and two chips per bank. MEM_CS1H is associated with MEM_DAT[31:16] of Bank 1.

178, 179, 149,

150

180 MEM_OE O 3.3V, 4mA Active LOW output enable.

123, 122, 121, 118, 117, 116, 115, 103, 102,

99, 146, 144,

130, 128, 127,

126, 125, 124

166, 167, 168, 170, 171, 173, 174, 175, 153, 154, 155, 156, 158, 159, 162, 164, 133, 134, 135, 136, 137, 138, 142, 143, 105, 106, 107, 108, 109, 112,

113, 114

165, 152, 131,

104

Note: MT90500 3.3 V CMOS inputs are pulled up to the 3.3 Volt rail. See Table 76 on page 112.

MEM_WR[3:0] O 3.3V, 4mA Active LOW byte-write enables. MEM_WR[3] is associated with

MEM_DAT[31:24]; MEM_WR[2] is associated with MEM_DAT[23:16]; MEM_WR[1] is associated with MEM_DAT[15:8]; MEM_WR[0] is associated with MEM_DAT[7:0].

MEM_ADD[17:0] O 3.3V, 4mA Memory address lines.

MEM_DAT[31:0] I/O 3.3V CMOS

PU / 3.3V 4mA

MEM_PAR[3:0] I/O 3.3V CMOS

PU / 3.3V 4mA

Memory data lines. MEM_DAT[31:24] represent the upper byte; MEM_DAT[23:16] represent the upper-middle byte; MEM_DAT[15:8] represent the lower-middle byte; MEM_DAT[7:0] represent the lower byte.

Memory parity lines. MEM_PAR[3:0] are the optional “parity” bits that allow TDM Read Underrun detection. MEM_PAR[3] is related to MEM_DAT[31:24], MEM_PAR[2] is related to MEM_DAT[23:16], MEM_PAR[1] is related to MEM_DAT[15:8], and MEM_PAR[0] is related to MEM_DAT[7:0]. When unused, these pins must be pulled up via external resistors.

MT90500

Table 5 - Master Clock, Test, and Power Pins

Pin # Pin Name I/O Type Description

87 MCLK I TTL PU Master Clock. This signal drives the internal logic (including the RX_SAR and

the TX_SAR) and the external memory (through MEMCLK). 60 MHz for most applications. MCLK should be more than 5 times CLKx1, and should be more than 3 times FNXI.

78 RESET I 5V TTL

Schmitt PU

97 TMS I 3.3V CMOSPUJTAG Test Mode Select signal.

93 TCK I 3.3V CMOSPUJTAG Test Clock.

95 TDI I 3.3V CMOSPUJTAG Test Data In.

96 TDO O 3.3V, 4mASRJTAG Test Data Out.

94 TRST I 3.3V CMOSPDJTAG Test Reset input (active LOW). Should be asserted LOW on power-up

1, 7, 16, 29, 43, 61, 86, 91, 110,

119, 129, 139, 151, 163, 172, 182, 197, 213,

229

100, 141, 161 CORE_VSS GND Ground for core logic.

20, 40, 80, 201,

221

92, 111, 120,

132, 145, 157,

169, 181

2, 13, 24, 42,

60, 88, 183,

207, 225, 240 101, 140, 160 CORE_VDD_3V PWR Power for core logic (3.3 V).

21, 41, 81, 200,

220

89 IC I IC TEST, must be grounded.

90 TRISTATE I 3.3V CMOS

IO_VSS GND Ground for I/O logic.

RING_VSS GND Ground for core logic.

IO_VDD_3V PWR Power for I/O logic (3.3 V).

IO_VDD_5V PWR Power for I/O logic (5 V).

RING_VDD_3V PWR Power for core logic (3.3 V).

3.3V ONLY

Chip reset signal (active LOW). Note that the MT90500 is synchronously reset, and that MCLK should be applied during reset. To asynchronously tristate outputs, assert the TRISTATE pin. The TRST pin (JTAG reset) should also be asserted LOW during chip reset. Reset should last at least 2 µs when MCLK is 60 MHz. Also see SRES bit in register 0000h.

Note: TDO is tristated by TRISTATE pin.

and during reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an internal pull-down.

Output Tristate Control. Asynchronously tristates all output pins when LOW. Can be asserted LOW on power-up and during reset. Pull up to 3.3V for normal operation. NOT 5V TOLERANT.

Table 6 - TDM Port Pins

Pin # Pin Name I/O Type Description

MT90500

25, 23, 22, 19, 18, 17, 15, 14,

12, 11, 10, 9,

8, 6, 5, 4

230 CLKx2PI I Diff + Differential clock signal input (+) running at twice the serial TDM data

227 CLKx2NI I Diff - Differential clock signal input (-) running at twice the serial TDM data

233 CLKx1 I/O TTL PU /

232 FSYNC I/O TTL PU /

30 IC I TTL PU Internal connection (must be HIGH). 32 CORSIGA /

235 CORSIGB / MC /

33 CORSIGC /

34 CORSIGD /

35 CORSIGE /

83 EX_8KA I TTL PU An 8 kHz clock input that can be used as reference in the generation of the

234 SEC8K I/O TTL PU /

226 REF8KCLK O 5V, 12mA SR An 8 kHz clock generated internally. This signal is generated from one of

224 PLLCLK I TTL PU 16.384 / 32.768 MHz TDM clock reference from external PLL.

31 FREERUN O 5V, 12mA SR Active HIGH external PLL freerun indication.

236 LOCx2 O 5V, 4mA SR Local TDM Bus Clockx2.

3 LOCx1 O 5V, 4mA SR Local TDM Bus Clockx1. 28 LSYNC O 5V, 4mA SR Local TDM Bus Frame Sync. 26 LOCSTo O 5V, 4mA SR Local TDM Bus Serial Data Out Stream. 27 LOCSTi I TTL PU Local TDM Bus Serial Data In Stream.

231 CLKx2/

228 CLKx2NO O 5V, 12mA CLKx2 Negative Output. Differential negative output clock. (Inverse of

ST[15:0] I/O TTL PU /

5V, 12mA SR

I/O TTL PU /

CLKFAIL

FNXI

MCTX /

SRTSENA

MCRX /

SRTSDATA

MCCLK

CLKx2PO

5V, 12mA SR

I/O TTL PU /

5V, 12mA SR

I/O TTL PU /

5V, 4mA SR

I/O TTL PU /

5V, 4mA SR

I/O TTL PU /

5V, 4mA SR

5V, 12mA

I/O TTL PU /

5V, 12mA

TDM data streams. Used to pass PCM (voice) bytes or other data types. In order to enable any of these pins as outputs, the GENOE bit in the TDM Interface Control Register (6000h) must be set, as well as the appropriate channel bits in the Output Enable Registers.

stream frequency. This pin is used only in differential clock mode (H-MVIP) and should be tied HIGH when not in use. For normal (non-differential) clock mode input, use CLKx2/CLX2PO pin.

stream frequency. This pin is used only in differential clock mode (H-MVIP) and should be grounded when not in use.

Clockx1. This signal represents the CLKx2 signal divided by 2.

Frame sync. Bidirectional 8 kHz reference to/from main TDM Bus.

CORSIGA I/O when not used by the TDM bus. Clock fail on SCSA bus.

CORSIGB I/O when not used by the TDM bus. Message Channel (I/O) on the SCSA bus. SRTS FNX Network Clock Input - this input line is required when SRTS clock recovery mode is used. Note: When used for clock recovery, this clock must be < MCLK / 3.

CORSIGC I/O when not used by the TDM bus. Message Channel Transmit (input) toward SCSA bus from HDLC controller. This signal represents SRTS ENA output when SRTS clock recovery mode is selected.

CORSIGD I/O when not used by the TDM bus. Message Channel Receive (output) from SCSA bus toward HDLC controller. This signal represents SRTS DATA output serial line when SRTS clock recovery mode is selected.

CORSIGE I/O when not used by the TDM bus. Message Channel HDLC controller clock (output) from the SCSA bus.

REF8KCLK or SEC8K lines. Secondary alternate 8 kHz clock. Compatible with MVIP and H-MVIP

modes.

several internal sources which are programmed by the user. This output can provide a reference clock to an external PLL to generate the 16.384 /

32.768 MHz required for the operation of the IC in master mode.

CLKx2 Input/Output / CLKx2 Positive Output. Normal (non-differential) CLKx2 input in TDM Clock Slave mode. CLKx2 output (differential and nondifferential) in TDM Clock Master mode.

CLKx2PO). Used in TDM Clock Master, differential clock mode (H-MVIP); active whenever MT90500 is TDM Clock Master. (Leave unconnected if non-differential clock desired.)

MT90500

Table 7 - Reset State of I/O and Output Pins

Pin Name I/O Reset State Additional Control Information

PTXDATA[7:0] O Active during and after reset. N / A

PTXPAR O Active during and after reset. N / A PTXCLK I/O High-impedance The PTXCLK_SEL bits in the Main Control Register (0000h) are LOW

after reset; PTXCLK is tristated and an input.

PTXEN O Active during and after reset. N / A

PTXSOC O Active during and after reset. N / A

STXCLAV O Active during and after reset. N / A

MEMCLK O Continues to drive at MCLK

rate during reset.

MEM_CS[1:0][H:L] O Active during and after reset. N / A

MEM_WR[3:0] O Active during and after reset. N / A

MEM_OE O Active HIGH during reset. RESET LOW forces this pin HIGH. After reset, this pin goes LOW. MEM_ADD[17:0] O Active during and after reset. N / A MEM_DAT[31:0] I/O High-impedance N / A

MEM_PAR[3:0] I/O High-impedance N / A

RDY/DTACK O Active during and after reset.

Tristated when CS is HIGH.

INT O High-impedance The interrupt enable bits in the Main Control Register at 0000h are reset to

D[15:0] I/O High-impedance N / A

TDO O Determined by TRST and / or

TAP controller state

ST[15:0] I/O High-impedance The GENOE bit in the TDM Interface Control Register (6000h) is LOW

CLKx1 I/O Input The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;

FSYNC I/O Input The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;

CORSIGA/

CLKFAIL

CORSIGB / MC /

FNXI

CORSIGC / MCTX /

SRTSENA

CORSIGD / MCRX /

SRTSDATA

CORSIGE

/ MCCLK

SEC8K I/O Input The SEC8KEN bit in the Master Clock Generation Control Register

REF8KCLK O Active during and after reset. Due to the reset values of the Master Clock Generation Control Register

FREERUN O Active HIGH during and after

LOCx2 O Active during and after reset. N / A LOCx1 O Active during and after reset. N / A

I/O Input The TDM I/O Register at 6004h resets to all zeroes; all CORSIGxCNF are

I/O Input See CORSIGA.

reset.

N / A

In Motorola mode, pin drives HIGH during reset. In Intel mode, drives LOW during reset.

zero; interrupts are masked after reset.

N / A

after reset; these TDM data pins are tristated and in loopback mode.

the MT90500 is TDM Slave, and CLKx1 is input from the TDM bus.

the MT90500 is TDM Slave and FSYNC is input from the TDM bus.

set to “00” and all CORSIGx pins are configured as inputs.

(6090h) resets to ‘0’; SEC8K is an input.

(6090h) and the Master Clock / CLKx2 Division Factor (6092h), REF8KCLK is initially equal to MCLK / 8194.

The FREERUN bits in the Master Clock Generation Control Register at 6090h are “00” after reset; the FREERUN pin is reset to active HIGH.

MT90500

Table 7 - Reset State of I/O and Output Pins

Pin Name I/O Reset State Additional Control Information

LSYNC O Active during and after reset. N / A

LOCSTo O Active during and after reset. N / A

CLKx2/CLKx2PO I/O Input The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;

the MT90500 is TDM Slave and CLKx2 is input from the TDM bus.

CLKx2NO O High-impedance The CLKMASTER bit in the TDM Bus Type Register (6010h) resets to ‘0’;

the MT90500 is TDM Slave and therefore no clock signals are driven from the MT90500.

Note: All pins are placed in high-impedance by asserting the TRISTATE pin.

Table 8 - Pinout Summary

Type Input Output I/O Power Ground

Primary UTOPIA 13 11 1

Secondary UTOPIA 11 1

External Memory Interface 28 36

Microprocessor Interface 21 2 16

Miscellaneous 8 1 TDM Interface 6 7 25

Power 26

Ground 27

Total

187 + 26 + 27 = 240

59 50 78 26 27

MT90500

MEM_OE

MEM_WR2

MEM_WR3

MEM_CS1H

MEM_CS0H

MEM_DAT24

MEM_DAT25

MEM_DAT26

IO_VSS

MEM_DAT27

MEM_DAT28

IO_VDD_3V

MEM_DAT29

MEM_DAT30

MEM_DAT31

MEM_PAR3

MEM_DAT16

IO_VSS

MEM_DAT17

CORE_VDD_3V

MEM_DAT18

IO_VDD_3V

CORE_VSS

MEM_DAT20

MEM_DAT19

MEM_DAT21

MEM_DAT22

MEM_DAT23

MEM_PAR2

IO_VSS

IO_VDD_3V

IO_VSS

IO_VDD_5V

AEM

A15 A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4

IO_VSS

RING_VDD_3V

IO_VDD_5V

RING_VDD_3V

IO_VDD_5V

CLKx2/CLKx2PO

RDY/DTACK

IO_VDD_5V

RING_VSS

A1 CS D0 D1 D2

D3 D4 D5 D6 D7

IO_VSS

D8 D9

D10 D11 D12 D13

RING_VSS

D14 D15

PLLCLK

REF8KCLK

CLKx2NI

CLKx2NO

IO_VSS

CLKx2PI

FSYNC

CLKx1

SEC8K

CORSIGB

LOCx2

WR/R\W

RD/DS

182 184 186 188 190 192 194 196 198 200

202 204 206 208 210 212 214 216 218 220

222 224 226 228 230 232 234 236 238 240

240 PIN PQFP

22 24 26 28 30

2018161412108642

152154156158160162164166168170172174176178180

ST0

ST1

ST2

ST3

ST4

ST5

ST6

ST7

ST8

LOCx1

IO_VSS

IO_VDD_5V

IO_VSS

ST9

IO_VDD_5V

Figure 2. Pin Connections

ST10

ST11

IO_VSS

ST12

ST13

RING_VSS

RING_VDD_3V

ST14

ST15

LOCSTo

IO_VDD_5V

LSYNC

LOCSTi

IO_VSS

MEM_WR0

MEM_WR1

MEM_CS1L

MEM_CS0L

MEM_ADD7

IO_VDD_3V

MEM_ADD6

MEM_DAT8

MEM_DAT9

CORE_VDD_3V

IO_VSS

MEM_DAT10

MEM_DAT11

CORE_VSS

MEM_DAT12

MEM_DAT13

MEM_DAT14

MEM_DAT15

IO_VDD_3V

MEM_PAR1

MEM_ADD5

IO_VSS

MEM_ADD4

MEM_ADD3

MEM_ADD2

MEM_ADD1

MEM_ADD0

MEM_ADD17

MEM_ADD16

MT90500

MEM_ADD15

240 PIN PQFP

122124126128130132134136138140142144146148150

52 54 56 58 6050484644424038363432

120 118 116 114 112 110 108 106 104 102 100

98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 68 66 64 62

IO_VDD_3V IO_VSS MEM_ADD14 MEM_ADD13 MEM_ADD12 MEM_ADD11 MEM_DAT0 MEM_DAT1 MEM_DAT2

IO_VDD_3V IO_VSS

MEM_DAT3 MEM_DAT4 MEM_DAT5 MEM_DAT6 MEM_DAT7 MEMPAR0 MEM_ADD10 MEM_ADD9 CORE_VDD_3V

CORE_VSS MEM_ADD8 MEMCLK TMS

TDO TDI

TRST TCK

IO_VDD_3V IO_VSS TRISTATE IC IO_VDD_5V MCLK IO_VSS STXCLK INT EX_8KA PTXCLK RING_VDD_3V

RING_VSS PRXCLK RESET STXDATA0 STXDATA1 STXDATA2 STXDATA3 STXDATA4 STXDATA5 STXDATA6 STXDATA7 STXSOC STXEN

STXCLAV PRXDATA0 PRXDATA1 PRXDATA2 PRXDATA3 PRXDATA4

IO_VSS

CORSIGA

CORSIGC

CORSIGD

FREERUN

CORSIGE

PTXDATA0

MOTOROLA

INTEL/

RING_VSS

PTXDATA1

IO_VDD_5V

RING_VDD_3V

IO_VSS

PTXDATA2

PTXDATA3

PTXDATA4

PTXDATA5

PTXDATA6

PTXDATA7

PTXEN

PTXPAR

PTXSOC

PRXEN

PRXSOC

PTXCLAV

PRXCLAV

PRXDATA7

PRXDATA6

PRXDATA5

IO_VDD_5V

MT90500

4. Functional Description

As shown in Figure 1, “MT90500 Block Diagram,” on page 12, the MT90500 device consists of the following major components: TDM Module, External Memory Controller, TX_SAR, RX_SAR, UTOPIA Module, Clock Recovery, Microprocessor Interface, and Test Interface. This section descr ibes each module in detail.

4.1 TDM Module

This circuit module is the interface to the Time Division Multiplexed (TDM) buses, which carry N x 64kbps data. The TDM module interfaces are:

• 16 bidirectional TDM data streams on pins ST[15:0]; these pins can be conﬁgured through soft-

ware registers to support various bus formats (ST-BUS, MVIP, H-MVIP, SCSA, or IDL) and data rates of 2.048 Mbps, 4.096 Mbps, or 8.192 Mbps; (F or the selection of the b us type , see TDM Bus Type Register at address 6010h in Section 5.)

• the TDM bus clocks (CLKx2, CLKx1) and frame synchronization signal (FSYNC);

• the TDM bus ancillary signals such as SEC8K (MVIP) and CLKFAIL (SCSA);

• a local TDM bus (LOCx2, LOCx1, LSYNC, LOCSTi, and LOCSTo); the format of the bus, which

runs at 2.048 Mbps (LOCx2 = 4.096 Mbps), is user-programmable via software (see Local Bus Type Register at address 6020h).

The TDM module moves TDM data from the TDM serial inputs to the external memory (where it is read by the TX_SAR) in the transmit direction, and from the external memory (where it was written by the RX_SAR) to the TDM outputs in the receive direction. This is done with the aid of an internal TDM frame buff er, which is used to buffer 4 frames of each TDM channel in both directions; i.e. four frames in the receive direction (ATM to TDM), and four frames in the transmit direction (TDM to ATM). The TDM module can be divided into four main processes:

• TDM Clock Logic, which controls all the operations related to clock generation and clock signal

monitoring on the TDM bus;

• TDM Interface Operation, which controls the input and output of the serial TDM data;

• TDM Data to External Memory Process, which transfers TDM input data into Transmit Circular

Buffers in the external memory;

• External Memory to TDM Data Output Process, which transfers TDM output data from Receive

Circular Buffers in the external memory to the TDM output bus.

Each of these processes are described in detail below.

4.1.1 TDM Clock Logic

The TDM Clock Logic controls all of the operations related to clock generation and clock signal monitoring on the TDM bus. The block diagram of the TDM Clock Logic is shown in Figure 3. This module consists of several blocks, including: selection logic for an 8 kHz reference for the external PLL (REF8KCLK), the main TDM bus clock generation logic, the local TDM bus clock generation logic, the clock drivers & clock selection for the SEC8K signal, and the clock failure detection logic.

4.1.1.1 TDM Timing Modes

The MT90500 supports 4 major TDM timing modes. There are also a number of TDM timing features which are independent of the TDM timing mode being used:

• The SEC8K pin (MVIP compatibility) can be programmed as either output or input. The SEC8KEN

bit in the MCGCR Register (6090h) enables the SEC8K pin driver. If the SEC8K pin is enabled as an output, the SEC8KSEL bit in the same register selects the source for this signal (the EX_8KA input, or the internal 8 kHz FS_INT signal which is derived from CLK16).

MT90500

CLKx2

CLKx1

Main TDM Bus

FSYNC

MCLK

SEC8K

Square

SEC8K_SQ

MT90500

Master/Slave

SEC8KEN

1 0

SEC8KSEL

0 1

ATM Cells

Internal CPU Bus

External CPU Bus

FS_INT

FSYNC

FS_INT

EX_8KA_INT

SRTS Clock

FNXI

Adaptive

Clock

Recovery

Main TDM

Bus Timing

Generation

SRTS

and

Clock Logic

Square

LOCx2

PHLEN

CLK16

(16.384 MHz)

Divide by

1,2,4,or 8

DIV1...8

DIVCLK_SRC

Divide by 2

to 16384

RXVCLK SEC8K_INT

EX_8KA_INT

EX_8KA

All control bits shown are in Master Clock Generation Control Register (6090h).

BEPLL

REFSEL<1:0>

EX_8KA_SQ

Local TDM

Bus

Clock

Generation

Logic

1 0

CLKx2

CLKx1

FSYNC

LOCx1

LSYNC

PLLCLK

FREERUN

REF8KCLK

Detection

Logic

REF8KCLK

Clock Absent

Detection

Logic

Local TDM Bus

MT9041 or

other PLL

External

PLL

(Optional)

Figure 3 - TDM Clock Selection and Generation Logic

• The CLKx2 signal can be selected as single-ended or differential. (Differential CLKx2 allows com-

patibility with the H-MVIP bus.) In TDM Timing Slav e, the CLKx2 signal can be input on the CLKx2 pin, or the differential CLKx2PI and CLKx2NI pins. This selection is made with CLKTYPE in the TDM Bus Type Register at address 6010h. In TDM Timing Master, the CLKx2 signal is output on the CLKx2/CLKx2PO pin, and an inverted clock is available on the CLKx2NO pin.

The MT90500 supports the following TDM timing modes:

• TDM Timing Bus Slave - CLKx2 Reference (CLKMASTER = ‘0’ in TDM Bus Type Register at 6010h) In this mode, the MT90500 is conﬁgured as a TDM Timing Slave and all internal TDM timing is synchronized to

the TDM clock inputs: CLKx2, CLKx1, and FSYNC. The following sub-modes are also selectable:

• The CLKx1 can be an input at the CLKx1 pin, or it can be derived internally from CLKx2. This is

controlled by TCLKSYN (address 6010h). If the CLKx1 pin is not used as an input in TDM Slave mode, it remains high-impedance.

• TDM Timing Slave operation takes its 8 kHz framing from the FSYNC input pin, which would usu-

ally be driven by the TDM bus. To support other implementations, the REF8KCLK output remains active in TDM Slave mode. An 8 kHz reference output can be made available at REF8KCLK, selectable from the EX_8KA input, the SEC8K pin, or one of the internal dividers. In addition, the FREERUN output can be used to monitor the presence of REF8KCLK.

MT90500

• TDM Timing Bus Master - Freerun (CLKMASTER = ‘1’ in TDM Bus Type Register at 6010h) In this mode, the MT90500 is conﬁgured as the TDM Timing Master and the MT90500 drives the three TDM

bus clocks: CLKx2, CLKx1, and FSYNC . The MT90500 cloc k gener ator b lock uses either the MCLK input or the PLLCLK input to generate all of the required clocks. Typically in this mode MCLK or PLLCLK is connected to an oscillator, and no other synchronization source is used. Several selections must be made:

• The selection of MCLK or PLLCLK is determined by the BEPLL bits in the Master Clock Genera-

tion Control Register at 6090h.

• The selected clock is divided by 1, 2, 4, or 8 to obtain a 16.384 MHz clock, called CLK16. This divi-

sion is controlled by the DIV1...8 bits at 6090h.

• TDM Timing Bus Master - 8 kHz Reference (CLKMASTER = ‘1’ in TDM Bus Type Register at 6010h) In this mode, the MT90500 is conﬁgured as the TDM Timing Master and the MT90500 drives the three TDM

bus clocks, synchronized to one of several possible 8 kHz references. Typically, in this mode, the PLLCLK input is driven by an external PLL (such as the Mitel MT9041), which is controlled by the REF8KCLK and FREERUN outputs. The following options are also selectable:

• One of four 8 kHz reference sources must be selected, using the REFSEL bits at 6090h. (See

Figure 3 and Section 4.1.1.2 for further details.)

• If the external PLL is controlled by the FREERUN output pin, the pin’s operation must be speciﬁed

by the FREERUN bits at 6090h. The CPU can force the FREERUN pin to either state, or allow the FREERUN pin to follow the REF8KCLK failure-detection bit (REFFAIL at 6082h).

• Bus Master-Alternate (CLKMASTER = ‘0’, CLKALT = ‘1’ in TDM Bus Type Register at 6010h) In this mode, the MT90500 is conﬁgured as a TDM Timing Slave, but stands ready to become the Timing

Master, should the timing on the TDM bus fail. The switch is normally automatic (based on the CLKFAIL input), but can also performed by the CPU (for instance: by programming the chip into TDM Timing Master following a Clock Absent interrupt). The following options are also selectable:

• To make the switch from Alternate to Master automatic, several settings are required: CLKALT at

6010h is set HIGH, and the CORSIGA pin is conﬁgured as the CLKFAIL input (CORSIGACNF = “11” at 6004h).

• The Master-Alternate operates normally as a TDM Timing Slave, and has the same options as the

TDM Timing Slave listed above.

• The Master-Alternate can be set up to switch to Master-Freerun operation, should the TDM bus

clocks fail. The same options as listed above for Master-Freerun apply to this mode.

• The Master-Alternate can be set up to switch to Master-8 kHz Reference operation, should the

TDM bus clocks fail. The same options as listed above for Master-8 kHz Reference apply to this mode. Additionally, REF8KCLK can be obtained from the TDM bus by dividing CLKx2. This allows the external PLL to be phase-locked to the TDM bus clocks. Note that in this case the FREERUN output should be set up to automatically place the external PLL in freerun should the TDM bus clocks fail.

• The internal 8 kHz (FS_INT) of the Master-Alternate can be phase-locked to the TDM bus FSYNC

by setting PHLEN = ‘1’ at 6090h. (This is only valid when the FSYNC type at 6010h is set to “00”.) This will align the internal “stand-by” FSYNC, CLKx2, and CLKx1 to the TDM bus to within a clock cycle of the internal 16.384 MHz clock, allowing for minimal phase-shift should the Master-Alternate MT90500 take over the TDM bus clocks.

4.1.1.2 REF8KCLK Selection Logic

The REF8KCLK output pin of the MT90500 is intended to provide a clock ref erence to an optional external PLL. This signal would usually be an 8 kHz frame pulse, but other signals are possible. The external PLL (e.g. Mitel MT9041) can be used to multiply the REF8KCLK output to 16.384 MHz (or 32.768 MHz) and attenuate jitter. The 16.384 MHz can then be applied to the PLLCLK input pin to allow the MT90500 to generate the TDM

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