MITEL MT9044AL, MT9044AP Datasheet

MT9044

T1/E1/OC3 System Synchronizer

Advance Information

Features

• Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4 timing for DS1 interfaces

• Supports ITU-T G.812 Type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing for E1 interfaces

• Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals

• Provides C1.5, C2, C3, C4, C6, C8, C16, and C19 (STS-3/OC3 clock divided by 8) output clock signals

• Provides 5 different styles of 8 KHz framing pulses

• Holdover frequency accuracy of 0.05 PPM

• Holdover indication

• Attenuates wander from 1.9Hz

• Provides Time Interval Error (TIE) correction

• Accepts reference inputs from two independent sources

• JTAG Boundary Scan

Applications

• Synchronization and timing control for multitrunk T1,E1 and STS-3/OC3 systems

• ST-BUS clock and frame pulse sources

DS5058 ISSUE 3 September 1999

Ordering Information

MT9044AP 44 Pin PLCC MT9044AL 44 Pin MQFP

-40 to +85 °C

Description

The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links.

The MT9044 generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz,

1.544MHz, or 8kHz input reference.

The MT9044 is compliant with AT&T TR62411 and Bellcore GR-1244-CORE Stratum 3, Stratum 4 Enhanced, and Stratum 4; and ETSI ETS 300 011. It will meet the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase change slope, holdover frequency and MTIE requirements for these speciﬁcations.

TCK

TDI

TMS

TRST

TDO

PRI

SEC

RSEL LOS1 LOS2

Corrector

TIE

Corrector

Enable

RST

TCLR

TIE

Circuit

State Select

HOLDOVER

Virtual

Reference

Impairment

Monitor

Guard Time

Circuit

OSCoOSCi

Master Clock

IEEE

1149.1a

Selected

Reference

Select

MUX

Reference Select

Automatic/Manual

Control State Machine

MS1 MS2 GTo GTi FS1 FS2

Reference

DPLL

State Select

Input

VDD VSS

Output

Interface

Circuit

Feedback

Frequency

Select

MUX

Figure 1 - Functional Block Diagram

APLL

C19o C1.5o

C3o C2o

C4o C6o

C8o C16o F0o F8o

F16o RSP

TSP

ACKi ACKo

MT9044 Advance Information

TDI

RST

FS1

343536

FS2

33 32 31 30 29 28 27 26 25 24 23

TEST RSEL

MS1 MS2

TDO

LOS1 LOS2 GTo VSS GTi HOLDOVER

VDD

OSCo

OSCi

VSS

F16o

RSP

F0o

TSP

F8o

C1.5o AVDD

SEC

PRI

TRST

TCLR

7 8

9 10 11 12 13 14 15 16 17

18 19 20 21 22 23 24

MT9044

VSS

TCK

2564344

TDI

TMS

RST

25 26 27 28

FS1

404142

FS2

39 38 37 36 35 34 33 32 31 30 29

TEST RSEL

MS1 MS2

TDO

LOS1 LOS2 GTo VSS GTi HOLDOVER

VDD

OSCo

OSCi

VSS

F16o

RSP

F0o

TSP

F8o

C1.5o AVDD

SEC

PRI

TRST

TCLR

42 41

1 2 3 4 5 6 7 8

9 10 11

12 13 14 15 16 17 18

MT9044AL

VSS

TCLK

404344 3738

TMS

19 20 21 22

C3o

C2o

C4o

C19o

ACKi

VSS

C4o

C2o

C6o

C8o

VDD

C16o

ACKo

C3o

ACKi

C19o

VSS

C8o

C6o

VDD

C16o

ACKo

Figure 2 - Pin Connections

Pin Description

Pin #

PLCC

1,10,

23,31

Pin #

MQFP

39,4,17

Name Description

Ground. 0 Volts.

,25

2 40 TCK Test Clock (TTL Input): Provides the clock to the JTAG test logic. This pin is

internally pulled up to VDD.

341TCLR TIE Circuit Reset (TTL Input): A logic low at this input resets the Time Interval

Error (TIE) correction circuit resulting in a re-alignment of input phase with output phase as shown in Figure 19. The TCLR pin should be held low for a minimum of 300ns. This pin is internally pulled down to VSS.

442TRST Test Reset (TTL Input): Asynchronously initializes the JTAG TAP controller by

putting it in the Test-Logic-Reset state. This pin is internally pulled down to VSS.

543 SEC Secondary Reference (TTL Input). This is one of two (PRI & SEC) input

reference sources (falling edge) used for synchronization. One of three possible frequencies (8kHz, 1.544MHzMHz, or 2.048MHz) may be used. The selection of the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual). This pin is internally pulled up to VDD.

6 44 PRI Primary Reference (TTL Input). See pin description for SEC. This pin is

internally pulled up to VDD.

7,28 1,22 V

Positive Supply Voltage. +5VDC nominal.

8 2 OSCo Oscillator Master Cloc k (CMOS Output). For crystal operation, a 20MHz crystal

is connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left unconnected, see Figure 9.

9 3 OSCi Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is

connected from this pin to OSCo, see Figure 10. F or clock oscillator oper ation, this pin is connected to a clock source, see Figure 9.

11 5 F16o Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active

low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 8.192 Mb/s. See Figure 20.

Advance Information MT9044

Pin Description (continued)

Pin #

PLCC

12 6 RSP Receive Sync Pulse (CMOS Output). This is an 8kHz 488ns active high framing

13 7 F0o Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active

14 8 TSP T ransmit Sync Pulse (CMOS Output). This is an 8kHz 488ns activ e high fr aming

15 9 F8o Frame Pulse (CMOS Output). This is an 8kHz 122ns active high framing pulse,

16 10 C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications. 17 11 AVdd Analog Vdd. +5VDC nominal. 18 12 C3o Clock 3.088MHz (CMOS Output). This output is used in T1 applications. 19 13 C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at

20 14 C4o Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at

Pin #

MQFP

Name Description

pulse, which marks the end of an ST-BUS frame. This is typically used for connection to the Siemens MUNICH-32 device. See Figure 21.

low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.

pulse, which marks the beginning of an ST-BUS frame. This is typically used for connection to the Siemens MUNICH-32 device. See Figure 21.

which marks the beginning of a frame. See Figure 20.

2.048Mb/s.

2.048Mb/s and 4.096Mb/s. 21 15 C19o Clock 19.44MHz (CMOS Output). This output is used in OC3/STS3 applications. 22 16 ACKi Analog PLL Clock Input (CMOS Input). This input clock is a reference for an

internal analog PLL. This pin is internally pulled down to VSS.

24 18 ACKo Analog PLL Clock Output (CMOS Output). This output clock is generated by

the internal analog PLL.

25 19 C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at

8.192Mb/s. 26 20 C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with

a 16.384MHz clock. 27 21 C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications. 29 23 HOLDOVER Holdover (CMOS Output). This output goes to a logic high whenever the digital

PLL goes into holdover mode. 30 24 GTi Guard Time (Schmitt Input). This input is used by the MT9044 state machine in

both Manual and Automatic modes. The signal at this pin aff ects the state changes

between Primary Holdover Mode and Primary Normal Mode, and Primary

Holdover Mode and Secondary Normal Mode. The logic level at this input is gated

in by the rising edge of F8o. See Tables 4 and 5. 32 26 GTo Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o,

buffered and output on GTo. This pin is typically used to driv e the GTi input through

an RC circuit. 33 27 LOS2 Secondary Reference Loss (TTL Input). This input is normally connected to the

loss of signal (LOS) output signal of a Line Interface Unit (LIU). When high, the

SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs

control the MT9044 state machine when operating in Automatic Control. The logic

level at this input is gated in by the rising edge of F8o. This pin is internally pulled

down to VSS.

MT9044 Advance Information

Pin Description (continued)

Pin #

PLCC

34 28 LOS1 Primary Reference Loss (TTL Input). Typically, external equipment applies a

35 29 TDO Test Serial Data Out (TTL Output). JTAG serial data is output on this pin on the

36 30 MS2 Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1,

37 31 MS1 Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the

38 32 RSEL Reference Source Select (TTL Input). In Manual Control, a logic low selects the

39 33 TEST Test (TTL Input). This input is normally tied low. When pulled high, it enables

Pin #

MQFP

Name Description

logic high to this input when the PRI reference signal is lost or invalid. The logic level at this input is gated in b y the rising edge of F8o . See LOS2 description. This pin is internally pulled down to VSS.

falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.

determines the device’s mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.

rising edge of F8o. See pin description for MS2. This pin is internally pulled down to VSS.

PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this input is gated in by the rising edge of F8o. See Table 2. This pin is internally pulled down to VSS.

internal test modes. This pin is internally pulled down to VSS.

40 34 FS2 Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects

which of three possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input

to the PRI and SEC inputs. See Table 1. 41 35 FS1 Frequency Select 1 (TTL Input). See pin description for FS2. 42 36 TDI Test Serial Data In (TTL Input). JTAG serial test instructions and data are shifted

in on this pin. This pin is internally pulled up to VDD. 43 37 RST Reset (Schmitt Input). A logic low at this input resets the MT9044. To ensure

proper operation, the device must be reset after changes to the method of control,

reference signal frequency changes and power-up. The RST pin should be held

low for a minimum of 300ns. While the RST pin is low, all frame and clock outputs

are at logic high. Following a reset, the input reference source and output clocks

and frame pulses are phase aligned as shown in Figure 19. 44 38 TMS Test Mode Select (TTL Input). JTAG signal that controls the state transitions of

the TAP controller. This pin is internally pulled up to VDD.

Advance Information MT9044

Functional Description

The MT9044 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links.

Figure 1 shows the functional block diagram which is described in the following sections.

Reference Select MUX Circuit

The MT9044 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables 1, 4 and 5.

Frequency Select MUX Circuit

The MT9044 operates with one of three possible input reference frequencies (8kHz, 1.544MHz or

2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1.

FS2 FS1 Input Frequency

0 0 Reserved 0 1 8kHz 1 0 1.544MHz 1 1 2.048MHz

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the output signals will occur. A phase step at the input of the DPLL will lead to unacceptable phase changes in the output signal.

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch, from one reference to the other, the State Machine ﬁrst changes the mode of the device

PRI or SEC

from

Reference

Select Mux

Programmable

Delay Circuit

TCLR

Resets Delay

Control

Circuit

TIE Corrector

Enable

from

State Machine

Control Signal

Delay Value

Compare

Circuit

Feedback

Signal from

Frequency

Select MUX

Figure 3 - TIE Corrector Circuit

Virtual

Reference

to DPLL

MT9044 Advance Information

from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch had not taken place. The State Machine then returns the device to Normal Mode.

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL.

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9044 consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz,

1.544MHz or 2.048MHz).

Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms speciﬁed by AT&T TR62411, and Bellcore GR-1244-CORE.

Loop Filter - the Loop Filter is similar to a ﬁrst order low pass ﬁlter with a 1.9 Hz cutoff frequency for all three reference frequency selections (8kHz,

1.544MHz or 2.048MHz). This ﬁlter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel.

The state diagrams of Figure 7 and 8 indicate the state changes that activate the TIE Corrector Circuit.

Virtual Reference from

TIE Corrector

Phase

Detector

Feedback Signal from Frequency Select MUX

Limiter Loop Filter

Figure 4 - DPLL Block Diagram

Control Circuit - the Control Circuit uses status and

control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freer un.

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and ﬁltered signal from the Loop FIlter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9044.

State Select from

Input Impairment

Monitor

State Select from

State Machine

Digitally

Controlled

Oscillator

Control Circuit

DPLL Reference to Output Interface Circuit

Advance Information MT9044

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal.

In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the DCO was generating while in Normal Mode.

T1 Divider

12MHz

Tapped

Delay

Line

C1.5o C3o

In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit , an E1 Divider Circuit, a DS2 Divider Circuit and an analog PLL to generate the required output signals.

Four tapped delay lines are used to generate a

16.384MHz, 12.352MHz, 12.624MHz and 19.44 MHz signals.

The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle.

The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.

The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal 50% duty cycle.

C2o C4o C8o C16o F0o F8o F16o

C6o

C19o

ACKo

From

DPLL

ACKi

Tapped

Delay

Line

Tapped

Delay

Line

Tapped

Delay

Line

16MHz

12MHz

19MHz

E1 Divider

DS2 Divider

Analog PLL

Figure 5 - Output Interface Circuit Block

Diagram

The frame pulse outputs (F0o, F8o, F16o, TSP, RSP) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o, F16o and C6o are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figures 20 and 21.

All frame pulse and clock outputs hav e limited driving capability, and should be buffered when driving high capacitance (e.g. 30pF) loads.

Analog Phase Lock Loop (APLL)

The analog PLL is intended to be used to achieve a 50% duty cycle output clock. Connecting C19o to ACKi will generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle. The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low jitter level a separate pin is provided to power (AVdd) the analog PLL.

MT9044 Advance Information

Input Impairment Monitor

This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g. ±0.05ppm). The the Auto-Holdover circuit does not use TIE correction. Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is the same as just prior to the switch to Auto-Holdover).

Automatic/Manual Control State Machine

Guard Time Circuit

The GTi pin is used by the Automatic/Manual Control State Machine in the MT9044 under either Manual or Automatic control. The logic level at the GTi pin performs two functions, it enables and disables the TIE Corrector Circuit (Manual and Automatic), and it selects which mode change takes place (Automatic only). See the Applications - Guard Time section.

For both Manual and Automatic control, when switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when GTi=1, and disabled when GTi=0.

Under Automatic control and in Primary Normal Mode, two state changes are possible (not counting Auto-Holdover). These are state changes to Primary Holdover or to Secondary Normal. The logic level at the GTi pin determines which state change occurs. When GTi=0, the state change is to Primary Holdover. When GTi=1, the state change is to Secondary Normal.

The Automatic/Manual Control State Machine allows the MT9044 to be controlled automatically (i.e. LOS1, LOS2 and GTi signals) or controlled manually (i.e. MS1, MS2, GTi and RSEL signals). With manual control a single mode of operation (i.e. Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2 and GTi signals determines the sequence of modes that the MT9044 will follow.

As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the DPLL and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1, MS2 and GTi of the Guard Time Circuit (See Figure 6).

All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of Operation section for full details on Automatic Control and Manual Control.

Reference

Select MUX

To TIE

Corrector

Enable

To DPLL

State

Select

Master Clock

The MT9044 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.

Control and Modes of Operation

The MT9044 can operate either in Manual or Automatic Control. Each control method has three possible modes of operation, Normal, Holdover and Freerun.

As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control.

Control RSEL Input Reference

MANUAL 0 PRI

1 SEC

AUTO 0 State Machine Control

RSEL

LOS1 LOS2

Automatic/Manual Control

State Machine

MS1

MS2

Figure 6 - Automatic/Manual Control State

Machine Block Diagram

To and From Guard Time Circuit

1 Reserved

Table 2 - Input Reference Selection

Advance Information MT9044

Normal Mode

MS2 MS1 Control Mode

0 0 MANUAL NORMAL 0 1 MANUAL HOLDOVER 1 0 MANUAL FREERUN 1 1 AUTO State Machine Control

Table 3 - Operating Modes and States

Manual Control

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9044 provides timing (C1.5o, C2o, C3o, C4o, C8o, C16o, and C19) and frame synchronization (F0o, F8o, F16o, RSP, TSP) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or

2.048MHz.

Manual Control should be used when either very simple MT9044 control is required, or when complex control is required which is not accommodated by Automatic Control. For example, very simple control could include operation in a system which only requires Normal Mode with reference switching using only a single input stimulus (RSEL). Very simple control would require no external circuitry. Complex control could include a system which requires state changes between Normal, Holdover and Freerun Modes based on numerous input stimuli. Complex control would require external circuitry, typically a microcontroller.

Under Manual Control, one of the three modes is selected by mode/control select pins MS2 and MS1. The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 7 for details of the state change sequences.

Automatic Control

Automatic Control should be used when simple MT9044 control is required, which is more complex than the very simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a microcontroller. For example, simple control could include operation in a system which can be accommodated by the Automatic Control State Diagram shown in Figure 8.

Automatic Control is also selected by mode/control pins MS2 and MS1. However, the mode and active reference source is selected automatically by the internal Automatic State Machine (See Figure 6). The mode and reference changes are based on the logic levels on the LOS1, LOS2 and GTi control pins. Refer to Table 5 and Figure 8 for details of the state change sequences.

From a reset condition, the MT9044 will take up to 25 seconds for the output signal to be phase locked to the selected reference.

The selection of input references is control dependent as shown in State Tables 4 and 5. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Holdover Mode

Holdover Mode is typically used for short durations (e.g. 2 seconds) while network synchronization is temporarily disrupted.

In Holdover Mode, the MT9044 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal.

When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9044 output frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device.

The frequency accuracy of Holdover Mode is ±0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. This meets the Bellcore GR-1244-CORE Stratum 3 requirement of ±0.37ppm (255 frame slips per 24 hours).

Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a ±32ppm

+ 21 hidden pages