MITEL MT9042CP Datasheet

MT9042C

Multitrunk System Synchronizer

Advance Information

Features

• Meets jitter requirements for: AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces; and for ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 for E1 interfaces

• Provides C1.5, C3, C2, C4, C8 and C16 output clock signals

• Provides 8kHz ST-BUS framing signals

• Selectable 1.544MHz, 2.048MHz or 8kHz input reference signals

• Accepts reference inputs from two independent sources

• Provides bit error free reference switching meets phase slope and MTIE requirements

• Operates in either Normal, Holdover and Freerun modes

Applications

• Synchronization and timing control for multitrunk T1 and E1 systems

• ST-BUS clock and frame pulse sources

• Primary Trunk Rate Converters

DS5144 ISSUE 2 September 1999

Ordering Information

MT9042CP 28 Pin PLCC

-40°C to +85°C

Description

The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links.

The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz,

1.544MHz, or 8kHz input reference.

The MT9042C is compliant with AT&T TR62411 Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300

011. It will meet the jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, holdover accuracy, capture range, phase slope and MTIE requirements for these speciﬁcations.

OSCi

OSCo

PRI

SEC

RSEL LOS1 LOS2

TRST

Virtual Refer-

State

Select

ence

DPLL

State

Select

Input

Impairment

Monitor

Guard Time

Circuit

Master

Clock

Selected

Reference

Select

MUX

Reference

Select

Automatic/Manual

Control State Machine

MS1 MS2 GTo GTi

Refer-

Corrector

Enable

TIE

Corrector

Circuit

ence

TIE

RST

Figure 1 - Functional Block Diagram

VDD VSS

Feedback

Output

Interface

Circuit

Frequency

Select

MUX

FS1 FS2

C1.5o C3o

C2o C4o

C8o C16o F0o F8o

F16o

MT9042C Advance Information

VSS

TRST

SEC

PRI

RST

FS1

FS2

VDD

OSCo

OSCi

F16o

F0o F8o

C1.5o

432 5

6 7

9 10 11

12 13 14 15 16 17 18

C2o

C3o

C4o

VSS

C8o

RSEL

MS1

MS2

LOS1

LOS2

GTo GTi

VDD

C16o

Figure 2 - Pin Connections

Pin Description

Pin # Name Description (see notes 1 to 5)

1,15 V

2 TRST TIE Circuit Reset (TTL Input). A logic low at this input resets the Time Interval Error (TIE)

3 SEC Secondary Reference (TTL Input). This is one of two (PRI & SEC) input reference

Ground. 0 Volts.

correction circuit resulting in a re-alignment of input phase with output phase as shown in Figure 19. The TRST pin should be held low for a minimum of 300ns.

sources (falling edge) used for synchronization. One of three possible frequencies (8kHz,

1.544MHzMHz, or 2.048MHz) may be used. The selection of the input reference is based upon the MS1, MS2, LOS1, LOS2, RSEL, and GTi control inputs (Automatic or Manual).

4 PRI Primary Reference (TTL Input). See pin description for SEC.

5,18 V

Positive Supply Voltage. +5VDC nominal.

6 OSCo Oscillator Master Clock (CMOS Output). For crystal operation, a 20MHz crystal is

connected from this pin to OSCi, see Figure 10. For clock oscillator operation, this pin is left unconnected, see Figure 9.

7 OSCi Oscillator Master Clock (CMOS Input). For crystal operation, a 20MHz crystal is

connected from this pin to OSCo, see Figure 10. For clock oscillator operation, this pin is connected to a clock source, see Figure 9.

8 F16o Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 16.384Mb/s. See Figure 20.

9 F0o Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low

framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. See Figure 20.

10 F8o Frame Pulse ST-BUS 8.192Mb/s (CMOS Output). This is an 8kHz 122ns active high

framing pulse, which marks the beginning of an ST-BUS frame. This is used for ST-BUS

operation at 8.192Mb/s. See Figure 20. 11 C1.5o Clock 1.544MHz (CMOS Output). This output is used in T1 applications. 12 C3o Clock 3.088MHz (CMOS Output). This output is used in T1 applications. 13 C2o Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. 14 C4o Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s

and 4.096Mb/s.

Advance Information MT9042C

Pin Description

Pin # Name Description (see notes 1 to 5)

16 C8o Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. 17 C16o Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation at 16.384Mb/

19 GTi Guard Time (Schmitt Input). This input is used by the MT9042B state machine in both

Manual and Automatic modes. The signal at this pin affects the state changes between Primary Holdover Mode and Primary Normal Mode, and Primary Holdover Mode and Secondary Normal Mode. The logic level at this input is gated in by the rising edge of F8o. See Tables 4 and 5.

20 GTo Guard Time (CMOS Output). The LOS1 input is gated by the rising edge of F8o, buffered

and output on GTo. This pin is typically used to drive the GTi input through an RC circuit.

21 LOS2 Secondary Reference Loss (TTL Input). This input is normally connected to the loss of

signal (LOS) output signal of a Line Interface Unit (LIU). When high, the SEC reference signal is lost or invalid. LOS2, along with the LOS1 and GTi inputs control the MT9042B state machine when operating in Automatic Control. The logic level at this input is gated in by the rising edge of F8o.

22 LOS1 Primary Reference Loss (TTL Input). Typically , external equipment applies a logic high to

this input when the PRI reference signal is lost or inv alid. The logic le vel at this input is gated in by the rising edge of F8o. See LOS2 description.

23 MS2 Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1, determines the

device’ s mode (Automatic or Manual) and state (Normal, Holdover or F reerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3.

24 MS1 Mode/Control Select 1 (TTL Input). The logic level at this input is gated in by the rising

edge of F8o. See pin description for MS1.

25 RSEL Reference Source Select (TTL Input). In Manual Control, a logic low selects the PRI

(primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. In Automatic Control, this pin must be at logic low. The logic level at this input is gated in by the rising edge of F8o. See Table 2.

26 FS2 Frequency Select 2 (TTL Input). This input, in conjunction with FS1, selects which of three

possible frequencies (8kHz, 1.544MHz, or 2.048MHz) may be input to the PRI and SEC

inputs. See Table 1. 27 FS1 Frequency Select 1 (TTL Input). See pin description for FS2. 28 RST Reset (Schmitt Input). A logic low at this input resets the MT9042B. To ensure proper

operation, the device must be reset after changes to the method of control, reference signal

frequency changes and power-up. TheRST pin should be held low for a minim um of 300ns.

While the RST pin is low, all frame and clock outputs are at logic high. F ollowing a reset, the

input reference source and output clocks and frame pulses are phase aligned as shown in

Figure 19.

Notes:

1. All inputs are CMOS with either TTL compatible logic levels, CMOS compatible logic levels or Schmitt trigger compatible logic levels as indicated in the Pin Description.

2. All outputs are CMOS with CMOS compatible logic levels.

3. See DC Electrical Characteristics for static logic threshold values.

4. See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for dynamic logic threshold values.

5. Unless otherwise stated, all unused inputs should be connected to logic high or logic low and all unused outputs should be left open circuit.

MT9042C Advance Information

Functional Description

The MT9042C is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for T1 and E1 Primary Rate Digital Transmission links.

Figure 1 is a functional block diagram which is described in the following sections.

Reference Select MUX Circuit

The MT9042C accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Tables 1, 4 and 5.

Frequency Select MUX Circuit

The MT9042C operates with one of three possible input reference frequencies (8kHz, 1.544MHz or

2.048MHz). The frequency select inputs (FS1 and FS2) determine which of the three frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1.

FS2 FS1 Input Frequency

0 0 Reserved 0 1 8kHz 1 0 1.544MHz 1 1 2.048MHz

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the output signals will occur. A phase step at the input of the DPLL will lead to unacceptable phase changes in the output signal.

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch, from one reference to the other, the State Machine ﬁrst changes the mode of the device

TRST

Resets Delay

PRI or SEC

from

Reference

Select Mux

Control

Circuit

Programmable

Delay Circuit

TIE Corrector

Enable

from

State Machine

Control Signal

Delay Value

Virtual

Reference

to DPLL

Compare

Circuit

Feedback

Signal from

Frequency

Select MUX

Figure 3 - TIE Corrector Circuit

Advance Information MT9042C

Virtual Reference

from

TIE Corrector

Frequency Select MUX

Phase

Detector

Feedback Signal

from

Limiter Loop Filter

State Select

Input Impairment Monitor

Figure 4 - DPLL Block Diagram

from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch not taken place. The State Machine then returns the device to Normal Mode.

The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL.

DPLL Reference

Output Interface Circuit

from

State Select

from

State Machine

Digitally

Controlled

Oscillator

Control

Circuit

The state diagrams of Figure 7 and 8 indicate under which state changes the TIE Corrector Circuit is activated.

Digital Phase Lock Loop (DPLL)

As shown in Figure 4, the DPLL of the MT9042C consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit.

Phase Detector - the Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz,

1.544MHz or 2.048MHz).

Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch.

The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TRST) pin. A minimum reset pulse width is 300ns. This results in a phase alignment between the input reference signal and the output signal as shown in Figure 20. The speed of the phase alignment correction is limited to 5ns per 125us, and convergence is in the direction of least phase travel.

Limiter - the Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125us. This is well within the maximum phase slope of 7.6ns per 125us or 81ns per 1.326ms speciﬁed by AT&T TR62411.

Loop Filter - the Loop Filter is similar to a ﬁrst order low pass ﬁlter with a 1.9 Hz cutoff frequency for all three reference frequency selections (8kHz,

1.544MHz or 2.048MHz). This ﬁlter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met.

Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.

MT9042C Advance Information

Digitally Controlled Oscillator (DCO) - the DCO receives the limited and ﬁltered signal from the Loop FIlter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the MT9042C.

In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal.

In Holdover Mode, the DCO is free running at a frequency equal to the last (less 30ms to 60ms) frequency the DCO was generating while in Normal Mode.

In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source.

Output Interface Circuit

The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses two Tapped Delay Lines followed by a T1 Divider Circuit and an E1 Divider Circuit to generate the required output signals.

C1.5o C3o

C2o C4o C8o C16o F0o F8o F16o

From

DPLL

Tapped

Delay

Line

Tapped

Delay

Line

T1 Divider

12MHz

E1 Divider

16MHz

The T1 Divider Circuit uses the 12.384MHz signal to generate two clock outputs. C1.5o and C3o are generated by dividing the internal C12 clock by four and eight respectively. These outputs have a nominal 50% duty cycle.

The frame pulse outputs (F0o, F8o, F16o) are generated directly from the C16 clock.

The T1 and E1 signals are generated from a common DPLL signal. Consequently, the clock outputs C1.5o, C3o, C2o, C4o, C8o, C16o, F0o and F16o are locked to one another for all operating states, and are also locked to the selected input reference in Normal Mode. See Figures 20 & 21.

All frame pulse and clock outputs hav e limited driving capability, and should be buffered when driving high capacitance (e.g., 30pF) loads.

Input Impairment Monitor

This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is outside the auto-holdover capture range (See AC Electrical Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g.,±0.05ppm). The the Auto-Holdover circuit does not use TIE correction. Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved (is the same as just prior to the switch to Auto-Holdover).

Automatic/Manual Control State Machine

Figure 5 - Output Interface Circuit Block

Diagram

Two tapped delay lines are used to generate a

16.384MHz signal and a 12.352MHz signal.

The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs. The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively. These outputs have a nominal 50% duty cycle.

The Automatic/Manual Control State Machine allows the MT9042C to be controlled automatically (i.e., LOS1, LOS2 and GTi signals) or controlled manually (i.e., MS1, MS2, GTi and RSEL signals). With manual control a single mode of operation (i.e., Normal, Holdover and Freerun) is selected. Under automatic control the state of the LOS1, LOS2 and GTi signals determines the sequence of modes that the MT9042C will follow.

As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit, the

Advance Information MT9042C

DPLL and the Guard Time Circuit. Control is based on the logic levels at the control inputs LOS1, LOS2, RSEL, MS1, MS2 and GTi of the Guard Time Circuit (See Figure 6).

RSEL LOS1 LOS2

Reference

Select MUX

Automatic/Manual Control

MS1

To TIE

Corrector

Enable

State Machine

MS2

To DPLL

State

Select

and From

Guard Time

Circuit

Figure 6 - Automatic/Manual Control State

Machine Block Diagram

All state machine changes occur synchronously on the rising edge of F8o. See the Controls and Modes of Operation section for full details on Automatic Control and Manual Control.

Guard Time Circuit

Control and Modes of Operation

The MT9042C can operate either in Manual or Automatic Control. Each control method has three possible modes of operation, Normal, Holdover and Freerun.

As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control.

Control RSEL Input Reference

MANUAL 0 PRI

1 SEC

AUTO 0 State Machine Control

1 Reserved

Table 2 - Input Reference Selection

MS2 MS1 Control Mode

0 0 MANUAL NORMAL

The GTi pin is used by the Automatic/Manual Control State Machine in the MT9042C under either Manual or Automatic control. The logic level at the GTi pin performs two functions, it enables and disables the TIE Corrector Circuit (Manual and Automatic), and it selects which mode change takes place (Automatic only). See the Applications - Guard Time section.

For both Manual and Automatic control, when switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when GTi=1, and disabled when GTi=0.

Under Automatic control and in Primary Normal Mode, two state changes are possible (not counting Auto-Holdover). These are state changes to Primary Holdover or to Secondary Normal. The logic level at the GTi pin determines which state change occurs. When GTi=0, the state change is to Primary Holdover. When GTi=1, the state change is to Secondary Normal.

Master Clock

The MT9042C can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.

0 1 MANUAL HOLDOVER 1 0 MANUAL FREERUN 1 1 AUTO State Machine Control

Table 3 - Operating Modes and States

Manual Control

Manual Control should be used when either very simple MT9042C control is required, or when complex control is required which is not accommodated by Automatic Control. For example, very simple control could include operation in a system which only requires Normal Mode with reference switching using only a single input stim ulus (RSEL). Very simple control would require no external circuitry. Complex control could include a system which requires state changes between Normal, Holdover and Freerun Modes based on numerous input stimuli. Complex control would require external circuitry, typically a microcontroller.

Under Manual Control, one of the three modes is selected by mode/control select pins MS2 and MS1. The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 7 for details of the state change sequences.

MT9042C Advance Information

Automatic Control

Automatic Control should be used when simple MT9042C control is required, which is more complex than the very simple control provide by Manual Control with no external circuitry, but not as complex as Manual Control with a microcontroller. For example, simple control could include operation in a system which can be accommodated by the Automatic Control State Diagram shown in Figure 8.

Automatic Control is also selected by mode/control pins MS2 and MS1. However, the mode and active reference source is selected automatically by the internal Automatic State Machine (See Figure 6). The mode and reference changes are based on the logic levels on the LOS1, LOS2 and GTi control pins. Refer to Table 5 and Figure 8 for details of the state change sequences.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9042C provides timing (C1.5o, C2o, C3o, C4o, C8o and C16o) and frame synchronization (F0o, F8o, F16o) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz or 2.048MHz.

From a reset condition, the MT9042C will take up to 25 seconds for the output signal to be phase locked to the selected reference.

When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the MT9042C output frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device.

The frequency accuracy of Holdover Mode is ±0.05ppm, which translates to a worst case 35 frame (125us) slips in 24 hours. This exceeds the AT&T TR62411 Stratum 3 requirement of ±0.37ppm (255 frame slips per 24 hours).

Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift on the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a ±32ppm master clock may have a temperature coefﬁcient of ±0.1ppm per degree C. So a 10 degree change in temperature, while the MT9042C is in Holdover Mode may result in an additional offset (over the ±0.05ppm) in frequency accuracy of ±1ppm. Which is much greater than the ±0.05ppm of the MT9042C.

The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from

0.05ppm to 0.10ppm.

Freerun Mode

The selection of input references is control dependent as shown in state tables 4 and 5. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Holdover Mode

Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily disrupted.

In Holdover Mode, the MT9042C provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal.

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved.

In Freerun Mode, the MT9042C provides timing and synchronization signals which are based on the master clock frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output clock is required, the master clock must also be ±32ppm. See Applications - Crystal and Clock Oscillator sections.

Advance Information MT9042C

Description State

Input Controls Freerun

Normal

(PRI)

Normal

(SEC)

Holdover

(PRI)

Holdover

(SEC)

MS2 MS1 RSEL GTi S0 S1 S2 S1H S2H

0 0 0 0 S1 - S1 MTIE S1 S1 MTIE 0 0 0 1 S1 - S1 MTIE S1 MTIE S1 MTIE 0 0 1 X S2 S2 MTIE - S2 MTIE S2 MTIE 0 1 0 X / S1H / - / 0 1 1 X / S2H S2H / 10 X X - S0 S0 S0 S0

Legend:

- No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Manual Control State Diagram for state changes to and from Auto-Holdover State

Table 4 - Manual Control State Table

Normal

Primary

(000)

(GTi=0)

(GTi=1)

NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal

Movement to Normal State from any state requires a valid input signal

{A} {A}

S1A

Auto-Holdover

Primary

(000)

S1H

Holdover

Primary

(010)

Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit)

Freerun

(10X)

S2A

Auto-Holdover

Secondary

(001)

S2H

Holdover

Secondary

(011)

Normal

Secondary

(001)

Figure 7 - Manual Control State Diagram

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