MITEL MT9041AP Datasheet



MT9041

Multiple Output Trunk PLL

Advance Information

Features

• Provides T1 and E1 clocks, and ST-BUS/GCI framing sign als loc ked t o an in put refe renc e of either 8 kHz (fram e pulse ), 1.54 4 MH z (T1) , or

2.048 MHz (E 1)

• Meets AT & T TR62411 and ETSI ETS 300 011 specificatio ns for a 1.544 M Hz (T1), or

2.048 MHz (E 1) in put refe renc e

• Typical unfiltered intrinsic output jitter is

0.013 UI peak -to- peak

• Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz a nd 5 0 dB @ 5 to 40 k Hz

• Low power CM OS tech nolog y

Applications

• Synchronization and timing control for T1 and E1 digital transmission links

• ST-BUS clock and f rame pulse s ource s

• Primary Trunk Rate Converters

ISSUE 1 May 1995

Ordering Information

MT9041AP 28 Pin PLCC

C to +85°C

-40

Description

The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz, or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz.

The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192 MHz, and 16.384 MHz for backplane synchronization.

T1.5)

PRI

IC0

IC1

VDD VSS

Phase

Detector

Mode

Select

MCLKo MCLKi

Loop Filter

DCO

FSEL1

Divider

FSEL2

Figure 1 - Functional Block Diagram

Interface Circuit

C3 C1.5 C16 C8 C4 C2 F0o FP8-STB FP8-GCI

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MT9041 Advance Information

VSS

IC0

PRI

RST

FSEL2

FSEL1

432

VDD

MCLKo

MCLKi

FP8-GCI

F0o

FP8-STB

C1.5 IC0

5 6 7 8

9 10 11

12 13 14 15 16 17 18

VSS

262728 25

IC0

IC1

C16

VDD

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

2,3 IC0 Internal Conne ction 0. Connect to V

4PRIPrimary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048

5V 6MCLKoMaster Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz

Negative Power Supply Voltage. Nominally 0 Volts.

SS.

MHz as controlled by the input frequency selection pins) is used as the primary reference source for PLL synchronization.

Positive Supply Voltage. Nominally +5 volts.

crystal.

7MCLKiMaster Clock Osc illato r Input. This is a CMOS input for a 20 MHz crystal or crystal

oscillator. Signals should be DC coupled to this pin.

8 FP8-GCI Frame Pulse Outpu t (CMOS com p atib le). This is an 8 kHz output framing pulse th at

indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock.

9F0o

Frame Pulse Outpu t (CMOS com p atib le). This is an 8 kHz output framing pulse th at indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096 MHz synchronization clock. This is an active low signal.

10 FP8-STB Frame Pulse Outpu t (CMOS com p atib le). This is an 8 kHz output framing pulse th at

indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock.

11 C1.5 Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked

to the reference input signal.

12 C3

Clock 3.088 MH z (CMOS compa tibl e). This output is a 3.088 MHz output clock locked to the reference input signal.

13 C2 Clock 2.048 MHz (CM OS compa tible). This output is a 2. 048 MHz (E1) output clock

locked to the reference input signal.

14 C4

Clock 4.096 MH z (CMOS com pa tible ). This output is a 4.096 MHz output clock locked to the reference input signal.

15 V

Negative Power Supply Voltage. Nominally 0 Volts.

16 C8 Clock 8.192 MHz (CMOS compati ble). This output is an 8.192 MHz output clock locked to

the reference input signal.

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Advance Information MT9041

Pin Description (continued)

Pin # Name Description

17 C16 Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked

to the reference input signal.

18 V

19 IC 0 Internal Conn ectio n 0. Connect to V

Positive Supply Voltage. Nominally +5 volts.

SS.

20 IC 1 Intern al Connectio n 1. Leave open circuit.

21, 22 IC0 Internal Conn ectio n 0. Connect to V

SS.

23 MS Mode Sel ect Input (TTL compa tib le). This input selects the PLL mode of operation (i.e. ,

NORMAL or FRE ERUN, see Table 1).

24, 25 IC0 Internal Conn ectio n 0. Connect to V

SS.

26 FSEL2 Frequenc y Select - 2 Input (TTL comp ati bl e). This input, in conjunction with FSEL1,

selects the frequency of the input refere nce source (i.e., 8 kHz, 1.544 MH z, or 2.048 MHz; see Table 3).

27 FSEL1 Frequenc y Select - 1 Input (TTL comp ati bl e). This input, in conjunction with FSEL2,

selects the frequency of the input refere nce source (i.e., 8 kHz, 1.544 MH z, or 2.048 MHz; see Table 3).

28 RST

Reset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. To guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply . In normal operation, the RST

pin must be held low for a minimum of 60 nsec to reset the

device.

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MT9041 Advance Information

Functional Description

The MT9041 is a fully digital, phase-locked loop designed to provide timing references to interface circuits for T1 and E1 Primary Rate Digital Transmission links. As shown in Figure 1, the PLL employs a high resolution Digitally Controlled Oscillator (DCO) to generate the T1 and E1 outputs.

The interface circuit on the output of the DCO generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048 MHz (C2), 4.096 MHz (C4 MHz (C16), and three 8 kHz frame pulses F0o

), 8.192 MHz (C8), 16.384

, FP8-

STB, and FP8-GCI.

Phase

Detector

ref

Loop

Filter

Divider

DCO

sync

Figur e 3 - PL L Blo ck Diag ra m

As shown in Figure 3, the PLL of the MT9041 consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency (n x f

) to one of three possible reference

ref

frequencies, configured using pins FSEL1 and FSEL2. The PLL is capable of providing a full range of E1/T1 clock signals synchronized to the primary PRI input. The loop filter is a first order lowpass structure that provides approximately a 2 Hz bandwidth.

Modes of Operat ion

The MT9041 can operate in one of two modes, NORMAL or FREERUN, as controlled by mode select pin MS (see Table 1).

is controlled by the logic levels of FSEL1 and FSEL2, as shown in Table 2. This variety of input frequencies was chosen to allow the generation of all the necessary T1 and E1 clocks from either a T1, E1 or frame pulse reference source.

FSEL2FSEL

Input Reference

Frequency

00 Reserved 01 8 kHz 1 0 1.544 MHz 1 1 2.048 MHz

Table 2 - Input Frequen cy Se lecti on of the MT9 041

PLL Measures of Perfor mance

To meet the requirements of AT & T TR62411 and ETSI 300 011, the following PLL performance parameters were measured:

• locking range an d loc k time

• free-run accu racy

• intrinsic jitter

• jitter transfer function

• output jitt er spec tru m

• wander

Locking Range and Lock Time

The locking range of the PLL is the range that the input reference frequency can be deviated from its nominal frequency while the output signals maint ain synchronization. The relevant value is usually specified in parts-per-million (ppm). For bot h the T1 and E1 outputs, lock was maintained while an 8 kHz input was varied between 7900 Hz to 8100 Hz (corresponding to ±12500 ppm). This is well beyond the required ±100 ppm. The lock range of 12500 ppm also applies to 1.544 MHz and 2.048 MHz reference inputs.

MS Description of Operation

0NORMAL 1FREERUN

Table 1- Operating Mo des of the M T9041

Normal Mode

. There are three possible input frequencies for

selection as the primary reference clock. These are 8 kHz, 1.544 MHz or 2.048 MHz. Frequency selection

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The lock time is a measure of how long it takes the PLL to reach steady state frequency after a frequency step on the reference input signal. The locking time is measured by applying an 8000 Hz signal to the primary reference and an 8000.8 Hz (+100 ppm) to the secondary reference. The output is monitored with a tim e inter v al ana lyze r durin g slow periodic rearrangements on the reference inputs.

The lock time for both the T1 and E1 outputs is approximately 311 ms, which is well below the required lock time of 1.0 seconds.

Advance Information MT9041

Freerun Accuracy

The Freerun accuracy of the PLL is a measure of how accurately the PLL can reproduce the desired output frequency. The freerun accuracy is a function of master clock frequency which must be 20 MHz ±32 ppm in order to meet AT & T TR62411 and ETSI specifications.

Jitter Performa nce

The output jitter of a digital trunk PLL is composed of intrinsic jitter, measured using a jitter free reference clock, and frequency dependent jitter, measured by applying known levels of jitter on the references clock. The jitter spectrum indicates the frequency content of the output jitter.

Intrinsic Jitte r

Intrinsic jitter is the jitter added to an output signal by the processing device, in this case the enhanced PLL. Tables 3 and 4 show the average measured intrinsic jitter of the T1 and E1 outputs. Each measurement is an average based upon a ±100 ppm deviation (in steps of 20 ppm) on the input reference clock. Jitter on the master clock will increase intrinsic jitter of the device, hence at tention to minimization of master clock jitter is required.

Jitter Transfer Function

The jitter transfer function is a measure of the transfer characteristics of the PLL to frequency specific jitt er on the refere nced input o f th e PL L. It is directly linked to the loop bandwidth and the magnitude of the phase error suppression characteristics of the P LL. It is measured by applying jitter of specific magnitude and frequencies to the input of the PLL, then measuring the magnitude of the output jitter (both filtered and unfiltered) on the T1 or E1 output.

Care must be taken when measuring the transfer characteristics to ensure that critical jitter alias frequencies are included in the measurement (i.e., for digital phase locked loops using an 8 kHz input).

Tables 5 and 6 provide measured results for the jitter transfer characteristics of the PLL for both a 1.544 MHz and 2.048 MHz reference input clock. The transfer characteristics for an 8 kHz reference input will be the same.

Figures 4 and 5 show the jitter attenuation performance of the T1 and E1 outputs plotted against AT & T TR62411 and ETSI requirements, respectively.

Output Jitter in UIp-p

Reference Input FLT 0 Unfil tered

8 kHz .011 .004 .006 .002

1.544 MHz .011 .001 .002 .001

2.048 MHz .011 .001 .002 .001

Table 3 -Typical Intri nsi c Jitter for the T1 Outpu t

Typical f igures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Output Jitter in UIp-p

Reference Input FLT0 Unfiltered

8 kHz .011 .002 .002

1.544 MHz .011 .002 .002

2.048 MHz .011 .002 .002

Table 4 - Typical Intr insic Ji tter for the E1 Outpu t

Typical f igures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

FLT1

10Hz - 8kHz

FLT1

20Hz - 100kHz

FLT2

10Hz - 40kHz

8kHz - 40kHz

700Hz - 100kHz

FLT3

FLT2

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