MITEL MT90220AL Datasheet

MT90220

Octal IMA/UNI PHY Device

Features

• Cost effective, single chip, 8-port ATM IMA and UNI processor

• Up to 4 IMA groups over 8 T1/E1 links can be implemented

• Supports MIXED mode; links not assigned to an IMA group can be used in UNI mode

• Versatile PCM Interface to most popular T1 or E1 framers, reducing development time

• Supports Symmetrical and Asymmetr ical Operation

• Supports both Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) clocking modes

• Supports T1 ISDN lines

• Provides UTOPIA Level 2 MPHY Interface (MT90220 device slaved to ATM device)

• Complies with ITU G.804 recommendations for performing cell mapping into T1 and E1 transmission systems

• Provides ATM framing using cell delineation according to the ITU I.432 cell delineation process

DS5036 ISSUE 4 December 1999

Ordering Information

MT90220AL 208 Pin MQFP

-40°C to +85°C

• Provides Header Error Control (HEC) veriﬁcation and generation, error detection, Filler cell ﬁltering (IMA mode) and Idle/ Unassigned cell ﬁltering (UNI mode)

• Provides statistics to support MIB

• Connects to popular asychronous SRAM

• Provides statistics on the number of HEC errors

• 8 bit Microprocessor Interface, compatible with Intel and Motorola

• 3.3V operation / 5V tolerant inputs

• MQFP-208 pin

• JTAG Test support

Utopia

Level 2

BUS

Utopia

I/F CTRL

Utopia FiFo

Processor I/F

RX External Static RAM

8 x CD Circuit

8 x TC Circuit

4 Internal

IMA

Processors

Cell

Delineator

Transmission Convergence

2.048 or

T1/E1

Framers

P/S

8 Serial PCM Ports

T1/E1

Framers

T1/E1

Framers

1.544 Mb/s

Figure 1 - MT90220 Block Diagram with Built-in IMA functions for 4 IMA Groups over up to 8 links

MT90220

Applications

• Cost effective single chip solution to implement IMA and UNI links over T1 or E1 in all public or private UNI, NNI and B-ICI applications

• ATM Edge switch IMA and UNI Line Card Design

• Can be used for cost reduction in current applications based on FPGA implementation

Description

The MT90220 device is targeted to systems implementing the ATM FORUM UNI speciﬁcations for T1/E1 rates or Inverse Multiplexing for ATM (IMA). In the MT90220 architecture, up to 8 physical and independent T1/E1 streams can be terminated through the utilization of off-the-shelf, traditional T1/ E1 framers and LIUs. This allows ATM designers to leverage previous T1/E1 design experience, hardware and software implementation, and to select the best T1/E1 framer for the required application.

The MT90220 device provides ATM system designers with a ﬂexible architecture when implementing ATM access over existing and deployed trunk interfaces, allowing a migration towards ATM service technology. In addition to allowing for the design of ATM UNI speciﬁcations for T1/E1 rates, the MT90220 device is compliant with the ATM FORUM IMA speciﬁcations for controlling IMA groups of up to 8 trunks in a single chip. The MT90220 can be conﬁgured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Ofﬁce sites. For systems targeting ATM over T1/E1 with IMA and UNI operating simultaneously, the MT90220 device provides the ideal architecture and capabilities.

The device provides up to 4 internal IMA circuits and allows for bandwidth scaleability through the use of the UTOPIA MPHY, Level 2 speciﬁcation at 25Mhz.

Hardware functions that are implemented in the MT90220 device are:

• Utopia Level 2 PHY Interface

• Incoming HEC veriﬁcation and correction (optional),

• Generation of a new HEC byte

• Format outgoing bytes into multi-vendor PCM formats

• Retrieve ATM Cells from the incoming multivendor PCM format

• Perform cell delineation

• Provide various counters to assist in performance monitoring

Hardware functions that are implemented by the IMA processor in the MT90220 device are:

• Transmit scheduler (one per IMA group)

• Generation of the TX IMA Data Cell Rate

• Generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode and Idle Cells in UNI (non-IMA) mode; the ICP cells are programmed by the user and the Filler and Idle cells are pre-deﬁned

• Retrieve and process ICP cells in IMA Mode

• Perform IMA Frame synchronization

• Management of RX links to be part of the internal re-sequencer when active

• Extraction of RX IMA Data Cell Rate

• Veriﬁcation of delays between links

• Perform re-sequencing of ATM cells using external asynchronous Static RAM

• Can accommodate more than 400 msec of link differential delay depending on the amount of external memory

• Provide structured Interrupt scheme to report various events.

The implementation of the IMA as per AF-PHY-

0086.001 Inverse Multiplexing for ATM (IMA) Speciﬁcation Version 1.1 is divided into hardware and software functions. Hardware functions are implemented in the MT90220 device and software functions are implemented by the user. Additional hardware functions are included to assist in the collection of statistical information to support MIB implementation.

MT90220

Table of Contents

1.0 Device Architecture ....................................................................................................................................... 8

1.1 Software Functions..................................................................................................................................... 8

1.1.1 Link State Machines........................................................................................................................... 8

1.1.2 IMA Group State Machines................................................................................................................ 8

1.1.3 Link Addition, Removal or Restoration............................................................................................... 8

1.1.4 Interrupt.............................................................................................................................................. 8

1.1.5 Signaling and Rate Adjustment.......................................................................................................... 8

1.1.6 Performance Monitoring..................................................................................................................... 8

1.2 Hardware Functions ................................................................................................................................... 9

2.0 The ATM Transmit Path................................................................................................................................. 9

2.1 Cell_In_Control........................................................................................................................................... 9

2.2 The ATM Transmission Convergence...................................................................................................... 10

2.2.1 TX Cell Ram and TX FIFO Length................................................................................................... 10

2.3 Parallel to Serial PCM Interface ............................................................................................................... 11

2.4 ATM Transmit Path in IMA Mode ............................................................................................................. 11

2.4.1 IMA Frame Length (M)..................................................................................................................... 11

2.4.2 Position of the ICP Cell in the IMA Frame........................................................................................ 11

2.4.3 Transmit Clock Operation ................................................................................................................ 11

2.4.4 Stuff Cell Rate.................................................................................................................................. 12

2.4.5 IMA Data Cell Rate .......................................................................................................................... 12

2.4.6 IMA Controller (RoundRobin Scheduler).......................................................................................... 12

2.4.7 ICP Cell Generator........................................................................................................................... 12

2.4.8 IMA Frame Programmable Interrupt ................................................................................................ 14

2.4.9 Filler Cell Definition.......................................................................................................................... 14

2.4.10 TX IMA Group Start-Up.................................................................................................................... 14

2.4.11 TX Link Addition............................................................................................................................... 14

2.4.12 TX Link Deletion............................................................................................................................... 14

2.5 ATM Transmit Path in UNI Mode ............................................................................................................. 15

3.0 The ATM Receive Path................................................................................................................................. 15

3.1 Cell Delineation Function ......................................................................................................................... 15

3.2 De-Scrambling and ATM Cell Filtering..................................................................................................... 16

3.3 ATM Receive Path in IMA Mode .............................................................................................................. 16

3.3.1 ICP Cell Processor........................................................................................................................... 17

3.3.1.1 IMA Frame Synchronization...................................................................................................... 17

3.3.1.2 Link Information......................................................................................................................... 18

3.3.1.3 RX OAM Label.......................................................................................................................... 18

3.3.2 Out of IMA Frame (OIF) Condition................................................................................................... 18

3.3.3 Link Out Of IMA Frame (LIF) Synchronization................................................................................. 18

3.3.4 Filler Cell Handling........................................................................................................................... 18

3.3.5 Stuff Cell Handling ........................................................................................................................... 18

3.3.6 Received ICP Cell Buffer ..................................................................................................................18

MT90220

Table of Contents

3.3.7 Rate Recovery ................................................................................................................................. 19

3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19

3.3.9 Cell Sequence Recovery ................................................................................................................. 19

3.3.10 Delay Between Links ....................................................................................................................... 20

3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20

3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20

3.3.10.3 Link Out of Delay Synchronization (LODS)............................................................................... 20

3.3.10.4 Negative Delay Values.............................................................................................................. 21

3.3.10.5 Measured Delay Between Links................................................................................................ 21

3.3.10.6 Incrementing/Decrementing the Recombiner Delay ................................................................. 21

3.3.11 RX IMA Group Start-Up ...................................................................................................................21

3.3.12 Link Addition .................................................................................................................................... 22

3.3.13 Link Deletion.................................................................................................................................... 22

3.3.14 Disabling an IMA Group................................................................................................................... 22

3.4 The ATM Receive Path in UNI................................................................................................................. 22

4.0 Description of the PCM Interface................................................................................................................ 23

4.1 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters................................................................ 23

4.2 PCM System Interface Modes.................................................................................................................. 24

4.2.1 Mode 2 and 6: ST-BUS Interface for T1 .......................................................................................... 25

4.2.1.1 Detailed ST-BUS Spaced Mapping (3 of Every 4 Channels).................................................... 26

4.2.1.2 Detailed ST-BUS Grouped Mapping (24 Consecutive Channels)............................................. 26

4.2.1.3 Detailed ST-BUS ISDN Mapping (T1 ISDN Modes) ................................................................. 26

4.2.2 Mode 4 and 8: ST-BUS lnterface for E1 .......................................................................................... 26

4.2.3 Mode 1 and 5: Generic PCM Interface for T1.................................................................................. 26

4.2.3.1 1.544 MHz Clock....................................................................................................................... 27

4.2.3.2 2.048 MHz Clock....................................................................................................................... 27

4.2.4 Mode 3 and 7: Generic PCM Interface for E1.................................................................................. 27

4.2.5 TXSYNC Signal in Mode 5 and 7..................................................................................................... 28

4.3 Clocking Options...................................................................................................................................... 28

4.3.1 Verification of the RXSYNC Period.................................................................................................. 28

4.3.2 Verification of the TXSYNC Period .................................................................................................. 28

4.3.3 Primary and Secondary Reference Signals..................................................................................... 28

4.3.4 Verification of Clock Activity............................................................................................................. 30

4.3.5 Clock Selection ................................................................................................................................ 30

5.0 UTOPIA Interface Operation........................................................................................................................ 30

5.1 ATM Input Port......................................................................................................................................... 30

5.2 ATM Output Port ...................................................................................................................................... 31

5.3 UTOPIA Operation With a Single PHY..................................................................................................... 31

5.4 UTOPIA Operation with Multiple PHY...................................................................................................... 31

5.5 UTOPIA Operation in UNI Mode.............................................................................................................. 31

5.6 UTOPIA Operation in IMA Mode.............................................................................................................. 32

5.7 Examples of UTOPIA Operation Modes................................................................................................... 32

MT90220

Table of Contents

6.0 Support Blocks............................................................................................................................................. 33

6.1 Counter Block........................................................................................................................................... 33

6.1.1 UTOPIA Input I/F counters............................................................................................................... 33

6.1.2 Transmit PCM I/F Counters ............................................................................................................. 33

6.1.3 Receive PCM I/F Counters .............................................................................................................. 33

6.1.4 Access to the Counters.................................................................................................................... 33

6.2 Interrupt Block.......................................................................................................................................... 34

6.2.1 IRQ Master Status and IRQ Master Enable Registers..................................................................... 34

6.2.2 IRQ Link Status and IRQ Link Enable Registers.............................................................................. 35

6.2.2.1 Bit 7 and 6 of IRQ Link 0 Status and IRQ Link 0 Enable Registers .......................................... 35

6.2.3 IRQ Link UNI Overflow and IRQ UTOPIA Input UNI Overflow Status Registers............................. 36

6.2.4 IRQ IMA Group Overflow Status and Enable Registers................................................................... 36

6.2.5 IRQ IMA Overflow Status and RX UTOPIA IMA Group FIFO Overflow Enable Registers .............. 36

6.3 Register and Memory Map....................................................................................................................... 36

6.3.1 Access to the Various Registers...................................................................................................... 36

6.3.2 Direct Access................................................................................................................................... 37

6.3.3 Indirect Access................................................................................................................................. 37

6.3.4 Clearing of Status Bits...................................................................................................................... 37

6.3.4.1 Toggle Bit.................................................................................................................................. 37

6.3.5 Test Modes ...................................................................................................................................... 37

7.0 Register Descriptions.................................................................................................................................. 38

7.1 Utopia Register Description...................................................................................................................... 41

7.2 TX Registers Description.......................................................................................................................... 45

7.3 TX ICP Register Description .................................................................................................................... 50

7.4 RX Registers Description ......................................................................................................................... 52

7.5 RX ICP Cell Registers Description........................................................................................................... 57

7.6 External SRAM Register Description ....................................................................................................... 60

7.7 RX Delay Registers Description............................................................................................................... 62

7.8 RX Recombiner Registers Description..................................................................................................... 65

7.9 TX/RX and PLL Control Registers Description......................................................................................... 67

7.10 Counter Registers Description ................................................................................................................ 73

7.11Interrupt Registers Description................................................................................................................. 75

7.12 Miscellaneous Registers Description ...................................................................................................... 78

8.0 Application Notes......................................................................................................................................... 79

8.1 Connecting the MT90220 to Various T1/E1 Framers............................................................................... 79

9.0 AC/DC Characteristics................................................................................................................................. 85

iii

MT90220

Table of Contents

Packaging Information......................................................................................................................................100

List of Changes..................................................................................................................................................102

List of Abbreviations and Acronyms...............................................................................................................104

ATM Glossary ....................................................................................................................................................104

MT90220

List of Figures

Figure 2 - Pin Connections..................................................................................................................................... 3

Figure 3 - Functional Block Diagram -Transmitter in IMA Mode........................................................................... 10

Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode...................................................................14

Figure 5 - Cell Delineation State Diagram............................................................................................................ 15

Figure 6 - SYNC State Block Diagram ................................................................................................................. 15

Figure 7 - The MT90220 Receiver Circuit in IMA Mode....................................................................................... 17

Figure 8 - Example of UNI Mode Operation......................................................................................................... 23

Figure 9 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Spaced Mapping)....................................................... 25

Figure 10 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Grouped Mapping) ................................................... 26

Figure 11 - PCM Mode 4 and 8: ST-BUS Interface for E1 ................................................................................... 27

Figure 12 - Mode 1 and 5: Generic PCM Interface for T1.................................................................................... 28

Figure 13 - Mode 3 and 7: Generic PCM Interface for E1.................................................................................... 29

Figure 14 - TXCK and TXSYNC Output Pin Source Options............................................................................... 29

Figure 15 - ATM Interface to MT90220 ................................................................................................................ 32

Figure 16 - ATM Interface to Multiple MT90220s................................................................................................. 32

Figure 17 - ATM Mixed-Mode Interface to One MT90220.................................................................................... 33

Figure 18 - IRQ Register Hierarchy...................................................................................................................... 34

Figure 19 - PCM MODE 2 AND 4: Synchronous ST-BUS Mode.......................................................................... 80

Figure 20 - PCM MODE 2 and 4 CTC Mode.........................................................................................................81

Figure 21 - PCM MODE 2 AND 4: ITC Mode....................................................................................................... 82

Figure 22 - PCM MODE 1 and 3: Generic PCM System Interface........................................................................83

Figure 23 - PCM MODE 5 and 7: Asynchronous Operations................................................................................84

Figure 24 - ST-BUS Functional Timing Diagram.................................................................................................. 86

Figure 25 - ST-BUS Timing Diagram.................................................................................................................... 87

Figure 26 - Generic PCM Interface Timing Diagram.............................................................................................88

Figure 27 - Detailed Generic PCM Interface Timing Diagram.............................................................................. 89

Figure 28 - Setup and Hold Time Definition ......................................................................................................... 91

Figure 29 - Tri-State Timing.................................................................................................................................. 91

Figure 30 - External Memory Interface Timing - Read Cycle ............................................................................... 92

Figure 31 - External Memory Interface Timing - Write Cycle................................................................................ 93

Figure 32 - CPU Interface Timing - Read Access ................................................................................................ 95

Figure 33 - CPU Interface Motorola Timing - Write Access.................................................................................. 96

Figure 34 - CPU Interface Intel Timing - Write Access......................................................................................... 97

Figure 35 - JTAG Port Timing............................................................................................................................... 98

Figure 36 - System Clock and Reset.................................................................................................................... 99

Figure 37 - Metric Quad Flat Package - 208 Pin................................................................................................ 100

MT90220

List of Tables

Pin Description ....................................................................................................................................................... 4

Pinout Summary..................................................................................................................................................... 7

Table 1 - IDCR Integration Register Value........................................................................................................... 12

Table 2 - ICP Cell Description.............................................................................................................................. 13

Table 3 - Cell Acquisition Time............................................................................................................................. 16

Table 4 - Differential Delay for Various Memory Configuration............................................................................ 19

Table 5 - Conversion Factors Time/Cell (msec)................................................................................................... 20

Table 6 - PCM Modes........................................................................................................................................... 24

Table 7 - PCM Clock and Mapping Options......................................................................................................... 24

Table 8 - T1Channel Mapping Using 3 Channels Every 4 Channels................................................................... 25

Table 9 - T1 Channel Mapping Using 24 Consecutive Channels......................................................................... 26

Table 10 - Channel Mapping from ST-BUS to E1 ................................................................................................ 26

Table 11 - Register Summary............................................................................................................................... 38

Table 12 - UTOPIA Input Link Address Registers................................................................................................ 41

Table 13 - UTOPIA Input Group Address Registers............................................................................................. 41

Table 14 - UTOPIA Input Link PHY Enable Register ........................................................................................... 41

Table 15 - UTOPIA Input Group PHY Enable Register........................................................................................ 42

Table 16 - Utopia Input Control Register.............................................................................................................. 42

Table 17 - UTOPIA Output Link Address Registers............................................................................................. 42

Table 18 - UTOPIA Output Group Address Registers......................................................................................... 43

Table 19 - UTOPIA Output Link PHY Enable Register......................................................................................... 43

Table 20 - UTOPIA Output Group PHY Enable Register..................................................................................... 43

Table 21 - RX UTOPIA IMA Group FIFO Overflow Enable Register.................................................................... 44

Table 22 - RX UTOPIA Link FIFO Overflow Enable Register .............................................................................. 44

Table 23 - TX Cell RAM Control Register............................................................................................................ 45

Table 24 - TX UTOPIA FIFO Level Register........................................................................................................ 45

Table 25 - TX FIFO Length Definition Register 1................................................................................................. 45

Table 26 - TX FIFO Length Definition Register 2................................................................................................ 45

Table 27 - TX FIFO Length Definition Register 3................................................................................................. 46

Table 28 - TX FIFO Length Definition Register 4................................................................................................ 46

Table 29 - TX FIFO Length Definition Register 5................................................................................................ 46

Table 30 - TX FIFO Length Definition Register 6................................................................................................. 46

Table 31 - TX Group Control Mode Registers..................................................................................................... 47

Table 32 - TX Link ID Registers .......................................................................................................................... 47

Table 33 - TX ICP Cell Offset Registers.............................................................................................................. 47

Table 34 - TX IDCR Integration Registers............................................................................................................ 48

Table 35 - TX Link Control Registers ................................................................................................................... 48

Table 36 - TX IMA Control Registers................................................................................................................... 49

Table 37 - TX IMA Mode Status Register............................................................................................................ 49

Table 38 - TX ICP Cell Handler Register.............................................................................................................. 50

Table 39 - TX ICP Cell Interrupt Enable Register................................................................................................ 50

Table 40 - TX ICP Cell Registers ........................................................................................................................ 51

Table 41 - RX Link Control Registers.................................................................................................................. 52

Table 42 - Cell Delineation Register.................................................................................................................... 52

Table 43 - Loss of Delineation Register ............................................................................................................... 52

Table 44 - IMA Frame Delineation Register........................................................................................................ 53

Table 45 - RX OAM Label Register..................................................................................................................... 53

MT90220

List of Tables

Table 46 - RX OIF Status Register...................................................................................................................... 53

Table 47 - RX OIF Counter Clear Command Register........................................................................................ 54

Table 48 - RX Load Values/Link Select Register ................................................................................................ 54

Table 49 - RX Link IMA ID Registers................................................................................................................... 54

Table 50 - RX ICP Cell Offset Register............................................................................................................... 55

Table 51 - RX Link Frame Sequence Number Register...................................................................................... 55

Table 52 - RX Link SCCI Sequence Number Register........................................................................................ 55

Table 53 - RX Link OIF Counter Value Register ................................................................................................. 55

Table 54 - RX Link ID Number Register...............................................................................................................56

Table 55 - RX State Register............................................................................................................................... 56

Table 56 - RX ICP Cell Type RAM Register 1...................................................................................................... 57

Table 57 - ICP Cell Type RAM Register 2........................................................................................................... 58

Table 58 - RX ICP Cell Buffer Increment Read Pointer Register........................................................................ 58

Table 59 - RX ICP Cell Level FIFO Status Register............................................................................................. 59

Table 60 - Test Mode Enable Register................................................................................................................. 59

Table 61 - SRAM Control Register...................................................................................................................... 60

Table 62 - RX External SRAM Read/Write Data................................................................................................. 60

Table 63 - RX External SRAM Read/Write Address 0.......................................................................................... 60

Table 64 - RX External SRAM Read/Write Address 1......................................................................................... 60

Table 65 - RX External SRAM Read/Write Address 2......................................................................................... 60

Table 66 - RX External SRAM Control Register.................................................................................................. 62

Table 67 - Increment/Decrement Delay Control Register.................................................................................... 62

Table 68 - RX Delay Select Register................................................................................................................... 63

Table 69 - RX Delay MSB Register..................................................................................................................... 63

Table 70 - RX Delay LSB Register...................................................................................................................... 63

Table 71 - RX Delay Link Number Register ........................................................................................................ 63

Table 72 - RX Guardband/Delta Delay LSB Register........................................................................................... 64

Table 73 - RX Guardband/Delta Delay MSB Register.......................................................................................... 64

Table 74 - RX Maximum Operational Delay LSB Register................................................................................... 64

Table 75 - RX Maximum Operational Delay MSB Register.................................................................................. 64

Table 76 - RX Recombiner Registers.................................................................................................................. 65

Table 77 - RX Recombiner Delay Control Registers........................................................................................... 65

Table 78 - Enable Recombination Status............................................................................................................ 66

Table 79 - RX Reference Link Control Registers ................................................................................................ 66

Table 80 - RX IDCR Integration Registers .......................................................................................................... 66

Table 81 - TX PCM Link Control Register Number 2 ........................................................................................... 67

Table 82 - TX PCM Link Control Register Number 1 ........................................................................................... 68

Table 83 - RX PCM Link Control Register........................................................................................................... 69

Table 84 - PLL Reference Control Register ........................................................................................................ 70

Table 85 - Clock Activity Register........................................................................................................................ 71

Table 86 - RX Sync. Status Register................................................................................................................... 71

Table 87 - TX Sync. Status Register................................................................................................................... 72

Table 88 - TX Clock Disabled Status................................................................................................................... 72

Table 89 - PLL REF Clock Disabled Status/Device Rev..................................................................................... 72

Table 90 - Counter Byte Number 3 Register....................................................................................................... 73

Table 91 - Counter Byte Number 2 Register....................................................................................................... 73

Table 92 - Counter Byte Number 1 Register....................................................................................................... 73

vii

MT90220

List of Tables

Table 93 - Select Counter Register..................................................................................................................... 74

Table 94 - Counter Transfer Command Register................................................................................................. 74

Table 95 - IRQ Master Status Register ................................................................................................................ 75

Table 96 - IRQ Master Enable Register .............................................................................................................. 75

Table 97 - IRQ Link Status Registers.................................................................................................................. 75

Table 98 - IRQ Link Enable Registers................................................................................................................. 76

Table 99 - IRQ IMA Group Overflow Status Register.......................................................................................... 76

Table 100 - IRQ IMA Group Overflow Enable Register....................................................................................... 76

Table 101 - IRQ IMA Overflow Status Registers................................................................................................. 76

Table 102 - IRQ UTOPIA UNI Overflow Status Registers................................................................................... 77

Table 103 - IRQ Link UNI Overflow Status Registers.......................................................................................... 77

Table 104 - General Status Register................................................................................................................... 78

Table 105 - Test 1 Register................................................................................................................................. 78

Table 106 - Test 2 Register.................................................................................................................................. 78

Absolute Maximum Conditions .............................................................................................................................85

Recommended Operating Conditions ...................................................................................................................85

DC Electrical Characteristics.................................................................................................................................86

AC Electrical Characteristics - PCM PORT ST-BUS Interface Mode................................................................... 86

AC Electrical Characteristics - Generic PCM Interface Mode .............................................................................. 88

AC Electrical Characteristics - Utopia Interface Transmit Timing......................................................................... 90

AC Electrical Characteristics - Receive Timing.................................................................................................... 90

AC Electrical Characteristics - External Memory Interface Timing - Read Access............................................... 92

AC Electrical Characteristics - External Memory Interface Timing - Write Access............................................... 93

AC Electrical Characteristics - CPU Interface Timing - Read Cycle..................................................................... 95

AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle...................................................... 96

AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle............................................................. 97

AC Electrical Characteristics - JTAG Port and RESET Pin Timing...................................................................... 98

AC Electrical Characteristics - System Clock and Reset...................................................................................... 99

Metric Quad Flat Package Dimensions...............................................................................................................100

viii

MT90220

VSS REFCK_3 REFCK_2 REFCK_1 REFCK_0

SR_A_18 SR_A_17 SR_A_16 SR_A_15 SR_A_14

VDD

VSS

SR_A_13 SR_A_12 SR_A_11 SR_A_10

VDD

VSS

SR_A_9 SR_A_8 SR_A_7 SR_A_6 SR_A_5

VDD

VSS

SR_A_4 SR_A_3 SR_A_2 SR_A_1 SR_A_0

SR_WE SR_D_7 SR_D_6 SR_D_5 SR_D_4 SR_D_3

VDD

VSS SR_D_2 SR_D_1 SR_D_0

SR_CS_1 SR_CS_0

VSS

VDD

RXSOC

RXCLAV

VDD

RXDATA_7

RXDATA_6

RXDATA_5

VSS

158 160 162 164 166 168

170 172 174 176 178 180 182 184 186 188

190 192 194 196 198 200 202 204 206 208

VSS

PLLREF_0

PLLREF_1

TEST3

TEST4

DSTI_0

RXSYNCI_0

VDD

RXCKI_0

VSS

RXCKI_1

DSTI_1

RXSYNCI_1

DSTI_2

RXSYNCI_2

VSS

RXCKI_2

VDD

RXCKI_3

2018161412108642

VSS

DSTI_3

RXSYNCI_3

22 24 26

VDD

RXCKI_5

RXSYNCI_4

VSS

DSTI_4

132134136138140142144146148150152154156

VDD

RXCKI_4

130 128 126 124 122 120 118 116 114 112 110 108 106

DSTI_5

RXSYNCI_5

RXSYNCI_6

VSS

DSTI_6

VDD

RXCKI_6

RXCKI_7

VSS

DSTI_7

VDD

RXSYNCI_7

DSTO_0

TXSYNCIO_0

208 PIN MQFP

323028

34 36 38 40 42 44 46 48 50 52

VSS

TXCKIO_0

TXCKIO_1

VDD

DSTO_1

TXSYNCIO_1

VSS

DSTO_2

TXSYNCIO_2

104 102 100

98 96 94

92 90 88 86 84 82 80 78 76 74

72 70 68 66 64 62 60 58 56 54

VSS TXCKIO_2 VDD TXCKIO_3 VSS DSTO_3 TXSYNCIO_3 DSTO_4 TXSYNCIO_4 VSS TXCKIO_4 VDD TXCKIO_5 VSS DSTO_5 TXSYNCIO_5 DSTO_6 TXSYNCIO_6 VDD TXCKIO_6 VSS TXCKIO_7 VDD DSTO_7 TXSYNCIO_7 VSS VDD TEST2 TEST1 VDD CLK VSS TCK TMS TDI TRST TDO UP_IRQ VDD UP_A_0 UP_A_1 UP_A_2 UP_A_3 UP_A_4 UP_A_5 UP_A_6 UP_A_7 UP_A_8 UP_A_9 UP_A_10 RESET VSS

VSS

RXDATA_4

RXDATA_3

RXDATA_2

RXDATA_1

RXDATA_0

VDD

VSS

RXADDR_4

RXADDR_3

RXADDR_2

RXADDR_1

VDD

VSS

RXCLK

RXADDR_0

VSS

VDD

RXENB

TXSOC

TX_CLAV

TXDATA_7

TXDATA_6

TXDATA_5

TXDATA_4

TXDATA_3

TXENB

TXDATA_2

TXDATA_1

TXDATA_0

VDD

TXCLK

Figure 2 - Pin Connections

VSS

TXADDR_4

TXADDR_3

UP_CS

TXADDR_2

TXADDR_1

TXADDR_0

UP_OE

VSS

VDD

UP_RW

UP_D_7

UP_D_6

UP_D_4

UP_D_5

UP_D_3

UP_D_2

UP_D_1

UP_D_0

VSS

MT90220

Pin Description

Pin # Name I/O Description

ATM Input Port Signals (UTOPIA Transmit Interface)

22, 23, 24, 25, 26, 27,

28, 29

21 TxSOC I UTOPIA Transmit Start of Cell Signal. Active HIGH signal asserted by the ATM

32 TxClk I UTOPIA Transmit Clock. Transfer clock from the ATM Layer device to the

30 TxEnb I UTOPIA Transmit Data Enable. Active LOW signal asserted by the ATM LAYER

20 TxClav O UTOPIA Transmit Cell Available Indication Signal. For cell-le v el ﬂo w control in a

34, 35, 36,

37, 38

TxData

[7:0]

TxAddr

[4:0]

I UTOPIA Transmit Data Bus. Byte-wide data driven from ATM LAYER device to

MT90220. Bit 7 is the MSB. All arriving data between the last byte of the previous cell and the ﬁrst byte of the following cell (indicated by the SOC signal) is ignored.

LAYER device when TxData[7:0] contains the ﬁrst valid byte of the cell. After this signal is high, the following 52 b ytes should contain v alid data. The MT90220 waits for another TxSOC signal after reading a complete cell.

MT90220 which synchronizes data transfers on TxData[7:0]. This signal is the clock of the incoming data. Data is sampled on the rising edge of this signal.

device during cycles when TxData contains valid cell data.

MPHY environment, TxClav is an active high tri-stateab le signal from the MT90220 to the ATM LAYER device. A polled MT90220 drives TxClav only during each cycle following one with its address on the TxAddr lines. The polled MT90220 asserts TxClav high to indicate it can accept the transfer of a complete cell, otherwise it deasserts the signal.

I Transmit Address.Five bit wide true data driven from the ATM to the PHY layer to

poll and select the appropriate MT90220. TxAddr[4] is the MSB. Each MT90220 keeps its addresses. The value for the Tx and Rx portions of the MT90220 can be different

ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1)

205, 206, 207, 2, 3,

4, 5, 6

202 RxSOC O UTOPIA Receive Start of Cell Signal. Activ e high asserted by the MT90220 when

15 RxClk I UTOPIA Receive Byte Clock. This signal is the clock of the outgoing data. Data

17 RxEnb I UTOPIA Receive Data Enable. Active LOW signal asserted by the ATM layer

203 RxClav O UTOPIA Receive Cell Available Indication Signal. For cell-level ﬂow control in a

RxData

[7:0]

O UTOPIA Receive Data Bus. Byte-wide data driven from MT90220 to ATM layer

device. RxData[7] is the MSB. To support multiple PHY conﬁgurations, RxData is tri-stateable, enabled only in cycles following those with RxEnb asserted.

RxData contains the ﬁrst valid byte of a cell. To support multiple PHY conﬁgurations, RxSOC is tri-stateable, enabled only in cycles following those with RxEnb asserted.

changes after the rising edge of this signal. The RxClk needs to be synchronized with the system clock.

device to indicate that RxData[7:0] and RxSOC will be sampled at the end of the next cycle. In multiple PHY conﬁgurations, RxEnb* is used to tri-state RxData and RxSOC MT90220 outputs. In that case, RxData and RxSOC would be enabled only in cycles following those with RxEnb asserted.

MPHY environment, RxClav is an active high tri-stateab le signal from the MT90220 to ATM LAYER device. A polled MT90220 drives RxClav only during each cycle following one with its address on the TxAddr lines. The polled MT90220 asserts RxClav high to indicate it has a complete cell av ailable f or transf er to the ATM Lay er device, otherwise it de-asserts the signal.

Pin Description (continued)

Pin # Name I/O Description

MT90220

9, 10, 11,

12, 13

188, 189, 190, 191, 192, 195,

196,197

162, 163, 164, 165, 166, 169, 170, 171, 172, 175, 176, 177, 178, 179, 182, 183, 184, 185,

186 187 sr_weOStatic Memory Read/Not Write. If low, data is written from the MT90220 to the

198, 199 sr_cs_1, 0 O Static Memory Chip Control Signal.

RxAddr

[4:0]

sr_d [7:0]

sr_a

[18:0]

I Receive Address. Five bit wide true data driven from the ATM to PHY layer to

select the appropriate MT90220. RxAddr[4] is the MSB. Each MT90220 keeps its address. The value for the Tx and Rx portions of the MT90220 can be different.

Receiver Static Memory Interface Signals (see Note 1)

I/O Static Memory Data Bus. Data Bus to exchange data between the MT90220 and

the external static memory.

O Static Memory Address Bus. The signal is used to select an entry in the external

static memory.

memory. If high, data is read from the memory to the MT90220.

Processor Interface Signals (see Note 2)

44, 45, 46, 47, 48, 49,

50, 51

55, 56, 57, 58, 59, 60, 61, 62, 63,

64, 65

41 up_r/w

40 up_oe

39 up_cs I Processor Chip Select. This is an active low input signal. If this signal is high, the

up_d

[7:0]

up_a

[10:0]

up_wr

up_rd

I/O Processor Data Bus. Data Bus to exchange data between the MT90220 and a

local processor.

I Processor Address Bus. They are used to select the internal registers and

memory positions of the MT90220.

I Processor Read/Not Write. Motorola Mode. This is an input signal. If low, data is

written from the processor to the MT90220. If high, data is read from the MT90220 to the processor. Processor Not Write (Intel Mode). This is an input signal. If low, data is written from the processor to the MT90220. De-asserting this signal to high will terminate a write access cycle.

I Output enable Motorola Mode. This is an input signal. This signal should be tied

to GND for Motorola timing mode. Processor Not Read (Intel Mode). This is an input signal. If low, data is read from the MT90220.

MT90220 ignores all other signals on its processor bus. If this signal is low, the MT90220 accepts the signals on its processor bus. De-asserting this signal to high will terminate an access cycle.

67 up_irq O Processor Interrupt Request. If this signal is low, the MT90220 signals to the

processor that an interrupt condition is pending inside the MT90220. Otherwise no interrupt is pending inside the MT90220. Open drain signal.

PCM Interface Signals

MT90220

Pin Description (continued)

Pin # Name I/O Description

81,88, 90,

97,99,107,

109,116

118, 124, 127, 134, 136, 143,

145, 151

83, 85, 92,

94, 101,

103, 111,

113

80, 87, 89,

96, 98,

106, 108,

115

DSTo

[7:0]

DSTi

[7:0]

TXCKi/o

[7:0]

TXSYNCio

[7:0]

O Serial PCM Data Output 7-0. A 1.544 Mbit/s or 2.048 Mbps serial stream which

contain 24 (T1) or 32 (E1) PCM or data channels received on T1 or E1 line. The output is set to high impedance for unused channels and if the link is not used.

I Serial PCM Data Input 7-0. A 1.544 Mbit/s or 2.048 Mbps serial stream which

contains the 24 (T1) or 32 (E1) PCM or data channels on T1 or E1 line.

I/O PCM Interface Transmit Clock 7-0.This pin is an input for PCM Modes 2, 4, 5 and

7. It is an output for Interface Modes 1, 3, 6 and 8 (see Section 4.2, PCM System Interface Modes). It is the clock for serial PCM data transmission of the T1 and E1 framers . The TXCK source is software selectable and can be either one of the eight RXCK or one of the four REFCK signals. It is used f or internal transmit timing and should be connected to the Transmit Clock of the framer.

1. The TXCK is 4.096 MHz for ST-BUS applications.

2. For generic PCM Interfaces (non ST-BUS or asynchronous line termination), these outputs can be programmed to provide either a 1.544 MHz (T1) or 2.048 MHz (T1 or E1) clock.

I/O Transmit Line 8KHz Frame Pulse 7-0. This pin is an input for Interface Modes 2,

4, 5 and 7. It is an output for Interface Modes 1, 3, 6 and 8 (see PCM Section 4.2, PCM System Interface Modes). It is the 8 kHz reference used as transmit synchronization for the PCM system interface. When an output, the TXSYNC is generated from the TXCK signal and is independent from other TXSYNC signals. Two output modes can be programmed:

1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32 channel frame of the ST-BUS interface at DSTi and DSTo lines (see Figure 25 - ST-BUS Timing Diagram for this sync pulse). The frame pulse is typically received through the RXSYNC[0] pin.

2. For generic PCM Interfaces, it can be programmed to generate either a positive or negative pulse polarity that lines up with the ﬁrst bit of the PCM system interface.

117, 125, 126, 133, 135, 142,

144, 150

120, 122, 129, 131, 138, 140,

146, 148

154, 155 PLLREF

158, 159,

160, 161

RXSYNCi

[7:0]

RXCKi

[7:0]

[1:0]

REFCK

[3:0]

I Receive line 8KHz Frame Pulse 7-0. This signal represents the 8 KHz reference

received from the incoming T1 or E1 line. The MT90220 can be programmed to accept different 8 KHz pulse formats at this input.

1. For ST-BUS applications, it is a low going pulse (F0), which delimits the 32 channel frame of ST-BUS interface at DSTi and DSTo lines. See STBUS timing diagram for this sync pulse.

2. For generic PCM Interfaces, it can be programmed to accept either positive or negative pulse polarities.

I PCM Interface Receive Clock 7-0. This input line represents the clock for the

receive serial PCM data of the T1 and E1 framers. The T1 or E1 frequency value to be received at this input clock is deﬁned by the user through an internal register.

1. For ST-BUS applications, input pin RXCKi receives the 4.096 MHz signal.

2. For generic PCM Interfaces, these inputs can be prog r ammed to accept either a

1.544 MHz (T1) or 2.048 MHz (T1 or E1) clock.

O Output reference to an external PLL. See 4.3 Description of the PCM Interface

for details.

I Input reference clock inputs 3 to 0. Receive the de-jittered transmit clock

reference to be internally routed to the T1/E1 framer transmit clocks (output pins TXCK[7:0]. See “Description of the PCM Interface” on page 23. for more details.

System Signals

MT90220

Pin Description (continued)

Pin # Name I/O Description

74 Clk I System Clock (25 MHz nominal). In the MT90220, this clock is used for all

internal operations of the device.

76 Test1 I Test1. This signal should be high for normal operation. The signal should be pulled

up for normal operation.

54 Reset I System Reset. This is an active low input signal. It causes the device to enter the

initial state. The Clk signal must be active to reset the internal registers. 72 TCK I JTAG Test Clock. It should be pulled down if not used 71 TMS I JTAG Test Mode Select. TMS is sampled on the rising edge of TCK. TMS has an

internal pull- up resistor. 70 TDI I JTAG Test Data Input. 68 TDO O JTAG Test Data Output. Note: TDO is tristated by TMS pin. 69 TRST I TAG Test Reset (active low). Should be asserted LOW on power-up and during

reset. Must be HIGH for JTAG boundary-scan operation. Note: This pin has an

internal pull-down. 77 Test2 I Test2. It should be pulled down for normal operation.

153 Test3 I Test3. It should be pulled down for normal operation. 152 Test4 I Test4. It should be pulled up for normal operation. NOT 5V TOLERANT

Notes:

1. Static memory stores the received cells. RAM is used for reordering the cells

2. These signals are used to transfer data between the MT90220 and the local processor

Pinout Summary

Type Input Output I/O Power Ground

TX UTOPIA 16 1 RX UTOPIA 7 10

Microprocessor Interface 14 1 8

External Memory Interface 22 8

TX PCM Interface 8 16 RX PCM Interface 24

PLL Interface 4 2

Miscellaneous 10 1

Power 25

Ground 31

Total

208

75 45 32 25 31

MT90220

1.0 Device Architecture

The MT90220, supported by software, implements the ATM Forum Inverse Multiplexing for Asynchronous Transfer Mode (IMA) Speciﬁcation. This approach minimizes the impact of any changes that might occur in the speciﬁcation. Actions are implemented by the MT90220 and decisions by the software.

The MT90220 supports following two major modes of operation:

• the IMA mode (as deﬁned by the ATM Forum IMA Speciﬁcation)

• the User Network Interface (UNI) mode

Up to four IMA Groups can be implemented. Any of the eight PCM Interfaces can be assigned dynamically to any of these IMA Groups. A different UTOPIA PHY address is assigned to each of the IMA Groups.

The UNI mode is used to transfer the cells from the UTOPIA Interface to a PCM port without any overhead. Up to 8 UTOPIA PHY addresses can be supported in UNI mode.

The MT90220 also supports a mixed mode where the PCM Interfaces not assigned to an IMA Group can be used in UNI mode.

The IMA implementation is divided into hardware and software functions. The MT90220 implements the hardware functions. The software functions are implemented by the user. The hardware and software functions are described below. Notice that a number of MT90220 functions are included to assist in the collection of statistical information. This information supports the MIB implementation.

1.1 Software Functions

For the MT90220 to comply with the IMA speciﬁcation, the following functions must be implemented by software:

• the transmit and receive Link State Machines (LSM)

• the IMA Group State Machines (GSM)

• the IMA Group Trafﬁc State Machines (GTSM)

• the Operations and Maintenance (OAM) functions

1.1.1 Link State Machines

The software implemented transmit and receive LSMs are independent (i.e., each link has its own LSM). LSMs rely on various events from the

MT90220 interface, such as cell errors, excessive delay between-links, etc.; or, from the T1 or E1 framer, such as Loss Of Signal (LOS), Loss Of Frame (LOF), Remote Alarm Indication (RAI) etc.

On-chip registers are used to generate the ICP cells that communicate the LSM states to the Far End (FE).

1.1.2 IMA Group State Machines

The IMA GSMs and Group Trafﬁc State Machines (GTSM) must be implemented in software. One of each state machine should be implemented for each IMA Group.

On-chip registers are used to generate the ICP cells that communicate the various states to the FE.

1.1.3 Link Addition, Removal or Restoration

The addition, removal or restoration of a link is controlled by software using the various control registers in the MT90220 and in the T1 or E1 framers. Decisions are based on the MT90220 and T1 or E1 framers status registers.

1.1.4 Interrupt

The MT90220 provides numerous registers and counters to implement a polling and/or interrupt mechanism for tracking link and IMA Group status. This trafﬁc in and out information is used by the Management Information Base (MIB) for each IMA Group.

1.1.5 Signaling and Rate Adjustment

The microprocessor controls the operation of the T1 or E1 link by providing handshaking between the FE and Near Ends (NE) including such functions as signaling and loopback controls. Rate adjustment is controlled by:

• adding or removing one or more T1 or E1 links

• providing feedback to the ATM network for adjusting the ATM trafﬁc.

1.1.6 Performance Monitoring

Software implements most of the performance monitoring. The MT90220 provides status information for:

• the Cell Delineation Block and IMA Fr ame State

Machine

• the number of ICP violations

• the total number of cells

• the number of idle or discarded cells.

MT90220

It also provides the content for received ICP cells that contain some changes. The external T1 or E1 framers provide the low level status of the link. The software integrates and responds to the various events.

1.2 Hardware Functions

The MT90220 circuitry implements the following functions:

• UTOPIA L2 Interface

• veriﬁcation of the incoming HEC (optional)

• generation of a new HEC byte

• transmit scheduler

• generation of the TX IMA Data Cell Rate (IDCR)

• generation and insertion of ICP cells, Filler Cells and Stuff Cells in IMA mode

• generation of Idle Cells in UNI mode (from onchip copies of the cells)

• ﬂexible PCM formatting of the outgoing bytes

• retrieval of ATM Cells from the incoming PCM format

• cell delineation

• retrieval and processing of ICP cells

• synchronization of the IMA Frame

• management of the internal re-sequencer RX links (when active)

• extraction of the RX IDCR

• veriﬁcation of the delays between-links

• re-sequencing of ATM cells using external Static RAM

• various performance monitoring counters

• 8-bit microprocessor interface (adaptable to Intel or Motorola interfaces)

The MT90220 can be separated into four major independent blocks and three support blocks.

The four major independent blocks are:

• the ATM Transmit Path

• the ATM Receive Path

• the PCM Interface

• the UTOPIA Interface

The three support blocks are:

• the Counter Block

• the Interrupt Block

• the Microprocessor Interface Block

2.0 The ATM Transmit Path

The transmit path corresponds to a cell ﬂow from the ATM Layer towards the T1/E1 interface. The ATM cell path on the transmit side starts at the UTOPIA L2 Interface. Once ATM cells are received at the UTOPIA port, the device transfers these cells to the transmit block.

The MT90220 provides ATM cell mapping and transmission convergence blocks to transport ATM cell payloads over eight ﬂexible PCM Interface ports. It uses these PCM Interface ports to communicate with most off-the-shelf T1 or E1 framers.

Each of the eight T1/E1 links can be assigned to either an IMA Group or to a UNI link. A single T1/E1 link cannot be assigned to more than one IMA Group.

The functional block diagram at Figure 3 illustrates the transmit function of the MT90220.

2.1 Cell_In_Control

In general terms, the MT90220 transmit input port has the following properties:

• cell level handshaking complies with the ATM Forum UTOPIA L2 Speciﬁcation

• behaves like a UTOPIA MPHY Device

• each port can be enabled or disabled independently

• generates and optionally veriﬁes the HEC for incoming cells

• includes the ATM Forum polynomial when generating the HEC (default option that can be disabled)

• either passes or removes incoming Idle cells

• either passes or removes incoming Unassigned cells

• provides a counter per UTOPIA port for the total number of Idle and Unassigned cells (24 bits)

• provides a counter per UTOPIA port for the total number of cells with wrong incoming HEC (24 bits)

• provides a counter per UTOPIA port for the total number of cells handled (24 bits)

The input port can be enabled to remove (ﬁlter) Unassigned or Idle cells. If Unassigned or Idle Cell Filtering is enabled, the device checks for and discards Unassigned or Idle cells. This function is programmed in the UTOPIA Input Control register.

Section 5 describes the UTOPIA Interface in more detail.

MT90220

ATM In

UTOPIA L2 Interface

Cell_In_Control

from IDCR Generator

Transmitter

Cell RAM

FIFO Link 0

(see Note 1)

FIFO Link 1

(see Note 1)

FIFO Link 7

(see Note 1)

TX Utopia FIFO

Group 0

TX Utopia FIFO

Group 3 Filler Cell Idle Cell ICP Cell Group 1 ICP Cell Group 2 ICP Cell Group 3 ICP Cell Group 4

ICP Cell Buffer RAM

Next ICP Cell Group 1

ICP Cell Modifier and

Cell Scrambling

ICP Cell Modifier and

Cell Scrambling

ICP Cell Modifier and

Cell Scrambling

Round Robin Scheduler

and FIFO Selection

and Adaptive Shaper

(1 of 4)

to Cell_In_Control

ICP Cell Handler

P/S P/S

P/S

IDCR Generator

(1 of 4)

Transmitter

Reference

Link Timing

Serial

Streams

Link 0

Link 1

Link 7

Micro I/F

Next ICP Cell Group 2 Next ICP Cell Group 3 Next ICP Cell Group 4

Figure 3 - Functional Block Diagram -Transmitter in IMA Mode

2.2 The ATM Transmission Convergence

The Transmit Convergence (TC) function is common for both the IMA and UNI modes. It integrates the circuitry to support ATM cell payload scrambling, HEC generation and the generation of Idle/Filler/ICP cells for use with the T1 and/or E1 trunks. Each of the eight MT90220 ATM TC circuits can use the polynomial X43 + 1 to scramble the ATM cell payload ﬁeld. The MT90220 ATM cell payload scrambling function can be disabled.

The ITU I.432 polynomial X8 + X2 + X + 1 is used to generate the HEC ﬁeld of the ATM cell. By default, the ATM Forum polynomial X6 + X4 + X2 + 1 is added to the calculated HEC octet. The addition of the ATM Forum polynomial can be disabled.

The resulting calculation is then over-written on the HEC ﬁeld and the ATM cell is ready (i.e., complies

Note 1: This FIFO is the TX UTOPIA FIFO when the link is configured in UNI Mode and it is the TX LINK FIFO when it is configured in IMA Mode.

with the IMA transmit protocol) for transmission over the PCM Interface.

In cases where the TC block requests a cell to be transferred to any of the PCM Interfaces and the TX UTOPIA FIFO has no cell ready for transmission, then the TC block will automatically send an IDLE cell (in UNI) or a Filler cell (in IMA mode) to the line. The default values for the Idle and the Filler cells comply with the ATM IMA Speciﬁcation and are preloaded in the MT90220 following a reset. The TX Cell RAM Control register can be used to reinitialize the TX Cell RAM.

2.2.1 TX Cell Ram and TX FIFO Length

The internal TX Cell Ram can hold up to 64 cells. The following six cells are reserved for MT90220 operation:

• one ICP cell for each IMA Group for a total of four cells

MT90220

• one common Filler Cell used in IMA mode

• one Idle Cell used in UNI mode The remaining 58 cells can be assigned to any of the

20 TX FIFOs. The TX FIFOs are divided in 12 TX UTOPIA FIFOs and 8 TX Link FIFOs.The MT90220 implements one TX UTOPIA FIFO for each link when used in UNI and one for each IMA Group for a total of 12 TX UTOPIA FIFOs. Each TX UTOPIA FIFO is associated with one TX UTOPIA Address. Please refer to the paragraph 5.0 UTOPIA Interface Operation for more details.

In addition, for each link to be used in IMA mode, an internal TX Link FIFO is utilized. These TX Link FIFOs are holding the cell streams that are to be sent on each TX serial port. There is a total of 8 TX Link FIFOs and their size is programmed on a per group basis using the TX IMA Control register. When a link is used in UNI mode, its corresponding TX Link FIFO is disabled and the TX UTOPIA FIFO is used.

TX UTOPIA FIFO Length Deﬁnition registers are used to set the TX UTOPIA FIFO size . A maxim um of 15 cells can be assigned to any single FIFO. The size of unused TX UTOPIA FIFOs should be set to zero. The recommended size for the IMA Group TX UTOPIA FIFO is 1.

In IMA Mode, the ATM User Cells are ﬁrst placed in the IMA TX UTOPIA FIFO and then transferred, by the internal round robin scheduler, to the proper TX Link FIFO. The TX UTOPIA FIFO length for each link conﬁgured in IMA mode should be set to zero.

The TX IMA Control registers are used to set the size of the internal TX Link FIFO. An upper and lower level limit must be set for the internal TX Link FIFO.

In UNI Mode, the ATM User Cells are queued in the TX UTOPIA FIFO until sent over the T1/E1 link.

The recommended upper limit value for the internal TX Link FIFO is ﬁve and the recommended lower limit is one when operating in ITC clocking mode. When operating in CTC mode, the recommended upper limit value for the internal TX Link FIFO is six and the recommended lower limit is one. In the case where CTC mode is used and when the ICP cells on all the links are sent with the same ICP cell offset and when carrying a CBR-type trafﬁc, an upper value of 7 may be required.

2.3 Parallel to Serial PCM Interface

ATM cell octet byte alignment conforms to ITU G.804 recommendations for T1 or E1 framer parallel to serial format conversion.

The TX PCM Control and RX PCM Control registers are used to select the T1 or E1 mode of operation. Refer to Section 4, Description of the PCM Interface, for more details.

2.4 ATM Transmit Path in IMA Mode

The MT90220 supports up to four independent IMA Groups. Each of the eight T1/E1 trunks can be assigned to any one of these IMA Groups. A T1/E1 trunk cannot be assigned to more than one IMA Group. Refer to Figure 3 for a functional block diagram of the transmitter.

The IMA transmitter splits the incoming stream into N sub-streams, where 1 ≤ N ≤ 8. Each sub-stream is passed to a separate line interface device that transmits the cells on a physical link.

The physical line rate is either 1.544 Mbps (T1) or

2.048 Mbps (E1). The transmitter inserts so-called ICP cells in the various outgoing streams according to the IMA speciﬁcation. The ICP cells are inserted every M ATM cells on each link. This is the task of the scheduler.

2.4.1 IMA Frame Length (M)

The IMA frame length (value of M) can be 256, 128, 64, or 32. The value of M for each IMA Group is set by the TX Group Control Mode registers. M is ﬁxed once an IMA Group is setup and should remain unchanged so long as that group is operational.

2.4.2 Position of the ICP Cell in the IMA Frame

The TX ICP Cell Offset registers control the position of the ICP cell in the IMA frame for each link. This parameter should remain unchanged so long as that group is operational.

2.4.3 Transmit Clock Operation

The MT90220 supports both the Common Transmit Clock (CTC) and Independent Transmit Clock (ITC) modes of operation. The desired mode is speciﬁed by writing to the TX Group Control Mode register. A reference link must be speciﬁed in the TX Group Control Mode register. The MT90220 introduces a Stuff cell on the reference link every 2048 cells and determines the appropriate time to inser t a Stuff cell on the remaining group links. See paragraph 2.4.4, Stuff Cell Rate, for more details.

MT90220

The clocking mode and reference link are ﬁxed once an IMA Group is setup and should remain unchanged so long as that group is operational. The reference link should not change unless problems are reported with the link.

2.4.4 Stuff Cell Rate

The Stuff event algorithm differs between CTC and ITC modes. In CTC mode, the Stuff event is typically ﬁxed and appears in the same IMA frame on all IMA Group links. In ITC mode, the Stuff event is determined using an adaptive algorithm that relates the level of the internal TX Link FIFO to that of the TX link FIFO of the Reference link.

The MT90220 implements 2 different stufﬁng algorithms: a ﬁxed stufﬁng rate and an adaptive stufﬁng rate. The Stufﬁng events do not happen more frequently than once every ﬁve IMA frames.

TX Group Control Mode register bit 3 selects either the adaptive or ﬁxed algorithm. Bit 4 determines the timing mode declared in the ICP cell.

There are three possible combinations:

• CTC Mode with internal Fixed algorithm

• CTC Mode with internal Adaptive algorithm

• ITC Mode with internal Adaptive algorithm In CTC mode, when using the Fixed algorithm, the

Stuff event is periodic and will appear in the same IMA frame, once every 2048 cells, on each link that is part of the IMA Group.

In CTC mode, when using the Adaptive algorithm, the Stuff event will occur at an average rate of once every 2048 cells on each link and may not occur in the same IMA Frame on all the links.

In ITC mode, the Stuff event is determined using the adaptive algorithm that relates the level of the internal TX Link FIFO with that of the TX Link FIFO of the Reference link. The reference link has one Stuff event every 2048 cells.

Integration register and the value is indicated in Table 1.

Preferred Value

PCM Mode

T1 ISDN (23 channels) 0x09 (216 clocks)

T1 (24 channels) 0x0B (218 clocks)

E1(30 channels) 0x0C (219 clocks)

Table 1 - IDCR Integration Register Value

2.4.6 IMA Controller (RoundRobin Scheduler)

The IMA controller produces the cell stream to be sent to the PCM blocks using the following four cell types:

• Data cells received from the UTOPIA port (User cells)

• Filler cells

• IMA ICP cells with Link status information

• Stuff cells

At an IDCR clock tick, the RoundRobin scheduler inserts either an ICP cell, a User cell or a Filler cell into the TX Link FIFO of the next link of the IMA group, based on ascending link ID numbers. An ICP cell is inserted every M cells and a stuff event is inserted when indicated by the stufﬁng algorithm.

If it is not time for an ICP cell and if the trafﬁc is not enabled for the link (see bit 6 of the TX Link Control register), then a Filler cell is inserted in the TX Link FIFO. If the trafﬁc is enabled and there is a User cell in the TX Utopia FIFO, then the User cell is transferred from the TX UTOPIA FIFO to the TX Link FIFO. If there is no User cell in the TX UTOPIA FIFO, then a Filler cell is inserted in the TX Link FIFO.

2.4.7 ICP Cell Generator

Once per IMA frame, an ICP cell is transmitted on each link of the IMA Group. The content of the ICP cell is controlled both by MT90220 and software. The software content of the ICP cell bytes is stored in buffer RAM. A copy of the ICP cell for each group is kept in the internal Transmitter Cell RAM.

TX IDCR Integration

The state of bit seven in the TX IMA Control register determines whether a Stuff indication is generated in the ﬁrst or ﬁrst four frames preceding a Stuff event.

2.4.5 IMA Data Cell Rate

The MT90220 computes the internal TX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate for the IMA Group reference link, speciﬁed in the TX Group Control Mode register, is integrated over a programmable period of time. The preferred integration period is programmed in the TX IDCR

The ICP cell to be transmitted on each link is assembled on an as required basis under the control of the internal RoundRobin scheduler and ICP Cell Modiﬁer.

Hardware controls the following bytes of the ICP cell:

• Byte 5 - the HEC is always calculated and inserted by the MT90220

• Byte 6 - the TX OAM Label is deﬁned by the software and the value contained in this location is transmitted in all ICP cells, Stuff

MT90220

Byte Description Control Source

1-5 ICP Cell Header Content of Header is under S/W control. The HEC is calculated by H/W.

6 OAM label S/W control 7 Cell ID, Link ID The Link ID is programmed through other registers and inserted by H/W 8 IMA Frame Sequence Hardware Control

9 ICP Cell Offset H/W Control. (Programmed by S/W through other registers) 10 Link Stuff Indication H/W Control 11 Status Change Indic. H/W Control 12 IMA ID S/W Control 13 Group Status and Control S/W Control except for value of M 14 Sync. Info. H/W Control (Programmed by S/W through other registers) 15 Test Control S/W Control 16 TX Test Pattern S/W Control 17 RX Test Pattern S/W Control

18-49 Link Status and Control S/W Control

50 Unused S/W Control 51 End-to-End Channel S/W Control

52-53 CRC Error Control H/W Calculation

Table 2 - ICP Cell Description

Cells and Filler cells sent on all the links that are part of the corresponding TX IMA group

• Byte 7 - the TX Link ID register is used to set the Link Logical ID and the cell type is determined by the internal controller on a per link basis

• Byte 8 - the frame sequence number is controlled by an internal counter

• Byte 9 - the TX ICP Cell Offset register is used to set the value. This value is inserted on a per link basis

• Byte 10 - the link Stuff indication is inserted automatically and the advance indication option is programmed by the TX IMA Control register on a per link basis

• Byte 11 - the SCCI is controlled by internal circuitry. The SCCI is incremented by one for each transfer of the TX ICP cell from the buffer area to the TX Cell RAM.

• Byte 13 - the value of M is programmed through the TX Group Control Mode register

• Byte 14 - the TX Group Control Mode register is used to set the Transmit Timing Information and deﬁne the reference link

• Bytes 52 and 53 - the calculated CRC-10 Error Control bits are inserted automatically

Software controls all remaining bytes of the ICP cells. It also maintains and updates all bytes that are not directly controlled by the MT90220. A dedicated address is reserved for each ICP cell byte for each of the four IMA Groups. This permits direct access to any of the bytes stored in each of the four ICP Cell registers. Refer to Table 2, ICP Cell Description, for details on the ICP cell byte contents.

To avoid updating or corruption problems, the internal copy of the ICP Cell cannot be directly accessed. ICP cells are prepared in a buffer area (RAM inside the MT90220) and transfer commands are issued to copy the content of the ICP cell into the internal Cell RAM area and to start using this new ICP cell. The MT90220 uses a ﬂag (status bit) to indicate that this transfer is underway. Changes should not be made to the content of the ICP cell in the buffer area until the transfer to the internal memory is complete. The status bit is cleared during the transfer and returns to ’1’ on completion of the transfer. IMA Groups are controlled independently. When access to the ICP cell of one group is prohibited, the other ICP cell buffer areas can still be updated. The TX ICP Cell Handler and TX ICP Interrupt Enable registers are used to initiate a transfer and enable an optional interrupt to indicate when the process is complete.

MT90220

The SCCI ﬁeld is incremented by one for each transfer command performed which includes a change in at least one byte of the ICP cell.

2.4.8 IMA Frame Programmable Interrupt

An optional interrupt is provided at the end of an IMA frame to simplify software implemented changes in the Group Control and Status ﬁeld. This interrupt can be enabled on an as required and per group basis to implement a frame counter. The TX ICP Cell Handler and TX ICP Interrupt Enable registers are used for the transfer ready and frame interrupt.

2.4.9 Filler Cell Definition

The content of the Filler cell is pre-initialized and conforms with the IMA Speciﬁcation.

2.4.10 TX IMA Group Start-Up

Initialize the TX IMA Group start-up as follows: (Note: The startup procedure below is given

indicating the most important steps. A more detailed and complete sequence can be found in the MT90220/221 Programmer’s Manual and example code).

• Conﬁgure the TX PCM port(s) by writing to the TX PCM Link Control register 1 and 2.

• Write the value of M, the Timing Mode and the reference link number to the TX Group Control register corresponding to the IMA Group number to be initialized.

• Write the Link ID (LID is between 0-31) to TX Link ID registers for each link to be used in the IMA Group. LID should not be changed when a group is operational. Ensure each link that is part of an IMA group has a unique LID (note that the MT90220 does not verify LIDs).

• Write the ICP Cell Offset value to TX ICP Cell Offset registers. This value depends on the value of M. Typically , the ref erence link will ha v e a delay of 0 cells in the IMA Frame and the ICP cell in each other link will be evenly spaced in a multiple of M/N cells (where M is deﬁned in the

IMA speciﬁcation and N is the number of links). The offset value for an operational g roup should not be changed.

• Write to the TX Link Control registers to put the link(s) in IMA mode and to enable the transfer of ATM User Cells when required.

2.4.11 TX Link Addition

The MT90220 supports software controlled link addition to the existing IMA group. Link addition is used to increase the available bandwidth. The TX PCM Link Control register 1 and 2, the TX Link ID and TX ICP Cell Offset registers are initialized ﬁrst with the proper IMA Group information. The link is assigned to a TX IMA group by writing to the lower 2 bits of the TX Link Control register. The bit 3, 1 and 0 of the Test 2 register have to be written with the proper value. The link is then conﬁgured in IMA mode by writing to the bit 2 of the TX Link Control register. The TX IMA Mode Status register is monitored to detect when the link is reported in IMA mode. When the link is in IMA mode, then the bit 3, 1 and 0 of the Test 2 register are reset to 0. TX Link control register bit 6 determines when ATM User cells can be sent. Note that the Test 2 register cannot be used as a read/modify/write register. The values that are written and the values that are read are independant. Note also that the bit 6 of the Test

2 register should always be set to 1.

2.4.12 TX Link Deletion

There are two reasons to remove a link: the required bandwidth decreases or a link becomes faulty. The MT90220 supports link deactivation under software control.

A link stops transmitting User cells when bit 6 of the TX Link Control register is set to 0. Filler and ICP cells will still be sent on the link. The link is removed from an IMA group by ﬁrst setting the bit 2 of the TX Link Control register to 1 while keeping the original IMA group number. The IMA group number can be changed only when the link is in UNI mode as

ATM In

Transmitter

Cell RAM

Cell_In_Control

Output Controller and

Cell Distribution

Tx Link [N] FIFO

P/S

Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode

(For Link[N] where 1 ≤ N ≤ 8)

Serial Streams Link [N]

MT90220

reported in the TX IMA Mode Status register. It then can be assigned to another IMA group.

When removing the last link of a TX IMA group, the TX Utopia FIFO has to be empty. This can easily be done by ﬁrst disabling the source of ATM cells (ATM Utopia contoller), then disabling the TX Utopia Port using the UTOPIA input Link or Group PHY enable registers while still keeping the "Send User Cell" bit of the TX Link Control Centre register set to 1. The level of the TX Utopia FIFO can be monitored using TX Utopia FIFO Level register. The above procedure can then be applied to assign the link in UNI mode.

When the link is conﬁgured in UNI mode, IDLE cells are transmitted. Writing to the TX PCM Link Control registers either turns off the transmitter or reconﬁgures the link into another mode.

2.5 ATM Transmit Path in UNI Mode

A maximum of eight independent T1/E1 interfaces can be selected in UNI mode. Figure 4 gives a functional block diagram of the transmitter in UNI mode.

ATM cells received from the ATM port are placed in a TX UTOPIA FIFO, waiting to be transmitted. If the Idle/Unassigned cell removal option is selected, these cells are dropped. If the TX UTOPIA FIFO is empty, an Idle cell is sent to the output link. The content of the Idle cell is pre-initialized with the header bytes set at 0x00, 0x00, 0x00 and 0x01. The payload bytes are set to 0x6A.

ATM User cells are transferred from the Input UTOPIA port to the TX PCM port.

3.0 The ATM Receive Path

The receive path corresponds to the cell ﬂow from the T1/E1 interfaces to the ATM UTOPIA Interface. The MT90220 provides cell delineation and optional cell ﬁltering to discard Unassigned or Idle cells on each link. The incoming cells are stored in the external RAM required in IMA mode to perform cell recovery due to delay variation between the links introduced by the network.

3.1 Cell Delineation Function

This block provides the circuitry necessary to perform functions such as Cell Delineation (CD), cell payload de-scrambling, HEC veriﬁcation and ﬁltering of Idle (UNI) cells. The CD circuit delineates ATM cells received from the payload of the T1 or E1 frame through the PCM Interface.

When performing delineation, correct HEC calculations are interpreted to indicate cell boundaries. The CD circuit performs a sequential byte by byte hunt for a correct HEC sequence. While performing this hunt, the cell delineation state machine is in the HUNT state. Figure 5 depicts a state diagram of the cell delineation operation.

Correct HEC (byte by byte)

Incorrect HEC

HUNT

(cell by cell)

PRESYNC

TX UTOPIA FIFO Length Deﬁnition registers are used to set the TX UTOPIA FIFO size. The total number of cells in all the TX UTOPIA FIFOs and TX Link FIFO (includes the links used in IMA Mode and the links used in UNI Mode) is limited to 58.

Idle Cells are transmitted on the UNI PCM Interface until the bit corresponding to the link in the UTOPIA

Input Link PHY Enable register is set. Then, the

ATM CELL DELINEATION SYNC STATE

HCS Multi-Bit Error Detected (cell discarded)

HCS Single Bit Error Detected (corrected or dropped)

No HCS Errors Detected

DELTA

Consecutive

Correct HCS’s

(PRESYNC State)

Cell

Accepted

Correction

Figure 6 - SYNC State Block Diagram

ALPHA

Consecutive

Incorrect HEC

(cell by cell)

SYNC

DELTA Consecutive

Correct HEC

(cell by cell)

Figure 5 - Cell Delineation State Diagram

When a correct HEC is found, the CD circuit locks on the cell boundary and enters the PRESYNC state. The PRESYNC state keeps checking the HEC to ensure that the previous indication was not false.

Cell

Discarded

Detection

ALPHA

Consecutive

Incorrect HCS’s

Jump to HUNT

State

MT90220

False indications are interpreted to mean the circuit is not tracking good ATM cells. After entering the PRESYNC state, the ﬁrst false indication triggers a transition back to HUNT state.

If the PRESYNC state HEC is correct, then a transition to the SYNC state occurs after“δ”cells (DELTA in ITU I.432) are correctly received. In the SYNC state, the CD circuit treats the incoming ATM cell stream as stable and the MT90220 functions normally.

While in the SYNC state, if an incorrect HEC is obtained cell delineation is considered lost and a transition is made back to the HUNT state (see Figure 6).

As deﬁned by the ITU I.432 recommendations, the value of ALPHA and DELTA determine the robustness of the delineation method. The value of ALPHA and DELTA for the Cell Delineation state machine are deﬁned in the Cell Delineation register. Only one set of values is deﬁned for the eight Cell Delineation state machines. The status of the CD state machine for each link is av ailable in bits 0 and 1 of the RX Cell Delineation State register.

The ITU I.432 suggested values are: ALPHA = 7; and DELTA = 6.

“a”

consecutive times (ALPHA in ITU I.432),

While the cell delineation state machine is in the SYNC state, the veriﬁcation circuit implements the state machine shown in Figure 6.

In normal operation, the HEC veriﬁcation state machine remains in the ’correction’ state. Incoming cells containing no HEC errors are passed to the receive IMA block (RX IMA). Incoming single-bit errors can be corrected if required by the application (i.e., single bit error correction can be enabled or disabled).

After correction (when enabled), the resulting ATM cell is passed to the RX IMA block for IMA sequencing control.

If a single or multi bit error occurs, the state machine goes to the ’detection’ state. When a cell with a good HEC is detected, the state machine returns to the ’correction’ state. The HEC calculation normally includes the ATM FORUM polynomial (X6 + X4 + X + 1). The use of the polynomial can be disabled by writing to bit 1 of the RX Link Control register.

3.2 De-Scrambling and ATM Cell Filtering

The CD circuit can de-scramble the cell payload ﬁeld. The de-scrambling algorithm can be enabled or disabled using bit 5 of the RX Link Control registers.

Loss of Cell Delineation (LCD) is detected by counting the number of incorrect cells while in HUNT state. The MT90220 provides an internal Loss Cell Delineation register to set the threshold for this count. A value of 360 in the LCD register would correspond to 79 msec for E1 and 100 msec for T1 applications. The LCD state for each link is available in bit 1 of the IRQ LinkStatus registers, and in bit 6 of the RX Link ID Number register.

The LCD status bit is reporting the current condition of the Cell Delineation State Machine at the time it is read and cannot not be programmed to generate an interrupt when exiting the LCD condition. The software has to poll the status bit to determine when the condition is cleared.

Table 3 provides the time, in microseconds, for the CD circuit to receive a full ATM cell from the T1 and E1 frame payloads.

Format Average Cell Acquisition Time (µs)

T1 276 E1 221

Table 3 - Cell Acquisition Time

The MT90220 can be programmed, using the RX Link Control registers, to discard received ATM cells

with HEC error.

HEC error correction is optional and can be enabled by the CPU. When the option to correct an incoming HEC value with 1 bit error is selected, the HEC is corrected and the cell is not counted as a cell with a bad HEC. If the option to remove the cells that are received with a bad HEC is selected, then the incoming cells are replaced by a Filler cell in IMA mode. The cell is simply discarded when in UNI mode. The counter is not incremented if the HEC value is corrected, when the option is enabled.

Incoming Idle and Unassigned cells can be detected and dropped automatically.

3.3 ATM Receive Path in IMA Mode

The block diagram at Figure 7 illustrates the MT90220 IMA mode receive path. The receiver must rearrange the incoming bit streams from N-links (1 ≤ N ≤ 8) into a single UTOPIA cell stream.

RAM Area

MT90220

RXCK

RXSYNC

DSTi

[0]

RXCK

RXSYNC

DSTi

[7]

S/P

Buffer

IMA

Frame

State

Machine

IMA

Frame

State

Machine

RAM

Controller

Rate

Recovery

Scheduler

Cell

Delineation

Cell

Delineation

Link Info

Registers

ICP

Processing

ICP

Processing

ICP Cell

With Changes

Micro

Figure 7 - The MT90220 Receiver Circuit in IMA Mode

UTOPIA Interface

Recovered

Cell CLK

3.3.1 ICP Cell Processor

In IMA mode, the transmitter inserts special ICP cells in the various outgoing streams every M ATM cells to comply with the IMA speciﬁcation. The receive block is using these ICP cells to synchronize with the Far End transmit side and to reconstruct the ATM cell original sequence.

3.3.1.1 IMA Frame Synchronization

The MT90220 implements IMA Frame Synchronization State Machines (IFSM) for each link, as described in Section 11 of the IMA Speciﬁcation. The values of Alpha, Beta and Gamma are programmable through the Frame Delineation register. Their values are the same for all links.

After the link is programmed to be in IMA mode by writing to the RX Link Control register, the IMA Frame State Machine is enabled. At the same time, the parameter’s value of the RX link are latched in internal reference registers and are used to determine if the received ICP cell meets the valid ICP cell criteria to determine IMA frame synchronization. Refer to section 3.3.1.2 and 3.3.1.3 for the list of link’s parameters.

Incoming ICP cells are automatically detected by the ICP Processing block. As soon as one valid ICP cell is received, the IMA Frame State Machine moves to the IMA PRESYNC state. When Gamma-valid ICP cells are received, the state machine moves to the IMA SYNC state. In the IMA PRESYNC state, one errored or missing ICP cell causes the state machine to return to the IMA HUNT state. In the IMA SYNC state, the state machine is forced to the IMA HUNT state by any of the following events:

• one missing ICP cell

• Alpha consecutive invalid ICP cells

• Beta consecutive errored ICP cells Bits 3 and 2 of the RX State register repor t the IMA

Frame State Machine state for a selected link. When in IMA HUNT mode, the information required to perform the veriﬁcation is extracted from the ICP cells received.

After the received information is validated, the IMA Group is conﬁgured by writing to the RX Reference

Link Control, the RX Link Control and RX Recombiner registers.

MT90220

3.3.1.2 Link Information

All required veriﬁcation and link validation information is extracted from the ICP received cells. The IMA ID, Link ID (LID), Reference Link Number, ICP Cell Offset and Frame Length can be read and validated before enabling an IMA Group link. Software obtains this information by writing to the RX Load Values register to select a link and by reading the RX Link IMA ID, RX Link ICP Offset, RX Link ID and Reference and RX State registers. This information can also be obtained by collecting all the received ICP cells in the RX ICP Cell Buffer and then processing the content of the ICP cell (i.e., writing to the RX ICP Cell Type RAM register and then reading from the RX ICP cell buffer).

The contents of the link information registers should be read after enabling the RX PCM link in the RX PCM Link Control register and before enabling the IMA mode. The link information can be accessed when a link is either in UNI or IMA mode.

3.3.1.3 RX OAM Label

The RX OAM Label is treated differently than the other link’s parameters. Four registers, the RX OAM Label registers, 1 per RX IMA Group, are used to deﬁned the RX OAM Label. Its value is written by the software and can be changed at any point in time. However, the RX OAM Label has to match the value contained in the RX ICP cell for the IMA Frame State Machine to reach the ACTIVE state.

3.3.2 Out of IMA Frame (OIF) Condition

Status bits in the RX OIF Status register, one bit per link, is reporting OIF conditions. The status bit is latching an OIF condition which corresponds to a transition of the IFSM from SYNC to HUNT. The OIF condition is reported as a status bit only and cannot generate an interrupt. The status bit is cleared by writing a 0 to the corresponding bit.

There are 8 OIF counters, one per link. For each OIF transition, the 8-bit counter associated with the link is incremented by one. The counter can be read with indirect access when issuing a load command with the RX Load Values register. The counter can be cleared by writing to the RX OIF Counter Clear

Command register.

3.3.3 Link Out Of IMA Frame (LIF) Synchronization

A link is declared out of IMA Frame (LIF) synchronization state when the IFSM goes in HUNT mode for ’gamma +2’ frames after it was in SYNC state. This condition is latched in bit 2 of the IRQ

Link Status register. Refer to 6.2.2 IRQ Link Status and IRQ Link Enable Registers for more details.

The LIF status bit is reporting the current condition of the IMA Frame State Machine at the time it is read and cannot not be programmed to generate an interrupt when exiting the LIF condition. The software has to poll the LIF status bit to determine when the condition is cleared.

3.3.4 Filler Cell Handling

The MT90220 scans each incoming cell received for the Filler Cell Indication code. Filler cells are written to external RAM to keep the IMA frame aligned. They are automatically discarded after being read from the external RAM by the recombiner.

3.3.5 Stuff Cell Handling

Each incoming ICP cell received is scanned for the Stuff Indication Code. Stuff cells are inserted at the transmit end as two identical and consecutive ICP cells with the Link Stuff Indication Bits set as deﬁned in the IMA speciﬁcation. The MT90220 automatically discards one of the two Stuff cells without storing it in external RAM. The other is kept and processed as a regular ICP cell. IMA Frame synchronization is maintained for all cases (except case 7, O-19 optional requirements) as described in Figure 20 of the IMA Speciﬁcation.

3.3.6 Received ICP Cell Buffer

An internal buffer is implemented to collect cells from the RX PCM links for analysis by the software. This storage unit is a circular buffer for each link and contains up to three cells per link. The buffer can selectively collect:

• all valid cells coming on a RX PCM port

• all valid ICP cells

• all valid ICP cells which contain new information (as indicated by the SCCI ﬁeld, valid only when the link is in IMA mode).

The type of cells collected is deﬁned in the RX ICP Cell Type RAM registers. A status bit and a maskable IRQ alerts the software when a new cell is waiting for processing in a speciﬁc link. These are found in the IRQ Link Status and Enable registers. Valid ICP cells when a link is in UNI mode is determined by a valid HEC byte. When in IMA mode, a valid ICP cell must meet the criteria deﬁned in Table 16 of the ATM IMA spec.

Software can directly access the cells in the RX buffer through a two-cell-wide access window. This access window can be advanced, one cell at a time, by issuing a command to move the internal pointer to the next cells. Since the window accesses two cells,

MT90220

the last processed cell can be accessed at the window’s base address and the new cell at the base address plus 0x40.

The RX ICP Cell Level FIFO register is used to read the level of any of the 8 RX ICP Cell buffers. A ’0’ in this register signiﬁes that no new cell has been received. A ’2’ indicates the possibility that one or more cells have been missed (overﬂow condition).

The cell in the last entry of the circular buffer is the last cell that was meeting the selection criteria. If the Cell FIFO level is 2, it is constantly overwritten by any new valid incoming cell.

The cell that is at the window’s base address when the level is 0 is never overwritten as it is kept for reference.

The RX ICP Cell Buffer Increment Read Pointer register is used to advance the access window by 1 cell at a time. Upon the command, the Buffer level is decreased by 1. When the level reaches 0, the window is not advanced anymore.

During the start-up phase, the software can select to collect all valid ICP cells coming in a RX PCM port and determine if the parameters are acceptable to proceed and start-up an IMA group.

In normal IMA operating mode, the software will select to collect only valid ICP with changes. The Status and Control Change Indication (SCCI) is monitored for all valid ICP cells received. If the SCCI ﬁeld indicates a change in the ICP cells, they are put aside for processing by software.

To accelerate the processing of ICP cells that contain changes, any byte of the last and next processed ICP cell can be accessed directly. To reduce the total processing time by the software, only those bytes that need to be read are accessed. The storage unit keeps the last read ICP cell and has room for up to three new ICP cells.

3.3.7 Rate Recovery

The MT90220 computes the internal RX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate of the reference link is integrated over a programmable period of time. Software must specify the reference link for the IMA Group in the RX Reference Link Control register and the period of integration in the RX IDCR Integration register. Refer to TX IMA Data Cell Rate in Section 2.4.5.

As an option, the reference link can be extracted automatically from the received ICP cell. This option is selected by bit 4 of the RX Reference Link

Control registers. When this option is enabled, the RX Reference Link is always updated to reﬂect the

content of the last valid RXICP cell that was received.

3.3.8 Cell Buffer/RAM Controller

The received cells are temporarily stored in external memory buffers until they can be correctly re-ordered for output. Memory size depends on the number of links and the maximum delay allowed between the links. The memory requirements for different conﬁgurations is listed in Table 4. The memory is

Memory Size

(Kbytes)

Delay (msec)

T1 links E1 links

32Kb 16 13

64Kb 34 27 128Kb 69 55 256Kb 140 112 512Kb 281 225

1024Kb 560 451

Note: Assuming a Guardband of 4 cells

Table 4 - Differential Delay for Various

Memory Conﬁguration

organized in blocks of 64 bytes. Each block can hold one cell. The following equation can be used to determine the maximum delay value or the required RAM size for a determined delay:

MaxDelay

RAMsize[]

---------------------------- -

-- -

1CellTime[]=

To simplify the RAM interface and pin loading, the MT90220 supports the following six, SRAM Control register selectable, external memory conﬁgurations:

• one 32 KByte SRAM device

• two 32 KByte SRAM devices

• one 128 KByte SRAM device

• two 128 KByte SRAM devices

• one 512 KBytes SRAM

• two 512 KBytes SRAM devices. To enable the correct memory access, the Test

Mode Enable register bit 7 has to be set to 1, the value 0x10 should be written to the RX Delay Link

Number register, the bit 3 of the RX External SRAM Control register has to be set to 1 and the bit 6 of Test 2 register has to be set to 1.

3.3.9 Cell Sequence Recovery

When an IMA Group is active, the IMA recombiner manages the pointers to the external RAM write and read location for the stored ATM cells. A cell is read out from the buffer located in the external RAM corresponding to the lowest link ID (LID) of the IMA Group and placed in the RX UTOPIA FIFO. After a

MT90220

complete cell read, a read pointer is set to the buffer corresponding to the next LID. At the following IDCR clock cycle, the next available cell is read. ICP cells are skipped and Filler cells are discarded. This operation is done in a RoundRobin fashion based on the LID value for each IMA Group link. Faulty conditions (i.e., buffer overﬂow, excessive delay) are reported through the IRQ Link Status and IRQ

UTOPIA Status registers.

3.3.10 Delay Between Links

The delay values between links are reﬂecting the various transit delays though the network. In order to rebuild the original ATM cell sequence, the link that exhibits less transport delay has to be stored until the data from the slowest link (link having the largest transport delay) has arrived. The link that exhibits the largest transport delay will be the link that requires the least cells to be stored. Conversely, the line that exhibits the least transport delay is the link that requires the largest number of cells to be stored.

Indirect access is provided to internal registers which hold the various link delay values. The link number and delay type are ﬁrst selected by writing to the RX Delay Select register. After 2 system clock cycles, the 14-bit value in the RX Delay MSB and LSB and the RX Delay Link Number registers are updated and can be read. The valid delay types are: the

Maximum Delay over Time, the Current Maximum Delay and the Current Minimum Delay for an IMA

group and the Current Delay values for any links.

The delay values can be converted to time values by multiplying the number of cells by the conversion factor listed in the Table 5.

The minimum recombiner delay would be the current worst case differential delay. In the example above, the recombiner delay would be set to 12 msec. In this case, a link with larger transport delay than the current worst value cannot be added to an existing IMA group: the cells from this slower link have not arrived when the cells sequence is rebuilt, as the read pointer was set using the previous worst case link. If this slower link is to be added, then the recombiner process has to stop for the time required to receive the cells on the slower link and then the recombiner process can resume. This causes disruption in the operation of the recombiner and will affect the Cell Delay Variation (CDV).

To provide an optimal recombiner delay, the MT90220 adds a guardband delay to the current worst case recombination delay when the IMA Group is ﬁrst started up. Guardband delay is programmable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case. The guardband delay is added to the minimum recombiner delay, when the recombiner process is enabled for the ﬁrst link of an IMA group. The operational delay corresponds to the guardband delay added to the current worst case delay value.

The guardband delay value is speciﬁed for each IMA group by writing to the Guardband/Delta Delay register. It should be the smallest value possible consistent with minimizing the disruptions and the smallest allowed value is 4. When operational, the value of the guardband delay corresponds to the delay value of the link having the greater transport delay (the link where the data is the last to arrive to the MT90220).

Link Type

T1 ISDN (23 ch. per frame) 0.288

T1 (24 ch. per frame) 0.276 E1 (30 ch. per frame) 0.221

Table 5 - Conversion Factors Time/Cell

(msec)

3.3.10.1 RX Recombiner Delay Value

The ICP Cell from each link of the same IMA Group is used to determine the external SRAM read and write pointers. The distance between the read and write pointers is referred to as the recombiner delay. Setting the recombiner delay to the maximum acceptable delay results in a ﬁxed recombiner delay that is not optimum. For example, setting recombiner delay to 25 msec when the worst case delay is 12 msec results in an additional, unnecessary delay of 13 msec.

Time per cell

(msec)

3.3.10.2 RX Maximum Operational Delay Value

The various delays on links of the same IMA Group are measured and compared to the programmed ’maximum allowable value’ stored in the RX Maximum Operational Delay register for the IMA Group. This value corresponds to the worst delay value that is expected. This value cannot be larger than the number of cells that can be stored in the external memory. The smallest ’maximum allowable value’ is four cells. These values are independently established for each of the four IMA Groups.

3.3.10.3 Link Out of Delay Synchronization (LODS)

If a link to be added is slower and cannot be accommodated by the present guardband, an LODS signal is generated and the link delay value is reported negative. A delay is negative when the 2 most signiﬁcant bits are set to "1". The value reported is with respect to the read pointer and

MT90220

represents the minimum number of cells that has to be added to the present guardband before adding the link in the IMA group. See paragraph 3.3.10.6 Incrementing/Decrementing the Recombiner Delay for more details.

If a link to be added is faster and would cause its write pointer to be set beyond the RX Maximum operational Delay programmed value, then the link is reported to be faulty through an LODS condition. The recombination process will not be affected as long as the amount of delay is not larger than the total number of cells in the external memory.

LODS will also be reported if, during operation, the delay of a link is changing to exhibits higher or lower delay which result in a negative delay value or beyond the RX Maximum Operating Delay value.

LODS events are reported by the IRQ Link Status register and the selected Current Maximum Delay register for an IMA Group.

3.3.10.4 Negative Delay Values

If the recombiner process is enabled for a link that is exhibiting a negative delay value then the recombiner process will be suspended until the write pointers are moved in such a way that the delay is reported with a positive value of 4. At this time, the recombiner process will resume. No cells are lost. The same behavior applies if the delay value of a link which is part of the round robin process (recombiner bit ON) goes negative: the recombiner process will be suspended until the delay value becomes positive with a value of 4. The latter condition can happen under severe error conditions if the recombiner process of the faulty link is not disabled.

The Maximum Delay over time value can be reset at any time by writing a clear command to bit 5 in the RX Delay Select register. The differential delays can be easily obtained by subtracting the delay values of the links.

3.3.10.6 Incrementing/Decrementing the Recombiner Delay

If a link to be added has a delay value which falls beyond the worst current delay value, then there are 2 options: either reject the link or re-adjust the pointers. To readjust the pointers, the number of cells to be added (delta) is speciﬁed and corresponds to the amount of extra delay to be added to the current recombination delay. The additional delay is ﬁrst programmed in the Guardband/Delta Delay register and then a command to increase the delay is issued (using the Increment/Decrement Delay Control register). The MT90220 device stops the recombiner process for the amount of time speciﬁed and then resumes the recombiner process. No cells are lost but there is an effect on the CDV. The increment process is completed when the control bit in the Increment/Decrement Delay Control register is returned to a 0 value.

If the link exhibiting the longest transmission delay is removed, the recombiner delay can be reduced accordingly. When such a correction occurs, the number of cells corresponding to the delay correction will be lost. To reduce the impact of this correction, its implementation can either be immediate or delayed. The Increment/Decrement Delay Control register is used for this purpose. The amount of delay to be removed (i.e., number of cells) in the recombiner process is controlled by the Guardband/ Delta Delay register. Alternatively, the links can all be placed in blocking mode for the transition period to avoid losing any cells.

3.3.10.5 Measured Delay Between Links

The values and delay type for a selected link(s) or IMA Group can be read using the RX Delay Select register.

IMA Group delay types include: the Maximum Delay

over time; the Current Maximum Delay and the Current Minimum Delay of an IMA Group. Current Link Delay reports the Current Delay of a link. These values are all reported through a common RX Delay register. The value is in number of cells. All

the delay values include the guardband delay value. The RX Delay Link Number register is reporting the link number associated with the delay value that is currently in the RX Delay registers, with the exception for the Maximum Delay over time value, where the link number reported is not valid (reports value of 0).

If a decrement delay command is issued which would result in a negative delay value on one or more links, the following action will take place: the read pointer is re-adjusted as required by the decrease delay command and since the delay is negative, the recombiner process is suspended until the delay on all the link are at least reaching a positive value of 4. Then, the recombiner process will resume.

3.3.11 RX IMA Group Start-Up

A quick initialization sequence for the RX IMA Group could be as follows (default values can be used for some registers).

(Note: The startup procedure below is given indicating the most important steps. A more detailed and complete sequence can be found in the

MT90220

MT90220/221 Programmer’s Manual and example code).

• Conﬁgure the SRAM parameters using the

SRAM Control, RX External SRAM Control

and Test Mode Enable registers

• Conﬁgure the Cell delineation and IMA Frame State Machines parameters by writing to the

Cell Delineation, Loss Cell Delineation and IMA Frame Delineation registers

• Write to the RX Link Control register to select the RX options

• Conﬁgure the RX PCM port(s) by writing to the RX PCM Link Control register

• Conﬁgure the RX UTOPIA port by writing to the

UTOPIA Output Group PHY Enable and UTOPIA OutputGroup Address registers

• Validate the IMA parameter values received over the PCM links and conﬁgure the link in IMA mode using the RX Recombiner and the RX Link Control register

• When ready, start the recombiner process by writing to the RX Recombiner register

3.3.12 Link Addition

The MT90220 supports software controlled link addition to the existing RX link group. Such an addition can be used to increase available bandwidth. The added link receives Filler cells until the Far End (FE) TX side is active. During this time, the new link’s delay is measured and compared with the current operating limits. The link is either rejected or accepted. The operational delay can be corrected if required as described in 3.3.10.6 Incrementing/ Decrementing the Recombiner Delay. After synchronization is achieved, the added link can be included in the recombiner algorithm using bit 2 of the RX Recombiner register. The link will be effectively included in the IMA Group when the corresponding bit in the Enable Recombination Status register is set.

A link may also be added to an IMA Group when the ﬁrst User cell is received. This is done by writing to the RX Recombiner Delay Control register.

The command to disable the recombination process for a link is issued by writing to bit 2 of the RX Recombiner register.

If the delay of the link to be removed is not the worst delay, then no pointer correction is required and the recombiner bit (i.e., bit 2 of RX Recombiner register) for the removed link should be set to 0.

If it is the worst case delay, then the pointer values should be corrected to reduce the amount of additional delay introduced by the recombiner. The pointers need to be changed (advanced). This results in reducing the number of cells (the amount of time) required for the recombiner process.

To reduce the impact of this correction, its implementation can either be immediate or delayed. A command in the Increment/Decrement Delay Control register is used for this purpose (refer to 3.3.10.6 Incrementing/Decerementing the Recombiner Delay, for more details).

3.3.14 Disabling an IMA Group

Before an IMA Group can be disabled, the software should ensure that no User cells are left in memory. As part of the higher level handshaking, the TX FE should have sent Filler cells for a while for the RX side to process all the User cells that could be in the external memory.

The procedure to follow is to stop the recombination process and then, wait for the enable process to be reported inactive (in the Enable Recombination Status register) before re-assigning the link to another IMA group or to UNI Mode.

3.4 The ATM Receive Path in UNI

Up to eight incoming T1/E1 lines can be connected to the MT90220 receiver and forwarded to the UTOPIA L2 interface served by an external ATMLayer device. Figure 8 illustrates four of the eight possible UTOPIA ports that can be addressed through the UTOPIA Interface.

3.3.13 Link Deletion

There are two reasons to deactivate a link:

• the bandwidth required decreases or

• an existing link becomes faulty.

Both link deactivation procedures speciﬁed in the IMA speciﬁcation are supported under the control of software.

The size of the RX UTOPIA FIFO is ﬁxed. The Idle cells are automatically removed at the RX PCM block and all other valid received cells are transferred to the RX UTOPIA FIFO.

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