MITEL MT89L86AP, MT89L86AN Datasheet

CMOS ST-BUS FAMILY

Multiple Rate Digital Switch

Advance Information

MT89L86

Features

• 3.3 volt supply

• 5V tolerant inputs and TTL compatible outputs.

• 256 x 256 or 512 x 256 switching conﬁgurations

• 8-bit or 4-bit channel switching capability

• Guarantees frame integrity for wideband channels

• Automatic identiﬁcation of ST-BUS/GCI interfaces

• Accepts serial streams with data rates of 2.048,

4.096 or 8.192 Mb/s

• Rate conversion from 2.048 Mb/s to 4.096 or

8.192 Mb/s and vice-versa

• Programmable frame offset on inputs

• Per-channel three-state control

• Per-channel message mode

• Control interface compatible to Intel/Motorola CPUs

• Low power consumption

Applications

• Medium size mixed voice and data switching/ processing matrices

• Hyperchannel switching (e.g., ISDN H0)

• MVIP™ interface functions

• Serial bus control and monitoring

• Centralized voice processing systems

• Voice/Data multiplexer

• ADPCM 32 kbit/s channel switching

DS5195 ISSUE 2 September 1999

Ordering Information

MT89L86AP 44 Pin PLCC MT89L86AN 48 Pin SSOP

-40°C to +85°C

Description

The 3.3V Multiple Rate Digital Switch (MT89L86) is pin compatible with MITEL’s 5V MT8986 and retains all of its functionality. This 3.3v device is designed to provide simultaneous non-blocking connections for up to 256 64kb/s channels or blocking connections for up to 512 64kb/s channels. The serial inputs and outputs may have 32 to 128 64kb/s channels per frame with data rates ranging from 2048 up to 8192 kb/s. It also provides per-channel selection between variable and constant throughput delays allowing voice and grouped data channels to be switched without corrupting the data sequence integrity.

STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15

** for 48-pin SSOP only

Serial

Parallel

Converter

Timing

Unit

CLK FR AS/

ALE

VDDV

DTA

AD7/ AD0

Output

Connection

Memory

RESET

Multiple Buffer Data

Memory

Internal Registers

Microprocessor

Interface

IM DS

CS R/W

A0/ A7

Figure 1 - Functional Block Diagram

MUX

CSTo

ODE

Parallel

Serial

Converter

STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 STo8 STo9

MT89L86 Advance Information

STi3 STi4

STi5 STi6/A6 STi7/A7

CLK STi8/A0 STi9/A1

STi10/A2

AS/ALE

7 8 9 10 11 12 13 14 15 16

STi0

STi1

STi2

STi11/A3

STi12/A4

STi13/A5

44 PIN PLCC

DTA

ODE

STo0

W/WR R/

AD7

STo1

AD6

CSTo

16 5 4 3 2 44434241

231819202122 242526 2728

RD DS/

STo2

STi14/STo8

39 38 37 36 35 34 33 32 31 30 29

AD5

STi15/STo9

STo3 STo4 STo5 STo6/A6 STo7/A7 V

AD0 AD1 AD2 AD3 AD4

V DTA STi0 STi1 STi2

AS/ALE

STi3 STi4 STi5

STi6/A6 STi7/A7

RESET

CLK

STi8/A0 STi9/A1

STi10/A2

IM STi11/A3 STi12/A4 STi13/A5

DS/RD

R/W\WR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 PIN SSOP

(JEDEC MO-118, 300mil Wide)

48 47 46 45 44

43 42 41 40 39 38 37 36

35 34 33 32 31 30 29 28 27 26

CSTo ODE STo0 STo1 STo2 STi14/STo8 STo3

STo4

STo5 STo6/A6 STo7/A7

AD0

AD1

AD2

AD3

AD4

STi15/STo9

AD5

AD6

AD7

Figure 2 - Pin Connections

Pin Description

Pin #

PLCC48SSOP

22 DTA Data Acknowledgment (Open Drain Output). This active low output indicates that a

3-5 7-9

10 10 STi6/A6 ST-B US Input 6/Addr.6 input (5V-tolerant Input). The function of this pin is determined

11 11 STi7/A7 ST-B US Input 7/Addr.7 input (5V-tolerant Input): The function of this pin is determined

Name Description

data bus transfer is complete. A pull-up resistor is required at this output.

STi0-5 ST-BUS Inputs 0 to 5 (5V-tolerant Inputs). Serial data input streams. These streams

may have data rates of 2.048, 4.096 or 8.192 Mbit/s with 32, 64 or 128 channels, respectively.

by the switching conﬁguration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus interface is selected, this pin assumes STi6 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 and STi6 inputs are required simultaneously (e.g., 8 x 4 switching conﬁguration at 4.096 Mb/s or rate conversion between 2.048Mb/ s to 4.196 or 8.192 Mb/s) the A6 input should be connected to pin STo6/A6.

by the switching conﬁguration enabled. If non-multiplexed CPU bus is used along with a higher input rate of 8.192 Mb/s, this pin provides A7 address input function. For 2.048 and 4.096 Mb/s (8x4) applications or when the multiplexed CPU bus is selected, this pin assumes STi7 function. See Control Register bits description and Tables 1, 2, 6 & 7 for more details. Note that for applications where both A7 and STi7 inputs are required simultaneously (e.g., 2.048 to 8.192 Mb/s rate conversion) the A7 input should be connected to pin STo7/A7.

Advance Information MT89L86

Pin Description (continued)

Pin #

PLCC48SSOP

Name Description

12 12,36 V

+3.3 Volt Power Supply.

13 RESET Device Reset ( 5v-tolerant input). This pin is only available for the 48-pin SSOP

package. In normal operation, This active low input puts the MT89L86 in its reset state . It clears the internal counters and registers. All ST-BUS outputs are set to the high impedance state. The RESET pin must be held low for a minimum of 100nsec to reset the device.

13 14 FR Frame Pulse (5V-tolerant Input). This input accepts and automatically identiﬁes frame

synchronization signals formatted according to ST-BUS and GCI interface speciﬁcations.

14 15 CLK Clock (5V-tolerant Input). Serial clock for shifting data in/out on the serial streams.

Depending on the serial interface speed selected by IMS (Interface Mode Select) register, the clock at this pin can be 4.096 or 8.192 MHz.

15-17 16-18 STi8/A0,

STi9/A1,

STi10/A2

Address 0-2 / Input Streams 8-10 (5V-tolerant Input). When the non-multiple xed CPU bus is selected, these lines provide the A0-A2 address lines to the MT89L86 internal registers. When the 16x8 switching conﬁguration is selected, these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s.

19-21 20-22 STi11/A3,

STi12/A4,

STi13/A5

Address 3-5 / Input Streams 11-13 (5V-tolerant Input). When the non-multiplexed CPU bus is selected, these lines provide the A3-A5 address lines to the MT89L86 internal registers. When the 16x8 switching conﬁguration is selected, these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s.

22 23 DS/RD Data Strobe/Read (5V-tolerant Input). When the non-multiple x ed CPU b us or Motorola

multiplex ed b us is selected, this input is DS. This active high input works in conjunction with CS to enable read and write operation. For the Intel/National multiplexed bus interface, this input is RD. This active low input conﬁgures the data bus lines (AD0-7) as outputs.

23 24 R/W\WR Read/Write \ Write (5V -tolerant Input). F or the non-multiple x ed or Motorola multiple x ed

bus interface, this input is R/W. This input controls the direction of the data bus lines (AD0-AD7) during a microprocessor access. For the Intel/National multiplexed bus interface, this input is WR. This active low signal conﬁgures the data bus lines (AD0-7) as inputs.

24 26 CS Chip Select (5V-tolerant Input). This active low input enables a microprocessor read

or write of the MT89L86’s internal control register or memories.

25-27 29-33

27-29 31-35

AD7-AD0 Data Bus (Bidirectional): These pins provide microprocessor access to the internal

control registers, connection memories high and low and data memories. For the multiplexed bus interface these pins also provide the input address to the internal Address Latch circuit.

34 1,

Ground.

25,37

35 38 STo7/A7 ST-BUS Output 7/Address 7 input (Three-state output/input). The function of this pin

is determined by the switching conﬁguration enabled. If non-multiplexed CPU bus is used along with data rates employing 8.192 Mb/s rates, this pin provides A7 address input function. For 2.048 Mb/s applications or when the multiple x ed CPU bus interface is selected, this pin assumes STo7 function. See Tables 1, 2, 6 & 7 for more details.

Note that for applications where A7 input and STo7 output are required simultaneously (e.g., 8.192 to 2.048 Mb/s rate conversion), the A7 input should be connected to pin STi7/A7.

MT89L86 Advance Information

Pin Description (continued)

Pin #

PLCC48SSOP

36 39 STo6/A6 ST-BUS Output 6/Address 6 input (Three-state output/input). The function of this

37-39 41-43

40-42 44-46

44 47 ODE Output Drive Enable (5V -tolerant Input). This is the output enab le input for the STo0

1 48 CSTo Control ST-BUS Output (Output). This is a 2.048 Mb/s output containing 256 bits per

6 6 AS/ALE Address Strobe or Latch Enable (5V-tolerant Input). This input is only used if

18 19 IM CPU Interface Mode (5V-tolerant Input). If HIGH, this input conﬁgures the MT89L86

28 30 STi15/

40 43 STi14/

Name Description

pin is determined by the switching conﬁguration enabled. If non-multiple x ed CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s, this pin pro vides the A6 address input function. For 2.048 Mb/s applications or when the multiplexed CPU bus interface is selected, this pin assumes STo6 function. See Tables 1, 2, 6 & 7 for more details. Note that for applications where both A6 input and STo6 output are required simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion applications), the A6 input should be connected to pin STi6/A6.

STo5-0 ST-BUS Outputs 5 to 0 (Three-state Outputs). Serial data output streams. These

serial streams may be composed of 32, 64 and 128 channels at data rates of 2.048,

4.096 or 8.192 Mbit/s, respectively.

to STo9 serial outputs. If this input is low STo0-9 are high impedance. If this input is high each channel may still be set to high impedance by using per-channel control bits in Connect Memory High.

frame. The level of each bit is determined by the CSTo bit in the Connect Memory high locations.

multiplexed bus is selected via the IM input pin. The falling edge of this signal is used to sample the address into the address latch circuit. When the non-multiplexed bus interface is selected, this input is not required and should be connected to ground.

in the multiplexed microprocessor bus mode. When this input pin is connected to ground, the MT89L86 assumes non-multiplexed CPU interface.

ST-BUS Input 15 / ST -BUS Output 9 (Input/three-state output). This pin is only used

STo9

STo8

if multiplexed CPU bus is selected. If 16-input x 8-output switching conﬁguration is enabled in the SCB bits (IMS register), this pin is an input receiving serial ST-BUS stream 15 at a data rate of 2.048 Mbit/s. If Stream Pair Selection capability is enabled (see s witching conﬁgur ation section), this pin is the ST-BUS stream 9 output. When non-multiplexed bus structure is used, this pin should be connected to ground.

ST-BUS Input 14 / ST -BUS Output 8(Input/three-state output). This pin is only used if multiplexed CPU bus is selected. If 16-input x 8-output switching conﬁguration is enabled in the SCB bits (IMS register), this pin is an input that receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s. If Stream Pair Selection capability is enabled (see s witching conﬁguration section), this pin is the ST-BUS stream 8 output. When non-multiplexed bus structure is used, this pin should be connected to ground.

Advance Information MT89L86

Device Overview

With the integration of voice, video and data services in the same network, there has been an increasing demand for systems which ensure that data at N x 64 kb/s rates maintain sequence integrity while being transported through time-slot interchange circuits. This requirement demands time-slot interchange devices which perform switching with constant throughput delay for wideband data applications while maintaining minimum delay for voice channels.

The MT89L86 device meets the above requirement and allows existing systems based on the MT8980D to be easily upgraded to maintain the data integrity when wideband data is transported. The device is designed to switch 32, 64 or N x 64 bit/s data. This MT89L86 can provide frame integrity for data applications and minimum throughput switching delay for voice applications on a per channel basis.

The serial streams of the MT89L86 can operate at

2.048, 4.096 or 8.192 Bit/s and are arranged in 125 µs wide frames which contain 32, 64 and 128 channels, respectively. In addition, a built-in rate conversion circuit allows the user to interconnect various backbone speeds like 2.048 or 4.096 or

8.192 Mb/s while maintaining the control of throughput delay function on a per-channel basis.

By using Mitel Message mode capability, the microprocessor can access input and output timeslots on a per channel basis to control external circuits or other ST-BUS devices. This MT89L86 automatically identiﬁes the polarity of the frame synchronization input signal and conﬁgures its serial port to be compatible to both ST-BUS and GCI formats.

Two different microprocessor bus interfaces can be selected through an input mode pin (IM): NonMultiplexed or Multiplexed. These interfaces provide compatibility with Intel/National multiplexed and Motorola Multiplexed/Non-Multiplexed buses. The MT89L86 provides a 16 x 8 switching conﬁguration to form a 512 x 256 channel blocking matrix. Also, a ﬂexible Stream Pair Selection operation allows the software selection of which pair of input and output streams can be connected to an internal 128 x 128 matrix. See Switching Conﬁgurations section for details.

TDM serial data can be received at different rates and from different number of serial streams.

Data and Connect Memories

For all data rates, the received serial data is converted to parallel format by the serial to parallel converters and stored sequentially in a Data Memory. Depending on the selected operation programmed in the IMS (Interface Mode Select) register, the Data Memory may have up to 512 bytes in use. The sequential addressing of the Data Memory is performed by an internal counter which is reset by the input 8 kHz frame pulse (FR) marking the frame boundaries of the incoming serial data streams.

Data to be output on the serial streams may come from two sources: Data Memory or Connect Memory. Locations in the Connect Memory, which is split into HIGH and LOW parts, are associated with particular ST-BUS output streams. When a channel is due to be transmitted on an ST-BUS output, the data for the channel can either be switched from an ST-BUS input as in connection mode or it can be from the Connect Memory Low as in message mode. Data destined for a particular channel on the serial output stream is read from the Data Memory or Connect Memory Low during the previous channel time-slot. This allows enough time for memory access and parallel to serial conversion.

Connection and Message Modes

In the connection mode, the addresses of the input source data for all output channels are stored in the Connect memories High (CMH) and Low (CML). The CML and CMH are mapped so that each location corresponds to an output channel on the output streams. The number of source address bits in CMH and CML to be utilized varies according to the switching conﬁguration selected in the IMS register. For details on the use of the source address data (CAB and SAB bits), see CMH and CML bit describethin (Figures 5 & 6). Once the source address bits are programmed by the CPU, the contents of the Data Memory at the selected address are transferred to the parallel-to-serial converters. By having the output channel specify the source channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcast facility within the switch.

Functional Description

A functional Block Diagram of the 3.3V MT89L86 is shown in Figure 1. Depending on the application,

In the message mode the CPU writes data to the Connect Memory Low locations corresponding to the output link and channel number. The contents of the Connect Memory Low are transferred directly to the parallel-to-serial converter one channel before it is to

MT89L86 Advance Information

be output. The Connect Memory Low data is transmitted on to the output every frame until it is changed by the CPU with a new data.

The features of each output channel in the 3.3V MT89L86 are controlled by the Connect Memory High bits. These bits determine individual output channels to be in message or connection mode, select throughput delay types and enable/disable output drivers. The Connect Memory High also provides additional stream and channel address bits for some conﬁgurations. In addition, the Connect Memory High provides one bit to allow the user to control the CST output in 2.048 Mb/s applications.

If an output channel is set to high-impedance, the TDM serial stream output will be placed in high impedance during that channel time. In addition to the per-channel control, all channels on the TDM outputs can be placed in high impedance by pulling the ODE input pin LOW. This overrides the individual per-channel programming by the Connect Memory High bits.

The Connect Memory data is received via the Microprocessor Interface through the data I/O lines. The addressing of the MT89L86 internal registers, Data and Connect memories is performed through address input pins and some bits of the device's Control register. The higher order address bits come from the Control register, which may be written or read through the microprocessor interface. The low er order address bits come directly from address input pins. For details on the device addressing, see Software Control and Control register bits description (Figure 3 & Tables 5, 6 and 7).

the IMS register. When Identical I/O data rates are selected by the DMO bit, the switching conﬁguration and the number of the device's input and output streams can be selected through the SCB bits (Switching Conﬁguration Bits) in the IMS register. See Switching Conﬁgurations section for details.

Depending on the application, the interface clock can be selected to be twice the data rate or equal to the data rate. This selection is performed through bit CLKM in the IMS register. For applications where both serial inputs and outputs are at 2.048 Mb/s (STBUS or GCI format), the CLKM bit should be set LOW enabling the interface clock to be twice the bit rate. In applications where both inputs and outputs are at 4.096 or 8.192 Mb/s, CLKM should be set HIGH enabling the interface clock to be equal to the bit rate. In applications where inputs and outputs are at different rates, the CLKM bit has no effect.

In applications with serial links at 2.048 Mb/s (see Figures 15 to 18), the input 8 kHz frame pulse can be in either ST-BUS or GCI format. This MT89L86 automatically detects the presence of an input frame pulse and identiﬁes what type of backbone is present on the serial interface. Upon determining the interface connected to the serial port, the internal timing unit establishes the appropriate transmit and sampling edges. In ST-BUS format, every second falling edge of the 4.096 MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into the bit cell. In GCI format, every second rising edge of the 4.096 MHz clock marks the bit boundary while data sampling is performed during the falling edge, at three quarters of the bit boundaries.

Serial Data Interface

The master clock (CLK) can be either at 4.096 or

8.192 MHz allowing serial data link operations at

2.048, 4.096 and 8.192 Mb/s. These data rates can be independently selected on input and output streams allowing this MT89L86 device to be used in various speed backbones and in rate conversion applications. The selected data rates apply to the inputs or the output streams. Different bit rates among input streams or among output streams are not allowed. Due to the I/O data rate selection ﬂexibility, two major operations can be selected: Identical or Different I/O data rates.

The DMO bit (Device Main Operation) in the IMS register is used for selecting between Identical I/O rates or Different I/O rates. On system power-up, the CPU should set up the DMO, the IDR (Input Data Rate) and ODR (Output Data Rate) bits located in

For identical I/O rates at 4.096 and 8.192 Mb/s (see Figure 19), the clock and interface data rates are equal. The bit transmit and sampling edges vary according to the applied frame pulse polarity. For example, if the FR pulse polarity is positive, the bit transmit operation is done on every rising edge of CLK and the bit sampling on every falling edge. If the FR pulse polarity is negative, these edges are inverted. For different I/O rates, the MT89L86 side operating at 2.048 Mb/s data rate will comply with ST-BUS or GCI interfaces for transmit and sampling procedures. The MT89L86 side operating at 4.096 or

8.192 Mb/s behaves according to the frame pulse polarity applied. See Figures 21 to 24.

Switching Conﬁgurations

Switching conﬁgurations are determined basically by the interface rates selected at the serial inputs and outputs. To specify the switching conﬁguration

Advance Information MT89L86

required, the IMS register has to be initialized on system power-up. In case of Identical I/O r ates (DMO bit LOW) at both inputs and outputs, the switching conﬁguration is selected by the two SCB bits as shown in Table 8 (see IMS register). In case of different I/O rates (DMO bit HIGH), the switching conﬁguration is always non-blocking with different number of I/O streams which is deﬁned by the IDR and ODR bits (see IMS register).

Identical Input/Output Data Rates

When identical input/output data rate is selected by the DMO bit, the I/O rate is determined by the IDR01 bits, and the ODR0-1 bits are ignored. For each data rate speciﬁed by the IDR bits, diff erent switching conﬁgurations can be selected in the SCB1-0 bits.

Serial Links with Data Rates at 2.048 Mb/s When the 2.048 Mb/s data rate is selected at the IDR

bits, four different I/O conﬁgurations can be selected by the SCB1-0 bits (see Table 8); 8 x 8, 16 x 8, 4 x 4 with stream pair selection and nibble switching.

If 8 x 8 switching conﬁguration is selected, a 256 x 256 channel non-blocking switching matrix is available. In this conﬁguration, the 3.3V MT89L86 is conﬁgured with 8 input and 8 output data streams with 32 64 Bit/s channels each. The interface clock for this operation is 4.096 MHz with both ST-BUS and GCI compatibilities and the per-channel selection between variable and constant throughput delay functions is provided.

In 16 x 8 switching conﬁguration, a 512 x 256 channel blocking switch matrix is available. This conﬁguration is available only when the CPU bus interface is conﬁgured in the multiplexed mode. The device clock in this application is 4.096 MHz, STBUS or GCI compatible. This conﬁguration only provides variable throughput delay.

If the stream pair selection switching conﬁguration is selected, only four input and four outputs (4 pairs of serial streams) can be selected by the CPU to be internally connected to the switch matrix, totalling a 128 x 128 channel non-blocking switch. From the 10 serial link pairs available, two pairs are permanently connected to the internal matrix (STi0/STo0 and STi1/STo1). An internal stream pair selection capability allows two additional pairs of serial links to be selected from the remaining 8 pairs (from STi/ STo2 to STi9/STo9) and be connected to the internal matrix along with the permanently connected STi0/ STo0 and STi1/STo1 streams. The two additional pair of streams called stream pair A and stream pair B, should be selected in the Stream Pair Selection

4.096 MHz compatible to ST-BUS and GCI interfaces. In addition, the per-channel selection between variable or constant throughput delay is available.

In the nibble switching conﬁguration, 4-bit wide 32 Kb/s data channels can be switched within the device. Every serial stream is run at 2.048 Mb/s and transports 64 nibbles per frame. When the Nibble Switching is selected at SCB bits, the 3.3V MT89L86 automatically assumes a 8-input x 4-output stream conﬁguration, providing a blocking switch matrix of 512 x 256 nibbles. If a non-blocking switch matrix is required for nibble switching, the switch capacity is reduced to 256 x 256 channel with a 4 input x 4 output conﬁguration; the non-blocking matrix can be arranged by the user by selecting any four of the 8 input streams. In nibble switching the interface clock is 4.096 MHz.

Serial Links with Data Rates at 4.096 Mb/s Two I/O conﬁgurations can be enabled by the SCB

bits when input and output data rates are 4.096 Mb/s on each serial stream: 8 x 4 and 4 x 4. When 8 x 4 switching conﬁguration is selected, a 512 x 256 channel blocking switch is available with serial streams carrying 64, 64 Kb/s channels each. For this operation, a 4.096 MHz interface clock equal to the bit rate should be provided to the 3.3V MT89L86. Only variable throughput delay mode is provided.

In the 4 x 4 switching conﬁguration, a 256 x 256 channel non-blocking switch is available with serial streams carrying 64, 64 Kb/s channels each. In this conﬁguration, the interface clock is 4.096 MHz and the per-channel selection between variable and constant throughput delay operation is provided. Figure 19 shows the timing for 4.096 Mb/s operation.

Serial Links with Data Rates at 8.192 Mb/s Only 2 input x 2 output stream conﬁguration is

available for 8.192 Mb/s, allowing a 256 x 256 channel non-blocking switch matrix to be implemented. To enable this operation, the IDR bits should be programmed to select 8.192 Mb/s rates and the SCB bits have no effect. At 8.192 Mb/s, every input and output stream provides 128 timeslots per frame. The interface clock for this operation should be 8.192 MHz. Figure 19 shows the timing for

8.192 Mb/s operation.

Table 1 summarizes the 3.3V MT89L86 switching conﬁgurations for identical I/O data rates.

MT89L86 Advance Information

Interface

Serial

Interface

Data Rate

2 Mb/s 4.096 8x8 256x256 Non-Blocking STi0-7/STo0-7 Yes 2 Mb/s 4.096 16x8 512x256 Blocking STi0-15/STo0-7 No

2 Mb/s 4.096 10x10 128x128 Non-Blocking

Nibble

Switching

(2 Mb/s)

4 Mb/s 4.096 8x4 512x256 Blocking STi0-7/STo0-3 No 4 Mb/s 4.096 4x4 256x256 Non-Blocking STi0-3/STo0-3 Yes 8 Mb/s 8.192 2x2 256x256 Non-Blocking STi0-1/STo0-1 Yes

Different Input/Output Data Rates

When Different I/O rate is selected by the DMO bit, the input and output data rates should be selected at the IDR and ODR bits, respectively. The Switching Conﬁguration Bits (SCB) are ignored with this operation. This selection allows the user to multiplex conventional 2.048 Mb/s serial streams into two higher rates and vice-versa. In addition to the rate conversion itself, the MT89L86 allows for a complete 256 x 256 channel non-blocking switch at different rates. In this operation, the per-channel variable/ constant throughput delay selection is provided.

Depending on which data rates are programmed for input and output streams, the number of data streams used on the input and output as well as the serial interface clock (CLK input pin) is different. Once the CPU deﬁnes the data rates at the IDR and ODR bits, the MT89L86 automatically conﬁgures itself with the appropriate number of input and output

Clock

required at

CLK Pin

(MHz)

4.096 8x4 512x256 Nibbles STi0-7/STo0-3 No

Table 1 - Switching Conﬁgurations for Identical Input and Output Data Rate

Number of

Input x Output

Streams

Matrix

Channel

Capacity

(only 4-input x 4-output

can be selected)

streams for the desired operation. Table 2 summarizes the four options available when it is used with different I/O rates. Figures 21 to 24 show the timing for each of the four modes shown in Table

Input Frame Offset Selection

For the 4.096 and 8.192 Mb/s serial interface data rates, the MT89L86 provides a feature called Input Frame Offset allo wing the user to compensate for the varying delays at the incoming serial inputs while building large switch matrices. Usually, different delays occur on the digital backbones causing the data and frame synchronization signals to be skewed at the input of the switch device. This may result in the system frame synchronization pulse to be active at the MT89L86’s FR input before the ﬁrst bit of the frame is received at the serial inputs.

Input/Output

Streams Used

STi0-9/STo0-9 Yes

Variable/

Constant

throughput

Delay

Selection

Interface

Input and

Output

Data Rates

2 Mb/s to 4 Mb/s 4.096 8x4 256x256 Non-Blocking STi0-7/STo0-3 Yes 2 Mb/s to 8 Mb/s 8.192 8x2 256x256 Non-Blocking STi0-7/STo0-1 Yes 4 Mb/s to 2 Mb/s 4.096 4x8 256x256 Non-Blocking STi0-3/STo0-7 Yes 8 Mb/s to 2 Mb/s 8.192 2x8 256x256 Non-Blocking STi0-1/STo0-7 Yes

Clock

required at

CLK Pin

(MHz)

Table 2 - Switching Conﬁgurations for Different I/O Data Rates

Number of Input

x Output

Streams

Matrix

Channel Capacity

Input/Output

Streams Used

Variab le/

Constant

throughput

Selection

Delay

Advance Information MT89L86

When the input frame offset is enabled, an "internal delay" of up to four clock periods is added to the actual data input sampling, providing the MT89L86 serial timing unit a new input frame reference. An internal virtual frame is created which is aligned with the framing of the actual serial data coming in at the serial inputs and not with the FR frame pulse input. In this operation, the transmission of the output frame on the serial links is still aligned to the frame pulse input signal (FR).

The selection of the data input sampling delay is deﬁned by the CPU in the Frame Input Offset Register (FIO). If this function is not required in the user's applications, the FIO register should be set up during system initialization to a state where offset functions are disabled.

Delay Through the MT89L86

The switching of information from the input serial streams to the output serial streams results in a delay. Depending on the type of information to be switched, this MT89L86 can be programmed to perform time-slot interchange functions with different

throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay can be selected ensuring minimum delay between input and output data. In wideband data applications, constant throughput delay can be selected maintaining the frame integrity of the information through the switch.

The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connect memory high.

Variable Throughput Delay Mode (V/C bit = 0)

Identical I/O Data Rates The delay in this mode is dependent on the

combination of source and destination channels and it is independent of the input and output streams. The minimum delay achievable in this MT89L86 depends on the data rate selected for the serial streams. For instance, for the 2.048 Mb/s data rate, the minimum delay achieved corresponds to three time-slots. For the 4.096 Mb/s data rate it corresponds to ﬁve time-slots while it is nine timeslots for the 8.192 Mb/s data rate. Switching

Output Channel (# m)

Input Rate

m < n m=n, n+1, n+2 m= n+3, n+4 m=n+5, .. n+8 m > n+8

2.048 Mb/s 32-(n-m) t.s. m-n + 32 t.s. m-n t.s. m-n t.s. m-n t.s.

4.096 Mb/s 64-(n-m) t.s. m-n + 64 t.s. m-n+64 t.s. m-n t.s. m-n t.s.

8.192 Mb/s 128-(n-m) t.s. m-n + 128 t.s. m-n+128 t.s. m-n+128 t.s. m-n t.s.

Table 3a - Variable Throughput Delay Values for Identical I/O Rate Applications

n= input channel, t.s. = time-slot

I/O Data Rate

Conﬁguration

2 Mb/s to 4 Mb/s

2 Mb/s to 8 Mb/s

4 Mb/s to 2 Mb/s

8 Mb/s to 2 Mb/s

0, 1 2, 3 4, 5 6, 7

dmin=5x 4Mb/s t.s. dmax=1 fr.+(4x 4Mb/s t.s.)

dmin=9x 8Mb/s t.s. dmax=1 fr.+(8x 8Mb/s t.s.)

dmin=3x 2Mb/s t.s. dmax=1 fr.+(2x 2Mb/s t.s.)

dmin=3x 2Mb/s t.s. dmax=1 fr.+(2x 2Mb/s

t.s.)

dmin=(2x 2Mb/s t.s.)+

(3x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(3x 8Mb/s t.s.)

Output Stream Used

dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.) dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(2x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(2x 8Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(1x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(1x 8Mb/s t.s.)

Table 3b - Min/Max Throughput Delay Values for Different I/O Rate Applications

Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.

t.s. = time-slot fr. = 125 µs frame 2 Mb/s t.s. = 3.9 µs 4 Mb/s t.s. = 1.95 µs 8 Mb/s t.s. = 0.975 µs

MT89L86 Advance Information

Data Rate Throughput Delay (d)

2.048 Mb/s d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slots)

2.048 Mb/s time-slot: 3.9µs IN: input time-slot (from 1 to 32)

OUT: output time-slot (from 1 to 32)

4.096 Mb/s d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slots)

4.096 Mb/s time-slot: 1.95 µs IN: input time-slot (from 1 to 64) OUT: output time-slot (from 1 to 64)

8.192 Mb/s d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)

8.192 Mb/s time-slot: 0.975 µs IN: input time-slot (from 1 to 128) OUT: output time-slot (from 1 to 128)

Table 4 - Constant Throughput Delay values

conﬁgurations with input and output channels that provides more than its corresponding minimum throughput delay, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame period. Table 3a shows the throughput delay for each data rate operation.

Different I/O Data Rates Except for the 2 Mb/s to 4 Mb/s and the 2 Mb/s to 8

Mb/s rate conversion operations, the throughput delay from the MT89L86 may vary according to the output stream used for switching.

Table 3b explains the worst case conditions for the throughput delay when different I/O data rate switching conﬁgurations are used.

Constant Throughput Delay mode (V/C bit = 1)

In this mode frame sequence integrity is maintained in both Identical and Different I/O Data Rate operations by making use of a multiple Data-Memory buffer technique. The input channels written in any of the buffers during frame N will be read out during frame N+2. In applications at 2.048 Mb/s for instance, the minimum throughput delay achievable in constant delay mode will be 32 time-slots; for example, when input time-slot 32 (channel 31) is switched to output time-slot 1 (channel 0). Likewise, the maximum delay is achieved when the ﬁrst time slot in a frame (channel 0) is switched to the last time-slot in the frame (channel 31), resulting in 94 time-slots of delay.

To summarize, any input time-slot from input frame N will always be switched to the destination time-slot on output frame N+2. Table 4 describes the constant throughput delay values at different data rates.

Microprocessor Port

The non-multiplexed bus interface provided by the MT89L86 is identical to that provided in the MT8986 Digital Switch device. In addition to the nonmultiplexed bus, this 3.3V MT89L86 device provides an enhanced microprocessor interface with multiplexed bus structure compatible to both Motorola and Intel buses. The multiplexed bus structure is selected by the CPU Interface Mode (IM) input pin.

If the IM input pin is connected to ground, the MT89L86’s parallel port assumes its default Motorola non-multiplexed bus mode identical to that of MT8986. If the IM input is connected HIGH, the internal parallel microprocessor port provides compatibility to MOTEL (MOtorola and InTEL compatible bus) interface allowing direct connection to Intel, National and Motorola CPUs.

The on-chip MOTEL circuit automatically identiﬁes the type of CPU Bus connected to the device. This circuit uses the level of the DS/RD input pin at the rising edge of the AS/ALE to identify the appropriate bus timing connected to the MT89L86. If DS/RD is LOW at the rising edge of AS/ALE then the Motorola bus timing is selected. If DS/RD is HIGH at the rising edge of AS/ALE, the Intel bus timing is selected.

When the parallel port of this device is operating in Motorola, National or Intel multiplexed bus interfaces, the signals available for controlling the device are: AD0-AD7 (Data and Address), ALE/AS (Address Latch Enable/Address Strobe), DS/RD (Data Strobe/Read), R/W\WR (Read/Write\Write), CS (Chip Select) and DTA (Data Acknowledgment). In the Motorola non-multiplexed bus mode, the interface control signals are: data bus (AD0-AD7),

Advance Information MT89L86

six address input lines (A0-A5) and four control lines (CS , DS, R/W and DTA). See Figures 25 to 27 for each CPU interface timing.

The parallel microprocessor port provides the access to the IMS, Control registers, the Connection Memory High, the Connection Memory Low and the Data Memory. All locations can be read or written except for the data memory which can be read only.

Software Control

The address bus on the microprocessor interface selects the internal registers and memories of the MT89L86. If the A5 address input is LOW, the Internal Control, Interface Mode, Stream Pair Selection and Frame Input Offset registers are addressed by the A4 to A0 bits according to Table 5. If the A5 input is HIGH, the remaining address input lines are used to select memory subsections of up to 128 locations corresponding to the maximum number of channels per input or output stream. The address input lines and the Stream Address bits (STA) of the Control register give the user the capability of accessing all sections of the MT89L86’s Data and Connect memories.

The Control and Interface Mode Selection registers together control all the major functions of the device. The Interface Mode Select register should be set up

during system power-up to establish the desired switching conﬁguration as explained in the Serial Interface and Switching Conﬁgurations sections.

The Control register is dynamically used by the CPU to control switching operations in the MT89L86. The Control register selects the device's internal memories and its subsections to specify the input and output channels selected for switching procedures.

The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream Address bits. The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits deﬁne an internal memory subsections corresponding to input or output ST-BUS streams.

Bit 7 (Slip Memory) of the Control register allows split memory operation whereby reads are from the Data memory and writes are to the Connect Memor y LOW.

The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the contents of the Connect Memory LOW

A7 A6 A5 A4 A3 A2 A1 A0 Location

X X 0 0 0 0 0 0 Control Register X X 0 0 0 0 0 1 Interface Mode Select Register X X 0 0 0 0 1 0 Stream Pair Select Register X X 0 0 0 0 1 1 Frame Input Offset Register 0 0 1 0 0 0 0 0 Channel 0* 0

•

1 1 1 1

•

Channel 1*

•

Channel 31* 0 1 1 0 0 0 0 0 Channel 32** 0

•

0 1

•

1 0

•

1 1 1 1

•

1 0

•

1 0

•

1 0

•

1 0

•

1 0

•

Channel 33**

•

Channel 63**

Channel 64***

•

Channel 127***

Table 5 - Address Memory Map

*: channels 0 to 31 are used in 2.048 Mb/s (8 x 8, 16 x 8 and 10 x 10) **: channels 0 to 63 are used in 4.096 Mb/s (Nibble Switching, 4 x 4, 8 x 4 or Different I/O rates) ***: channels 0 to 127 are used in 8.192 Mb/s (2 x 2 or Different I/O rates)

MT89L86 Advance Information

(CML) are output on the ST-BUS output streams once every frame unless the ODE input pin is LOW. If ME bit is HIGH, then the MT89L86 behaves as if bits 2 (Message Channel) and 0 (Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value. If ME bit is LOW, then bit 2 and 0 of each Connect Memor y HIGH location function normally. For example, if bit 2 of the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the contents of the SAB and CAB bits of the CMH and CML deﬁne the source information (stream and channel) of the time-slot that is to be switched to an output.

If the ODE input pin is LOW, then all ser ial outputs are set to high impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual ST-BUS output stream and channel.

The contents of bit 1 (CSTo bit) of each Connection Memory High location is output to the CSTo pin once every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the corresponding bit on CSTo output is transmitted HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo output is transmitted LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially to the CSTo output pin and are synchronous to the 2.048 Mb/s ST-BUS streams. To allow for delay in any external control circuitry the contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS channel 31 bit 6. For more detailed description of the CSTo operation, see section 6 of Application Note MSAN-123.

During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish the high impedance state control to the OE bit of the CMH (CMH

A RESET pin is available for the 48-pin SSOP package. When this pin is set low for a minimum of 100n sec, the ST-BUS outputs are put to the high impedance state and all register contents are set to zero.

0s).

The V/C bit (Variable/Constant Delay) of each Connect Memory High location allows the perchannel selection between Variable and Constant throughput delay modes.

Initialization of the MT89L86

On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple MT89L86 ST-BUS outputs are tied together to form matrices, as these outputs may conﬂict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition.

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