MITEL MT8986AP, MT8986AC, MT8986AE, MT8986AL Datasheet



CMOS ST-BUS FAMILY

MT8986

Multiple Rate Digital Switch

Features

• 256 x 256 or 512 x 256 sw i tc hi ng configurat i ons

• 8-bit or 4-bit ch annel swi tching c apab ility

• Guarantee s fram e integ rity for w ideba nd
channels

• Automatic identification of ST-BUS/GCI
inter fa ces

• Accepts serial streams with data rates up to

8.192 Mb/s

• Rate conve rsi on fro m 2.048 Mb/ s to 4.09 6 or

8.192 Mb/s an d vi ce-ve rsa

• Programmable frame offset on inputs

• Per-channel three-s tate control

• Per-channel mess age mode

• Control interface compatible to Intel/Motorola
CPUs

• Low power co nsu mptio n

Applications

• Medium si ze digi tal sw itch matric es

• Hyperchann el s witch ing (e.g ., ISDN H0)

•MVIP

• Serial bus co ntrol an d mon itoring

• Centralized voice processing systems

• Voice/Data multip lexer

• 32 kbit/s channel switching

™

interface functions

ISSUE 3 May 1995

Ordering Information

MT8986AC 40 Pin Ceramic DIP
MT8986AE 40 Pin Plastic DIP
MT8986AP 44 Pin PLCC
MT8986A L 44 Pin QFP

-40°C to +85°C

Description

The Multiple Rate Digital Switch (MRDX) is an
upgraded version of MITEL's MT8980D Digital
Switch (DX). It is pin compatible with the MT8980D
and retains all of its functionality. This device is
designed to provide simultaneous connections (non­blocking) for up to 256 64kb/s channels or blocking
connections for up to 512 64kb/s channels. The
serial inputs and outputs connected to MT8986 may
have 32 to 128 64kb/s channels per frame with data
rates ranging from 2048 up to 8192 kb/s. The
MT8986 provides per-channel selection between
variable and constant throughput delays allowing
voice and grouped data channels to be switched
without corrupting the data sequence integrity.

In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The
MT8986 is ideal for medium size mixed voice and
data switching/processing applications.

STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8

STi9
* STi10
* STi11
* STi12
* STi13
* STi14
* STi15

* 44 Pin only

Serial

to

Parallel

Converter

Timing

Unit

CLK FR AS/

ALEIM*

V

DDVSS

Multiple Buffer Data

Memory

Internal Registers

Microprocessor

Interface

DS

CS R/W

RD

WR

A0/
A7

DTA

AD7/
AD0

Connection

Figure 1 - Functional Block Diagram

Output

MUX

Memory

CSTo

ODE

Parallel

to

Serial

Converter

STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *

2-63

MT8986

AS/ALE

ODE

STo0

STo1

STo2

CSTo

STi4/STo8

DTA

STi0

STi1

STi2

AS/ALE

ODE

STo0

STo1

STo2

CSTo

STi4/STo8

DTA

STi0

STi1

STi2

STi3
STi4

STi5
STi6/A6
STi7/A7

VDD

FR

CLK
STi8/A0
STi9/A1

STi10/A2

7
8
9
10
11
12
13
14
15
16

17

IM

STi11/A3

165432 44434241

231819 20 21 22 24 25 26 2728

DS/RD

STi3/A5

STi12/A4

R/W/WR

44 PIN PLCC

CS

40

STo3

39
38

STo4

37

STo5

36

STo6/A6

35

STo7/A7

34

VSS

33

AD0

32

AD1

31

AD2

30

AD3

29

AD4

AD5

AD6

AD7

STi15/STo9

FR

A0
A1
A2
A3
A4
A5

1
2

3
4
5

6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

DTA
STi0
STi1
STi2
STi3
STi4

STi5
STi6/A6
STi7/A7

VDD

CLK

DS/RD

R/W\WR

STi6/A6
STi7/A7

STi8/A0
STi9/A1

STi10/A2

40
39

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

STi3
STi4
STi5

VDD

FR

CLK

CSTo
ODE

STo0
STo1
STo2
STo3
STo4

STo5
STo6/A6
STo7/A7

VSS

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

CS

4443424140

1

2
3
4
5
6
7
8
9
10
11

1213141516

IM

STi11/A3

STi12/A4

STi3/A5

44 PIN QFP

3837363534

39

17

1819202122

CS

DS/RD

R/W/WR

AD7

AD6

33
32
31
30
29
28
27
26
25
24
23

AD5

STo3
STo4
STo5
STo6/A6
STo7/A7
VSS
AD0
AD1
AD2
AD3
AD4

STi15/STo9

40 PIN DIP

Figure 2 - Pin Connections

Pin Description

Pin #

40

DIP44PLCC44QFP

1240DTAData Acknowledgeme nt (Open Drain Out put ). This act ive l ow output indicates

2-7 2-5

2-64

7-9

41-43

1-3

Name Descri ption

that a data bus transfer is complete . A 10kΩ pull-up resistor is required at this
output.

STi0-5 ST-BUS Inputs 0 to 5 (Inputs). Serial data input streams. These streams may

have data rates of 2.048, 4.096 or 8.192 Mbi t/s with 32, 64 or 128 channels,
respectively.

MT8986

Pin Description (continued)

Pin #

40

DIP44PLCC44QFP

8 10 4 STi6/ A6 ST-BUS Input 6/Ad dr.6 input (Input). The function of this pin is determined by

9 11 5 STi7/ A7 ST-BUS Input 7/Ad dr.7 input (Input): The function of this pin is determined by

Name Descri ption

the switching configura tion enabled . If non-multiplexed CP U bus is used along
with a higher input rate of 8.192 or 4.096 Mb/s, this pin provides A6 address
input function. For 2.048 and 4.096 Mb/s (8x4) applicati ons or when multiplexed
CPU bus (44 pin only) is selected, this pin assum es STi6 function. S ee Cont rol
Register bits description and Tables 1, 2, 6 & 7 for more details.
Note that for applicati ons where both A6 and STi6 inputs are required
simultaneously (e. g., 8 x 4 swi tching conf igura tion at 4.09 6 Mb/ s or rate
conversion between 2.048Mb/ s to 4.196 or 8.192 Mb/ s) the A6 input shoul d be
connected to pin STo6/A6.

the switching configura tion enabled . If non-multiplexed CP U bus is used along
with a higher input rate of 8.192 Mb/s, this pin provides A7 address input
function.
For 2.048 and 4.096 Mb/s (8x4 ) applications or when multiple xe d CPU bus
(44 pin only) is selected, this pin assumes STi7 function. See Control Register
bits descriptio n and Tables 1, 2, 6 & 7 for more details.
Note that for applicati ons where both A7 and STi7 inputs are required
simultaneously (e.g., 2.048 to 8.192 Mb/s rate co nversion) the A 7 input should
be connected to pin STo7/A7.

10 12 6 V
11 13 7 FR F ram e Pulse (Input). This input accepts and aut omatical ly ident ifies frame

12 14 8 CLK Clock (Input). Serial clock for shiftin g data in/out on the serial streams.

13-15 15-17 9-11 A0-2/

STi8-1 0

16-18 19-21 13-15 A3-5/

STi11-13

19 22 16 DS/RD

20 23 17 R/ W

+5 Volt Power Supply.

DD

synchronization signals formatted ac cording to ST-BUS and GCI interface
specifications.

Depending on the serial interface speed selected by IMS (Interface Mode Select)
register, the clock at this pin can be 4.096 or 8.192 MHz.

Address 0-2 / Input Stre ams 8-1 0 (Input). When non-multiplexe d CPU bus is
selected, these lines provide the A0-A2 address lines to MT8986 inte rnal
registers. When 16x8 switching conf iguration is se lecte d (in 44 pin only), then
these pins are ST-BUS serial inputs 8 to 10 receiving data at 2.048 Mb/s.

Address 3-5 / Input Stre ams 11-13 (Input). When non-multi plexed CP U bus is
selected, these lines provide the A3-A5 address lines to MT8986 internal
registers. When 16x8 switching conf iguration is se lecte d (in 44 pin only), then
these pins are ST-BUS serial inputs 11 to 13 receiving data at 2.048 Mb/s.

Data Strobe/Read (Input). When non-m ult iplexed CPU bus or Motoro la
multiplexed bus (44 pin only) are selected, this input is DS. This active high input
works in conjunction with CS
For Intel/Natio nal mu lti plexed bus (44 pin only), th is input is RD
input configures the data bus lines (AD0-AD7) as outputs.

\WR Read/Write \ Write (Input). In case of non-multiplexed and Motorol a multipl exed

buses (44 pin only), this input is R/W
bus lines (AD0-AD7) during a microprocessor access.
With Intel/Nat ion al multip lexed ti min g (44 pin only), thi s input is WR
low signal configures the data bus lines (AD0-AD7) as inputs.

to enable read and write operation.

. This active low

. This input controls the direction of the data

. This active

21 24 18 CS

22-29 25-27

29-33

30 34 28 V

19-21
23-27

AD7-

AD0

SS

Chip Se le c t (Input ). Active low input enabling a microprocessor read or write of

the control register or internal memories.
Data Bus (Bidirectional): These pins provide mic roprocessor access to the

internal control registers, connection memories high and low and data memories.
In multiplexed bus mode (44 pin) these pins also provide the input address t o the
internal Address Latch circuit.

Ground.

2-65

MT8986

Pin Description (continued)

Pin #

40

DIP44PLCC44QFP

31 35 29 STo7/A7 ST-BUS Output 7/Address 7 inpu t (Three-state output/input). The function of

32 36 30 STo6/A6 ST-BUS Output 6/Address 6 inpu t (Three - state output/input). The function of

33-38 37-39

41-43

31-33
35-37

Name Descri ption

this pin is determined by the switching configurat ion enab led. If non-multipl exed
CPU bus is used along with data rates employing 8. 192 Mb /s rates, this pin
provides A7 address input function. For 2.048 Mb/s applications or when
multiplexe d CPU bus (44 pin only) is selected, t his pin as sumes S To7 function.
See Tables 1, 2, 6 & 7 for more details.

Note that for applicati ons where A7 input and STo7 outpu t are required
simultaneously (e.g., 8.19 2 to 2.048 Mb/s rate conver sion), the A7 input should
be connected to pin STi7/A7.

this pin is determined by the switching configurat ion enab led. If non-multipl exed
CPU bus is used along with a higher data rate employing 8.192 or 4.096 Mb/s,
this pin provides the A6 address input function. F or 2.048 Mb/s appli ca tio ns or
when multiplexed CPU bus (44 pin only) is selected, this pin assumes S To6
function. See Tables 1, 2, 6 & 7 for more details.
Note that for applicati ons where both A6 input and STo6 output are required
simultaneously (e.g., 4.096 to 2.048 Mb/s or 8.192 to 2.048 Mb/s rate conversion
applications), the A6 input should be connected to pin STi6/A6.

STo5-0 ST-BUS Outputs 5 to 0 (Three-state Output s). Serial data output stream s.

These serial streams may be composed of 32, 64 and 128 channels at data rates
of 2.048, 4.096 or 8.192 Mbit/s, respectively.

39 44 38 ODE Output Drive Enable (Input). This is the output enable input for the STo0 to

40 1 39 CSTo Control ST-BUS Output (Output). This is a 2.048 Mb/s o utput containing 256

- 6 AS/ALE Address Strobe or Latc h Enabl e (Inpu t). This input is only used if multiplexed

- 18 IM CPU Interface Mode (Input). If HIGH, this input configures MT 8986 in

- 28 STi15/
STo9

- 40 STi14/
STo8

STo9 serial outputs. If this input is low STo0-9 are high impedance. I f this input is
high each channel may still be put into high impedance by using per-channel
control bits in Connect Memory High.

bits per frame. The level of each bit is determined by the CSTo bit in the Connect
Memory high locations.

bus is selected via the IM input pin (44 pin only).
The falling edge of this signal is used to sample the add ress into the address
latch circuit. In case of non-multiplexed bus, this input is not required and should
be left open.

multiplexed microprocessor bus mode. If this input pin is not connected or
grounded, the MT8986 assumes non-mul tiplexed CP U interf ac e.

ST-BUS Input 15 / ST-BUS Output 9 (Input/three-stat e out put ). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabl ed in the SCB bits (IMS register), th is pin is an input
receiving serial ST-BUS stream 15 at a data rate of 2.048 Mb it/s.
If Stream Pair Select ion capab ilit y is enabled (see switching conf igurat ion
section), this pin is the ST-BUS stream 9 output.
When non-multiplexed bus structu re is used, this pin should be left open.

ST-BUS Input 14 / ST-BUS Output 8 (Input/three-stat e out put ). This pin is only
used if multiplexed CPU bus is selected. If 16-input x 8-output switching
configuration is enabl ed in the SCB bits (IMS register), th is pin is an input that
receives serial ST-BUS stream 14 at a data rate of 2.048 Mbit/s.
If Stream Pair Select ion capab ilit y is enabled (see switching conf igurat ion
section), this pin is the ST-BUS stream 8 output.
When non-multiplexed bus structu re is used, this pin should be left open.

2-66

MT8986

DEVICE OVERVIEW

With the integration of voice, video and data services
in the same network, there has been an increasing
demand for systems which ensure that data at N x
64 kbit/s rates maintain sequence integrity while
being transported through time-slot interchange
circuits. This requirement demands time-slot
interchange devices which perform switching with
constant throughput delay for wideband data
applications while guaranteeing minimum delay for
voice channels.

The MT8986 device meets the above requirement
and allows existing systems based on the MT8980D
to be easily upgraded to maintain the data integrity
when wideband data is transported. The device is
designed to switch 32, 64 or N x 64 kbit/s data. The
MT8986 can provide frame integrity for data
applications and minimum throughput switching
delay for voice applications on a per channel basis.

The serial streams of the MT8986 device can
operate at 2.048, 4.096 or 8.192 Mbit/s and are
arranged in 125 µs wide frames which contain 32, 64
and 128 channels, respectively. In addition, a built-in
rate conversion circuit allows the user to
interconnect various backplane speeds like 2.048 or

4.096 or 8.192 Mb/s while maintaining the control of
throughput delay function on a per-channel basis.

MT8986 device receives TDM serial data at different
rates and from different number of serial streams.

Data and Con nect Memo ries

For all data rates, the received serial data is
converted to parallel format by the serial to parallel
converters and stored sequentially in a Data
Memory. Depending on the selected operation
programmed in the IMS (Interface Mode Select)
register, the Data Memory may have up to 512 bytes
in use. The sequential addressing of the Data
Memory is performed by an internal counter which is
reset by the input 8 kHz frame pulse (FR) marking
the frame boundaries of the incoming serial data
streams.

Data to be output on the serial streams may come
from two sources: Data Memory or Connect Memory.
Locations in the Connect Memory, which is split into
HIGH and LOW parts, are associated with particular
ST-BUS output streams. When a channel is due to
be transmitted on an ST-BUS output, the data for the
channel can either be switched from an ST-BUS
input as in connection mode or it can be from the
Connect Memory Low as in message mode. Data
destined for a particular channel on the serial output
stream is read from the Data Memory or Connect
Memory Low during the previous channel time-slot.
This allows enough time for memory access and
parallel to serial conversion.

By using Mitel Message mode capability, the
microprocessor can access input and output time­slots on a per channel basis to control external
circuits or other ST-BUS devices. The MT8986
automatically identifies the polarity of the frame
synchronization input signal and configures its serial
port to be compatible to both ST-BUS and GCI
formats.

In the 44 pin packages, two different microprocessor
bus interfaces can be selected through an input
mode pin (IM): Non-Multiplexed or Multiplexed.
These interfaces provide compatibility with Intel/
National m ultiplexed and Motorola Multiplexed/Non­Multiplexed buses. In 44 pin, the MT8986 provides a
16 x 8 switching configuration to form a 512 x 256
channel blocking matrix. Also, a flexible Stream Pair
Selection operation allows the software selection of
which pair of input and output streams can be
connected to an internal 128 x 128 matrix. See
Switching Configurations section for details.

Functional Description

A functional Block Diagram of the MT8986 device is
shown in Figure 1. Depending on the application, the

Connection and Mess age Mo des

In connection mode, the addresses of the input
source data for all output channels are stored in the
Connect memories High (CMH) and Low (CML). The
CML and CMH are mapped so that each location
corresponds to an output channel on the output
streams. The number of source address bits in CMH
and CML to be utilized varies according to the
switching configuration selected in the IMS register.
For details on the use of the source address data
(CAB and SAB bits), see CMH and CML bit descrip­tion (Figures 5 & 6). Once the source address bits
are programmed by the CPU, the contents of the
Data Memory at the selected address are transferred
to the parallel-to-serial converters. By having the
output channel specify the source channel through
the connect memory, the user can route the same
input channel to several output channels, allowing
broadcast fa c i lity w ith i n th e switch.

In message mode the CPU writes data to the
Connect Memory Low locations corresponding to the
output link and channel number. The contents of the
Connect Memory Low are transferred directly to the
parallel-to-serial converter one channel before it is to

2-67

MT8986

be output. The Connect Memory Low data is
transmitted on to the output every frame until it is
changed by the CPU with a new data.

The features of each output channel in the MT8986
are controlled by the Connect Memory High bits.
These bits determine individual output channels to
be in message or connection mode, select
throughput delay types and enable/disable output
drivers. The Connect Memory High also provides
additional stream and channel address bits for some
configurations. In addition, the Connect Memory
High provides one bit to allow the user to control the
CSTo output in 2.048 Mb/s applications.

If an output channel is set to high-impedance, the
TDM serial stream output will be placed in high
impedance during that channel time. In addition to
the per-channel control, all channels on the TDM
outputs can be placed in high impedance by pulling
the ODE input pin LOW. This overrides the individual
per-channel programming by the Connect Memory
High bits.

The Connect Memory data is received via the
Microprocessor Interface through the data I/O lines.
The addressing of the MT8986 internal registers,
Data and Connect memories is performed through
address input pins and some bits of the device's
Control register. The higher order address bits come
from the Control register, which may be written or
read through the microprocessor interface. The
lower order address bits come directly from address
input pins. For deta ils on the device addr essing, see
Software Control and Control register bits
description (Figure 3 & Tables 5, 6 and 7).

Serial D ata Interface

The master clock (CLK) can be either at 4.096 or

8.192 MHz allowing serial data link operations at

2.048, 4.096 and 8.192 Mb/s. These data rates can
be independently selected on input and output
streams allowing the MT8986 device to be used in
various speed backplanes and in rate conversion
applications. The selected data rates apply to the
inputs or the output streams. Different bit rates
among input streams or among output streams are
not allowed. Due to the I/O data rate selection
flexibility, two major operations can be selected:
Identica l or D i fferen t I/O data rate s.

and the number of the device's input and output
streams can be selected through the SCB bits
(Switching Configuration Bits) in the IMS register.
See Switching Configurations section for details.

Depending on the appl ication, the interface clock can
be selected to be twice the data rate or equal to the
data rate. This selection is performed through bit
CLKM in the IMS register. For applications where
both serial inputs and outputs are at 2.048 Mb/s (ST­BUS or GCI format), the CLKM bit should be set
LOW enabling the interface clock to be twice the bit
rate. In applications where both inputs and outputs
are at 4.096 or 8.192 Mb/s, CLKM should be set
HIGH enabling the interface clock to be equal to the
bit rate. In applications where inputs and outputs are
at different rates, the CLKM bit has no effect.

In applications with serial links at 2.048 Mb/s (see
Figures 16 to 19), the input 8 kHz frame pulse can be
in either ST-BUS or GCI format. The MT8986 device
automatically detects the presence of an input frame
pulse and identifies what type of backplane is
present on the serial interface. Upon determining the
interface connected to the serial port, the internal
timing unit establishes the appropriate transmit and
sampling edges. In ST-BUS format, every second
falling edge of the 4.096 MHz clock marks a bit
boundary and the input data is clocked in by the
rising edge, three quarters of the way into the bit cell.
In GCI format, every second rising edge of the 4.096
MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at
three quarters of the bit boundaries.

For identical I/O rates at 4.096 and 8.192 Mb/s (see
Figure 20), the clock and interface data rates are
equal. The bit transmit and sampling edges vary
according to the applied frame pulse polarity. For
example, if the FR pulse polarity is positive, the bit
transmit operation is done on every rising edge of
CLK and the bit sampling on every falling edge. If
the FR pulse polarity is negative, these edges are
inverted. For different I/O rates, the MT8986 side
operating at 2.048 Mb/s data rate will comply with
ST-BUS or GCI interfaces for transmit and s ampling
procedures. The MT8986 side operating at 4.096 or

8.192 Mb/s behaves according to the frame pulse
polarity applied. See Figures 22 to 25.

Switching Configurations

The DMO bit (Device Main Operation) in the IMS
register is used for selecting between Identical I/O
rates or D i fferen t I/O rates. O n s yste m p ow e r- u p, th e
CPU should set up the DMO, the IDR (Input Data
Rate) and ODR (Output Data Rate) bits located in
the IMS register. When Identical I/O data rates are
selected by the DMO bit, the switching configuration

2-68

Switching configurations are determined basically by
the interface rates selected at the serial inputs and
outputs. To specify the switching configuration
required, the IMS register has to be initialized on
system power-up. In case of Identical I/O rates
(DMO bit LOW) at both inputs and outputs, the
switching configuration is selected by the two SCB

MT8986

bits as shown in table 8 (see IMS register). In case of
different I/O rates (DMO bit HIGH), the switching
configuration is always non-blocking with different
number of I/O streams which is defined by the IDR
and ODR bits (see IMS register).

Identical Input/Output Data Rates

When identical input/output data rate is selected by
the DMO bit, th e I/O rate is de term ined b y th e ID R0­1 bits, and the ODR0-1 bits are ignored. For each
data rate specified by the IDR bits, different
switching configurations can be selected in the
SCB1-0 bits.

Serial Links with Data Rates at 2.048 Mb/s

When 2.048 Mb/s data rate is selected at the IDR
bits, four different I/O configurations can be selected
by the SCB1-0 bits (see Table 8); 8 x 8, 16 x 8, 4 x 4
with stream pair selection and nibble switching.

If 8 x 8 switching configuration is selected, a 256 x
256 channel non-blocking switching matrix is
available. In this configuration, the MT8986 device is
configured with 8 input and 8 output data streams
with 32 64 Kbit/s channels each. The interface clock
for this operation is 4.096 MHz with both ST-BUS
and GCI compatibilities and the per-channel
selection between variable and constant throughput
delay functions is provided. This configuration is
available in both the 40 and 44 pin packages.

register (SPS). The device clock for this operation is

4.096 MHz compatible to ST-BUS and GCI
interfaces. In addition, the per-channel selection
between variable or constant throughput delay is
available. This configuration is only provided in the
44 pin packages.

In case of nibble switching, 4-bit wide 32 kb/s data
channels can be switched within the device. In this
case, every serial stream is run at 2.048 Mb/s and
transports 64 nibbles per frame. When Nibble
Switching is selected at SCB bits, the MT8986
automatically assumes a 8 input x 4 output stream
configuration, providing a blocking switch matrix of
512 x 256 nibbles. If a non-blocking switch matrix is
required for nibble switching, the switch capacity is
reduced to 256 x 256 channel with a 4 input x 4
output configuration; the non-blocking matrix can be
arranged by the user by selecting any four of the 8
input streams. In nibble switching the interface clock
is 4.096 MHz.

Serial Links with Data Rates at 4.096 Mb/s

Two I/O configurations can be enabled by the SCB
bits when input and output data rates are 4.096 Mb/s
on each serial stream: 8 x 4 and 4 x 4. When 8 x 4
switching configuration is selected, a 512 x 256
channel blocking switch is available with serial
streams carrying 64, 64 Kb/s channels each. For this
operation, a 4.096 MHz interface clock equal to the
bit rate should be provided to MT8986. Only variable
throughput delay mode is provided.

In 16 x 8 switching configuration, a 512 x 256
channel blocking switch matrix is available. This
configuration is only provided in the 44 pin package
and when the CPU interface is configured in
multiplexed bus mode. The device clock in this
application is 4.096 MHz, ST-BUS or GCI
compatible. This configuration only provides variable
throughput delay.

If the stream pair selection switching configuration is
selected, only four input and four outputs (4 pairs of
serial streams) can be selected by the CPU to be
internally connected to the switch matrix, totalling a
128 x 128 channel non-blocking switch. From the 10
serial link pairs available, two pairs are permanently
connected to the internal matrix (STi0/STo0 and
STi1/STo1). An internal stream pair selection
capability allows two additional pairs of serial links to
be selected from the remaining 8 pairs (from STi/
STo2 to STi9/STo9) and be connected to the internal
matrix along with the permanently connected STi0/
STo0 and STi1/STo1 streams. The two additional pair
of streams called stream pair A and stream pair B,
should be selected in the Stream Pair Selection

In case of 4 x 4 switching configuration, a 256 x 256
channel non-blocking switch is available with serial
streams carrying 64, 64 Kb/s channels each. In this
configuration, the interface clock is 4.096 MHz and
the per-channel selection between variable and
constant throughput delay operation is provided.
Figure 20 shows the timing for 4.096 Mb/s operation.

Serial Links with Data Rates at 8.192 Mb/s

Only 2 input x 2 output stream configuration is
available for 8.192 Mb/s, allowing a 256 x 256
channel non-blocking switch matrix to be
implemented. To enable this operation, the IDR bits
should be programmed to select 8.192 Mb/s rates
and the SCB bits have no effect. At 8.192 Mb/s,
every input and output stream provides 128 time­slots per frame. The interface clock for this operation
should be 8.192 MHz. Figure 20 shows the timing for

8.192 Mb/s operation.

Table 1 summarizes the MT8986 switching
configurations for identical I/O data rates.

2-69

MT8986

Interface

Serial

Interface

Data Rate

2 Mb/s 4.096 8x8 256x256 Non-Blocking STi0-7/STo 0-7 Yes
2 Mb/s

*

2 Mb/s

*

Nibble

Switching

(2 Mb/s)

4 Mb/s 4.096 8x4 512x256 Bloc king STi0-7/STo0-3 No
4 Mb/s 4.096 4x4 256x256 Non-Blocking STi0-3/STo0-3 Yes
8 Mb/s 8.192 2x2 256x256 Non-Blocking STi0-1/STo0-1 Yes

Table 1. Switching Configurations for Identical Input and Output Data Rates

* - only in the 44 pin packages

Different Inpu t/Outpu t Data Rat es

When Differen t I/O rate is selec ted by the DMO bit,
the input and output data rates should be selected at
the IDR and ODR bits, respectively. The Switching
Configuration Bits (SCB) are ignored with this
operation. This selection allows the user to multiplex
conventional 2.048 Mb/s serial streams into two
higher rates and vice-versa. In addition to the rate
conversion itself, the MT8986 allows for a complete
256 x 256 channel non-blocking switch at different
rates. In this operation, the per-channel variable/
constant throughput delay selection is provided.

Clock

required at

CLK Pin

(MHz)

4.096 16x8

4.096 10x10

4.096 8x4 512x256 Nibbles STi0-7/STo0-3 No

Number of

Input x
Output

Streams

*

*

Matrix

Channel

Capacity

512x256 Blocking STi0-15/STo0-7 No

128x128 Non-Bloc king

(on ly 4 inpu t x 4-output

can be selected)

Input Frame Offset Selection

When 4.096 or 8.192 Mb/s serial interfaces are
selected, the MT8986 device provides a feature
called Input Frame Offset allowing the user to
compensate for the varying delays at the incoming
serial inputs while building large switch matrices.
Usually, different delays occur on the digital
backplanes causing the data and frame
synchronization signals to be skewed at the input of
the switch device. This may result in the system
frame synchronization pulse to be active at the
MT8986 FR input before the first bit of the frame is
received at the serial inputs.

Input/Outpu t

Streams Used

STi0-9/STo0-9 Yes

Variable/

Constant

throughp ut

Delay

Selection

Depending on which data rates are programmed for
input and output streams, the number of data
streams used on the input and output as well as the
serial interface clock (CLK input pin) is different.
Once the CPU defines the data rates at the IDR and
ODR bits, the MT8986 automatically configures itself
with the appropriate number of input and output
streams for the desired operation. Table 2
summarizes the four options available when MT8986
is used with different I/O rates. Figures 22 to 25
show the timing for each of the four modes shown in
Table 2.

Interface

Input and

Output

Data Rates

2 Mb/s to 4 Mb/s 4.096 8x4 256x256 Non-Blocking STi0-7/STo0-3 Yes
2 Mb/s to 8 Mb/s 8.192 8x2 256x256 Non-Blocking STi0-7/STo0-1 Yes
4 Mb/s to 2 Mb/s 4.096 4x8 256x256 Non-Blocking STi0-3/STo0-7 Yes
8 Mb/s to 2 Mb/s 8.192 2x8 256x256 Non-Blocking STi0-1/STo0-7 Yes

2-70

Clock

require d at

CLK Pin

(MHz)

Table 2. Switching Configurations for Different I/O Data Rates

Number

of Input

x Output

Streams

When the input frame offset is enabled, an "internal
delay" of up to four clock periods is added to the
actual data input sampling, providing the MT8986
serial timing unit a new input frame reference. An
internal virtual frame is created which is aligned with
the framing of the actual serial data coming in at the
serial inputs and not with the FR frame pulse input.
In this operation, the transmission of the output
frame on the serial links is still aligned to the frame
pulse input signal (FR).

The selection of the data input sampling delay is
defined by the CPU in the Frame Input Offset

Variable/

Matrix

Channel Cap aci ty

Input/Outpu t

Streams Used

Constant

throughput

Selection

Delay

MT8986

Register (FI O). If this functi on is not require d in the
user's applications, the FIO register should be set up
during system initialization to a state where offset
functions are disabled.

Delay Through the MT8 986

The switching of information from the input serial
streams to the output serial streams results in a
delay. Depending on the type of information to be
switched, the MT8986 device can be programmed to
perform time-slot interchange functions with different
throughput delay capabilities on a per-channel basis.
For voice applications, variable throughput delay can
be selected ensuring minimum delay between input
and output data. In wideband data applications,
constant throughput delay can be selected
maintaining the frame integrity of the information
through the switch.

The delay through the MT8986 device varies
according to the type of throughput delay selected in
the V

/C bit of the connect memory high.

Variable Throughput Delay Mode (V

/C b it = 0)

it is independent of the input and output streams.
The minimum delay achievable in the MT8986
depends on the data rate selected for the serial
streams. For instance, for 2.048 Mb/s the minimum
delay achieved corresponds to three time-slots. For

4.096 M b/s i t co rrespond s to five ti me-slots wh ile fo r

8.192 Mb/s it is nine time-slots. Switching
configurations with input and output channels that
provides more than its corresponding minimum
throughput delay, will have a throughput delay equal
to the difference between the output and input
channels; i.e., the throughput delay will be less than
one frame period. Table 3a shows the MT8986
throughpu t d e l ay fo r each data rate operat i on.

Different I/O Data Rates

Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s
rate conversion operations, the throughput delay in
the MT8986 may vary according to the output stream
used for switching.

Table 3b explains the worst case conditions for the
throughput delay when different I/O data rate
switching configurations are used.

Identical I/O Data Rates

The delay in this mode is dependent on the
combination of source and destination channels and

Constant Throughput Delay mode (V

In this mode frame sequence integrity is maintained
in both Identical and Different I/O Data Rate

/C bit = 1)

Output Channel (# m)

Input Rate

m < n m=n, n+1, n+2 m= n+3, n+4 m=n+5, .. n+8 m > n+8

2.048 Mb/s 32-(n-m) t.s. m-n + 32 t.s. m-n t.s. m-n t.s. m -n t.s.

4.096 Mb/s 64-(n-m) t.s. m-n + 64 t.s. m -n+64 t.s. m-n t.s. m-n t.s.

8.192 Mb/s 128-(n-m) t.s. m-n + 128 t.s. m-n+128 t.s. m-n+128 t.s. m-n t.s.

Table 3a. Variable Throughput Delay Values for Identical I/O Rate Applications

n= inpu t channel, t.s . = time-s lo t

I/O Data Rate

Configu rati on

2 Mb/s to 4 Mb/s
2 Mb/s to 8 Mb/s
4 Mb/s to 2 Mb/s
8 Mb/s to 2 Mb/s

0, 1 2, 3 4, 5 6, 7

dmin=5x 4Mb/s t.s.
dmax=1 fr.+(4x 4Mb/s t.s.)

dmin=9x 8Mb/s t.s.
dmax=1 fr.+(8x 8Mb/s t.s.)

dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s t.s.)

dmin=3x 2Mb/s t.s.
dmax=1 fr.+(2x 2Mb/s

t.s.)

dmin=(2x 2Mb/s t.s.)+

(3x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(3x 8Mb/s t.s.)

Output Str eam U sed

dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)
dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(2x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(2x 8Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(1x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/ s

t.s.)+(1x 8Mb/s t.s.)

Table 3b. Min/Max Throughput Delay Values for Different I/O Rate Applications

Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.

t.s. = tim e- sl ot

fr. = 125 µs frame
2 Mb/s t.s . = 3 .9 µs
4 Mb/s t. s. = 1.9 5 µs
8 Mb/ s t. s . = 0. 97 5 µs

2-71

MT8986

Data Rate Throughput Delay (d)

2.048 Mb/s d=[32 + (32 - IN) + (OUT - 1)]; (expressed in # time-slot s)

2.048 Mb/s time-sl ot: 3.9µs
IN: input time-slot (from 1 to 32)
OUT: output time-slot (from 1 to 32)

4.096 Mb/s d=[64 + (64 - IN) + (OUT - 1)]; (expressed in # time-slot s)

4.096 Mb/s time-sl ot: 1.95 µs
IN: input time-slot (from 1 to 64)
OUT: output time-slot (from 1 to 64)

8.192 Mb/s d=[128 + (128 - IN) + (OUT - 1)]; (expressed in # time-slots)

8.192 Mb/s time-sl ot: 0.975 µs
IN: input time-slot (from 1 to 128)
OUT: output time-slot (from 1 to 128)

Table 4. Constant Throughput Delay values

operations by making use of a multiple Data-Memory
buffer techn ique. The input channels written in any of
the buffers during frame N will be read out during
frame N+2. In applications at 2.048 Mb/s for
instance, the minimum throughput delay achievable
in constant delay mode will be 32 time-slots; for
example, when input time-slot 32 (channel 31) is
switched to output time-slot 1 (channel 0). Likewise,
the maxim um delay is a chieved when the first tim e
slot in a frame (channel 0) is switched to the last
time-slot in the frame (channel 31), resulting in 94
time-slots of delay.

To summarize, any input time-slot from input frame N
will always be switched to the destination time-slot
on output frame N+2. Table 4 describes the MT8986
constant throughput delay values for different data
rates.

Microprocessor Port

The non-multiplexed bus interface provided by the
MT8986 device is identical to that provided in
MT8980 Digital Switch device. In addition to the non­multiplexed bus, the MT8986 device provides an
enhanced microprocessor interface with multiplexed
bus structure compatible to both Motorola and Intel
buses. The multiplexed bus structure is available
only in the 44 pin packages and it is selected by the
CPU Interface Mode (IM) input pin.

If IM input pin is not connected (left open) or
grounded, the MT8986 parallel port assumes its
default Motorola non-multiplexed bus mode identical
to that of MT8980. If IM input is connected HIGH, the
internal parallel microport provides compatibility to
MOTEL interface allowing direct connection to Intel,
National and Motorola CPUs.

The MOTEL circuit (MOtorola and InTEL compatible
bus) automatically identifies the type of CPU Bus
connected to the MT8986 device. This circuit uses

the level of the DS/RD

input pin at the rising edge of
the AS/ALE to identify the appropriate bus timing
connected to the MT8986. If DS/RD

is LOW at the
rising edge of AS/ALE then Motorola bus timing is
selected . If DS/RD

is HIGH at the rising edge of AS/

ALE, then Intel bus timing is selected.

When MT8986 parallel port is operating in Motorola,
National or Intel multiplexed bus interfaces, the
signals available for controlling the device are: AD0­AD7 (Data and Address), ALE/AS (Address Latch
Enable/Address Strobe), DS/RD
Read), R/W
Select) and DTA

\WR (Read/Write\Write), CS (Chip

(Data Acknowledgement). In

(Data Strobe/

Motorola non-multiplexed bus, the interface control
signals are: data bus (AD0-AD7), six address input
lines (A0-A5) and four control lines (CS

, DS, R/W
and DTA). See Figures 26 to 28 for each CPU
interface timin g.

The MT8986 parallel microport provides the access
to the IMS, Control registers, the Connection
Memory High, the Connection Memory Low and the
Data Memory. All locations can be read or written
except for the data memory which can be read only.

Softwar e Cont rol

The address bus on the microprocessor interface
selects the internal registers and memories of the
MT8986. If the A5 address input is LOW, then the
MT8986 Internal Control, Interface Mode, Stream
Pair Selection and Frame Input Offset registers are
addressed by the A4 to A0 bits according to Table 5.
If A5 input is HIGH, then the remaining address input
lines are used to select memory subsections of up to
128 locations corresponding to the maximum
number of channels per input or output stream. The
address input lines and the Stream Address bits
(STA) of the Control register give the user the
capability of accessing all sections of the MT8986
Data and Connect memories.

2-72

MT8986

The Control and Interface Mode Selection registers
together control all the major functions of the device.
The Interface Mode Select register should be set up
during system power-up to establish the desired
switching configuration as explained in the Serial
Interface and Switching Configurations sections.

The Control register is dynamically used by the CPU
to control switching operations in the MT8986. The
Control register selects the device's internal
memories and its subsections to specify the input
and output channels selected for switching
procedures.

The data in the Control register consists of Split
memory and Message mode bits, Memory select and
Stream Address bits. The memory select bits allow
the Connect Memory HIGH or LOW or the Data
Memory to be chosen, and the Stream Address bits
define an internal memory subsections
corresponding to input or output ST-BUS streams.

Bit 7 (Slip Memory) of the Control register allows split
memory operation whereby reads are from the Data
memory and writes are to the Connect Memory
LOW.

The Message Enable bit (bit 6) places every output
channel on every output stream in message mode;
i.e., the contents of the Connect Memory LOW
(CML) are output on the ST-BUS output streams
once every frame unless the ODE input pin is LOW.
If ME bit is HIGH, then the MT8986 behaves as if bits
2 (Message Channel) and 0 (Output Enable) of every

Connect M emory H IGH ( CMH) loca tions we re set to
HIGH, regardless of the actual value. If ME bit is
LOW, then bit 2 and 0 of each Connect Memory
HIGH loc ation funct ion norm ally. In this case, if bit 2
of the CMH is HIGH, the associated ST-BUS output
channel is in Message mode. If bit 2 of the CMH is
LOW, then the contents of the SAB and CAB bits of
the CMH and CML define the source information
(stream and channel) of the time-slot that is to be
switched to an output.

If the ODE input pin is LOW, then all serial outputs
are high-impedance. If ODE is HIGH, then bit 0
(Output Enable) of the CMH location enables (if
HIGH) or disables (if LOW) the output drivers for the
corresponding individual ST-BUS output stream and
channel.

The contents of bit 1 (CSTo) of each Connection
Memory High location is output on CSTo pin once
every frame. The CSTo pin is a 2048 Mbit/s output
which carr ies 2 56 bits . If CSTo bi t is set HIGH, th e
corresponding bit on CSTo output is transmitted
HIGH. If CSTo bit is LOW, the corresponding bit on
the CSTo output is transmitted LOW. The contents of
the 256 CSTo bits of the CMH are transmitted
sequentially on to the CSTo output pin and are
synchron ous to t he 2.04 8 Mb /s ST-BUS stre ams. To
allow for delay in any external control circuitry the
contents of the CSTo bit is output one channel before
the corresponding channel on the ST-BUS streams.
For example, the contents of CSTo bit in position 0
(ST0, CH0) of the CMH, is transmitted
synchronously with ST-BUS channel 31, bit 7. The
contents of CSTo bit in position 32 (ST1, CH0) of the

A7 A6 A5 A4 A3 A2 A1 A0 Location

XX000000 Control Register
XX000001 Interface Mode Select Regist er
XX000010 Stream Pair Select Register
XX000011 Frame Input Offset Register
00100000 Channel 0*
0

•

•

0
01100000 Channel 32**
0

•

•

0
1

•

•

1

*: c h annels 0 to 31 are used i n 2 .0 48 M b/s (8 x 8, 16 x 8 an d 1 0 x 10)
**: channels 0 to 63 are used i n 4 .0 96 M b/s (N ib bl e Switching , 4 x 4 , 8 x 4 or D iffer en t I/O rates)
***: ch annels 0 to 127 are used in 8.192 Mb /s (2 x 2 or Di fferent I/O rates)

0

•

•

0

1

•

•

1
0

•

•

1

1
1
1
1

1
1
1
1

1
1
1
1

0

•

•
1

0

•

•
1

0

•

•
1

0

•

•

1

0

•

•

1
0

•

•

1

0

•

•

1

0

•

•

1
0

•

•

1

Table 5 . Add ress Me mory Map

0

•

•

1

0

•

•

1
0

•

•

1

1

•

•

1

1

•

•

1
0

•

•

1

Channel 1*

•

•

Channel 31*

Channel 33**

•

•

Channel 63**

Channel 64***

•

•

Channel 127***

2-73

MT8986

CMH is transmitted during ST-BUS channel 31 bit

6. For more detailed description of the CSTo
operation, see section 6 of Application Note MSAN-

123.

The Bit V
Connect Memory High location allows the per­channel selection between Variable and Constant
throughput delay modes.

Initialization of the MT8986

On initialization or power up, the contents of the
Connection Memory High can be in any state. This
is a potentially hazardous condition when multiple
MT8986 ST-BUS outputs are tied together to form
matrices, as these outputs may conflict. The ODE
pin should be held low on power up to keep all
outputs in the high impedance condition.

During the microprocessor initialization routine, the
microprocessor should program the desired active
paths through the matrices, and put all other
channels into the high impedance state. Care
should be taken that no two ST-BUS outputs drive
the bus simultaneously. When this process is
complete, the microprocessor controlling the
matrices can bring the ODE signal high to relinquish
high impedance state control to the CMH

/C (Variable/Constant Delay) of each

0s.

b

2-74