MITEL MT8977AP, MT8977AC, MT8977AE Datasheet
ISO-CMOS ST-BUS FAMILY
MT8977
T1/ESF Framer Circuit (ACCUNETT1.5)
Preliminary Information
Features
• D3/D4 or ESF frami ng and S LC-96 com patib le
• Two frame elastic buffer with jitter tolerance
improved t o 156 UI
• Insertion and dete ction of A, B, C, D bits,
signalling freeze , opti ona l debo unc e
• Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
• Yellow alarm and blue alarm signal capabilities
• Bipolar violation count, F
error count, CRC
T
error count
• Selectab le robbed bit signalling
• Frame and superframe sync. signals, Tx and Rx
• AMI encoding and decoding
• Per channel , overa ll, and re mot e loop around
• Digital ph ase det ecto r betw een T1 line and STBUS
• One uncommitted scan point and drive point
• Pin compa tible wit h MT897 6 a nd MT89 79
• ST-BUS compatible
Applications
• DS1/ESF digital trunk interfaces
• Computer to PBX interfaces (DMI and CPI)
• High speed comp uter t o com pute r data links
ISSUE 2 May 1995
Ordering Information
MT8977AC 28 Pin Cerami c DIP
MT8977A E 28 Pin Pl astic D IP
MT8977A P 44 Pin PLC C
-40°C to 85°C
Descript io n
The MT8977 is a variant of the MT8976 framer,
which has been enhanced to meet ACCUNET
wander tolerance (138 UI).
The MT8977 meets ESF and D3/D4 formats, and is
compatible with SLC-96 systems.
®
T1.5
TxSF
C2i
F0i
RxSF
DSTo
DSTi
CSTi0
CSTi1
CSTo
XCtl
XSt
ST-BUS
Timing
Circuitr y
Data
Interface
Serial
Control
Interface
Control Logic
2 Frame
Elastic Buf fer
with Slip
Control
2048-1544
Converter
ABCD
Signalling RAM
Figure 1 - Functional Block Diagram
ACCUNET® T1.5 is a register ed tra de m ark o f AT & T
DS1
Link
Inte rface
Phase
Detect or
Remote &
DS1
Counter
Digital
Loopbacks
C1.5i
RxFDLClk
RxFDL
RxA
RxB
TxA
TxB
TxFDLClk
TxFDL
RxD
E1.5i
E8Ko
V
•
SS
V
DD
4-99
MT8977 ISO-CMOS Preliminary Information
1
TxA
2
TxB
DSTo
RxD
CSTi1
TxFDL
TxFDLClk
CSTi0
E8Ko
VSS
3
4
NC
5
RxA
6
RxB
7
8
9
10
11
NC
12
13
14
28 PIN CERDIP/PDIP
Pin Description
Pin #
DIP PLCC
Name Description
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
TxA
65432 44434241
7
NC
8
NC
NC
NC
NC
9
10
11
12
13
14
15
16
17
VSS
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
Figure 2 - Pin Conne ctions
TxBNCDSTo
NC
E8Ko
CSTi0
44 PIN PLCC
VDD
VSS
ICNCF0iNCE1.5i
1
2318192021 22 2425 262728
XCtl
VSS
DSTi
CSTo
RxFDLClk
40
39
38
37
36
35
34
33
32
31
30
29
NC
XSt
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
12 TxATransmit A Outpu t. Unipolar output that can be used in conjunction with TxB and
external line driver circuitry to generate the bipolar DS1 signal.
23 TxBTransmit B Output. Unipolar output that can be used in conjunction with TxA
and external line driver circuitry to generate the bipolar DS1 signal.
3 5 DSTo Data ST-BUS Output. A 2048 kbit/s serial output stream which contains the 24
PCM or data channels received from the DS1 line.
44 NC No Connection.
59 RxA
Receive A Complementary Input. Accepts a unipolar split phase signal decoded
externally from the received DS1 bipolar signal. This input, in conjunction with
, detects bipolar violations in the received signal.
RxB
610 RxB
Receive B Complementary Input. Accepts a unipolar split phase signal
decoded externally from the received DS1 bipolar signal. This input, in
conjunction with RxA
, detects bipolar violations in the received signal.
711 RxD Receive Data Input. Unipolar RZ data signal decoded from the received DS1
signal. Gener al l y the signals input at RxA
and RxB are combined externally with a
NAND gate and the resulting composite signal is input at this pin.
813 CSTi1Control ST-BUS Input #1. A 2048 kbit/s serial control stream which carries 24
per-channel control words.
9 14 TxFDL Transmit Facility Data Link (Input). A 4 kHz serial input stream that is
multiplexed into the FDL posit i on in the ESF mode, or the F
pattern when in SLC-
S
96 mode. It is clocked in on the rising edge of TxFDLClk.
10 16 TxFDLClk Transmit Fa cility Da ta Link Clock (O utput). A 4 kHz clock used to clock in the
FDL data.
11 NC No connection.
4-100
Preliminary Information ISO-CMOS MT8977
Pin Description (Continued)
Pin #
Name Description
DIP PLCC
12 19 CSTi0 Control ST-BUS Input #0. A 2048 kbit/s serial control stream that contains 24 per
channel control words and two master control words.
13 20 E8Ko Extracted 8 kHz Output. The E1.5i clock is internally divided by 193 to produce an
8 kHz clock which is aligned with the received DS1 frame and output at this pin. The
8 kHz signal is derived from C1.5 in Digital Loopback mode.
14 6,
V
SS
System Ground.
18,
22
15 23 XCtl External Control (Output). This is an uncommitted external output pin which is set
or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated
once per frame.
16 24 XSt External Status (Schmitt T rigger Input). The state of this pin is sampled once per
frame and the status is reporte d in bit 5 of Master Status Word 2 on CSTo .
17 26 CSTo Control ST-BUS Output. This is a 2048 kbit/s serial control stream which provides
the 24 per-channel status words, and two master status words.
18 27 RxFDLClk Receive Facility Data Link Clock (Output). A 4 kHz clock signal used to clock out
FDL information. The data is clocked out on the rising edge of RxFDLClk.
19 28 DSTi Data ST-BUS Input. This pin accepts a 2048 kbit/s serial stream which contains the
24 PCM or data channels to be transmitted on the T1 trunk.
20 29 RxFDL Received Facility Data Link (Output). A 4 kHz serial output stream that is
demultiplexed from the FDL in E SF mode, or the received Fs bit pattern in SLC-96
mode. It is clocked out on the rising edge of RxFDLClk.
21 34 C2i 2.048 MHz Clock Input. This is the master clock used for clocking serial data into
DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.
22 37 TxSF
Transmit Superframe Pulse Input. A low going pulse applied at this pin will make
the next transmit frame the first frame of a superframe. The device will free run if
this pin is held high.
23 38 RxSF
Received Superframe Pulse Output. A pulse output on this pin designates that the
next frame of data on the ST-BUS is from frame 1 of the received superframe. The
period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are
output only when the device is synchronized to the received DS1 signal.
24 39 C1.5i 1.544 MHz Clock Input. This is the DS1 transmit clock and is used to output data on
TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising
edge of C1.5i.
25 40 E1.5i 1.544 MHz Extracted Clock (Input). This clock which is extracted from the received
, RxB and RxD . The falling edge of the clock
and RxB.
26 42 F0i
data is used to clock in data at RxA
is nominally aligned with the cente r of the received bit on RxD, RxA
Frame Pulse Inpu t. This is the frame synchronization signal which defines the
beginning of the 32 channel ST-BUS frame.
27 44 IC Internal Connecti on. Tied to V
28 1 V
DD
Positive Pow er Su pp ly Inpu t. +5V ±5%.
for normal operation
SS
.
4-101
MT8977 ISO-CMOS Preliminary Information
Functional Timing Diagrams
125µSec
C2i
DSTi
DSTo
CSTi0/CSTi1
CSTo
E1.5i
INT DATA
DS1 AMI
LINE SIGNAL
RxA
RxB
765 4
7
1
6
1
5
4
0
3
3
2
2
1
1
0
0
•
•
Figur e 3 - S T-BUS Ti ming
125µSec
01
10
•
•
1
•
•
•
•
•
•
•
•
•
•
7
•
7
•
RxD
E8Ko
C1.5i
INT DATA
TxA
TxB
DS1 AMI
LINE SIGNAL
Figur e 4 - D S1 Re ceiv e Ti mi ng
Figure 5 - DS1 Transm it Tim in g
4-102
Preliminary Information ISO-CMOS MT8977
29 30 31
25 26 27 28
21 22 23 24
17 18 19 20
30
29
28
26
25
24
22
21
20
18
17
16
31
PC
PC
PC
27
PC
PC
PC
23
PC
PC
PC
19
PC
PC
PC
15
X
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
X
31
MS
W2
2
2
2
2
2
2
2
2
2
2
2
2
15
30
29
28
26
25
24
22
21
20
18
17
16
27
23
19
MS
W
PCS
W
PCS
W
PCS
X
W
PCS
W
PCS
W
PCS
X
W
PCS
W
PCS
W
PCS
X
W
PCS
W
PCS
W
PCS
W1
31
W2
MC
PC
PC
PC
27
PC
PC
PC
23
PC
PC
PC
19
PC
PC
PC
MC
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
W1
1
1
1
1
1
1
1
1
1
1
1
1
30
29 30 31
X
X
X
X
X
25 26 27 28
X
21 22 23 24
X
17 18 19 20
X
29
28
26
25
24
22
21
20
18
17
16
15
13 14 15 16
X
9 101112
X
5678
X
1234
X
ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED
13 14 15 16
X
9 101112
X
5678
X
1234
X
ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED
14
13
12
10
9
8
6
5
4
2
1
PC
PC
PC
11
PC
PC
PC
7
PC
PC
PC
3
PC
PC
PC
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
1
1
1
1
1
1
1
1
1
1
1
1
14
13
12
10
9
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
8
6
5
4
3
2
1
PC
PC
PC
11
PC
PC
PC
7
PC
PC
PC
X
PC
PC
PC
CW
CW
CW
X
CW
CW
CW
X
CW
CW
CW
CW
CW
CW
2
2
2
2
2
2
2
2
2
2
2
2
ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED
W
14
PCS
W
13
PCS
W
12
PCS
X
11
W
10
PCS
9
W
PCS
8
W
PCS
7
X
6
W
PCS
5
W
PCS
4
W
PCS
3
W
PS
2
W
PCS
1
W
PCS
W
PCS
Figure 6 - ST-BUS Channel Allocations
ST-BUS VERSUS DS1 CHANNEL STATUS
DSTi 0
DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
DSTo 0
DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
CSTi0 0
DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PCCW = Per Channel Control Word
MCW1/2 =Ma ster Cont rol Word 1 /2
CSTi1 0
DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
PCCW = Per Channel Control Word
CSTo 0
DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
X = Unused
PCSW =Per C hann el St atus Word
PSW = Phase Sta tus Wo rd
MSW =M aster Status Word
4-103
MT8977 ISO-CMOS Preliminary Info rm atio n
Functional Description
The MT8977 provides a simple interface to a
bidirectional DS1 link. All of the formatting and
signalling insertion and detection is done by the
device. Various programmable options in the device
include: ESF, D3/D4, or SLC-96 mode, common
channel or robbed bit signalling, zero code
suppression, alarms, and local and remote loop
back. All data and control information is
communicated to the MT8977 via 2048 kbit/s serial
streams co nf or mi n g to Mite l ’s ST-BUS fo rma t.
The ST-BUS is a TDM serial bus that operates at
2048 kbits/s. The serial streams are divided into 125
µsec frames that are made up of 32 8 bit channels.
A serial stream that is made up of these 32 8 bit
channels is known as an ST-BUS stream, and one of
these 64 kbit/s channels is known as an ST-BUS
channel.
The system side of the MT8977 is made up of STBUS inputs and outputs, i.e. control inputs and
outputs (CSTi/o) and data inputs and outputs
(DSTi/ o). These signals are functionally represented
in Figure 3. The line side of the device is made up of
the split phase inputs and outputs that can be
interfaced to an external bipolar receiver and
transmitter. Functional transmit and receive
timing is shown in Figures 4 and 5.
Data for transmission on the DS1 line is clocked
serially into the device at the DSTi pin. The DSTi pin
accepts a 32 channel time division multiplexed STBUS stre a m . Data is cl o c ked i n w i th th e fa l ling edge
of the C2i clock. ST-BUS frame boundaries are
defined by the frame pulse applied at the F0i pin.
Only 24 of the available 32 channels on the ST-BUS
serial stream are actually transmitted on the DS1
side. The unused 8 channels are ignored by the
device.
Data recei ved from the DS1 li ne i s cl o c ke d o ut of th e
device in a similar manner at the DSTo pin. Data is
clocked out on the rising edge of the C2i clock. Only
24 of the 32 channels output by the device contain
the information from the DS1 line. The DSTo pin is,
however, actively driven during the unused channel
timeslots. Figure 6 shows the correspondence
between the DS1 channels and the ST-BUS
channels.
All control and monitoring of the device is
accomplished through two ST-BUS serial control
inputs and one serial control output. Cont rol ST-BUS
input number 0 (CSTi0) accepts an ST-BUS serial
stream which contains the 24 per channel control
words and two master control words. The per
channel control words relate directly to the 24
information channels output on the DS1 side. The
master control words affect operation of the whole
device. Control ST-BUS input number 1 (CSTi1)
accepts an ST-BUS stream containing the A, B, C
and D signalling bits. The relationship between the
CSTi channels and the controlled DS0 channels is
shown in Figure 6. Status and signalling information
is received from the device via the control ST-BUS
output (CSTo). This serial output stream contains
two master status words, 24 per channel status
words and one Phase Status Word. Figure 6 shows
the correspondence between the received DS1
channels and the status words. Detailed information
on the operation of the control interface is presented
below.
Progra m ma ble Fe atu res
The main features in the device are programmed
through two master control words which occupy
channels 15 and 31 in Control ST-BUS input stream
number 0 (CSTi0). These two eight bit words are
used to:
• Select the different operating modes of the
device ESF, D3/D4 or SLC-96.
• Activate t he fe atur es tha t are ne eded i n a
certain application; common channel signalling,
zero code s uppre ssi on, si gnall ing de bounc e,
etc.
• Turn on in service alarm s, di agnos tic loop
arounds, an d the extern al c ontrol fun ction .
Tables 1 and 2 contain a complete explanation of
the function of the different bits in Master Control
Words 1 and 2.
Major Operating Modes
The major operating modes of the device are
enabled by bits 2 and 4 of Master Control Word 2.
The Extended Superframe (ESF) mode is enabled
when bit 4 is set high. Bit 2 has no effect in this
mode. The ESF mode enables the transmission of
the S bit pattern shown in Table 3. This includes the
frame/superframe pattern, the CRC-6, and the
Facility Data Link (FDL). The device generates the
frame/multiframe pattern and calculates the CRC for
each superframe. The data clocked into the device
on the TxFDL pin is incorporat ed into the FDL. ESF
mode will also insert A, B, C and D signalling bits into
the 24 frame multiframe. The DS1 frame begins
after approximately 25 periods of the C1.5i clock
from the F0i
During synchronization the receiver locks to the
incoming frame, calculates the CRC and compares it
frame pulse.
4-104
Preliminary Information ISO-CMOS MT8977
Bit Name Description
7 Debounce When set the received A, B, C and D signalling bits are reported directly in the per channel status
words output at CSTo. When clear, the signalling bits are debounced for 6 to 9 ms before they are
placed on CSTo.
6 TSPZCS Transparent Zero Code Suppression. When this bit is set, no zero code suppression is
implemented.
5 B 8ZS Binary Eight Zero Suppression. When this bit is set, B8ZS zero code suppression is enabled.
When clear, bit 7 in data channels containing all zeros is forced high before being transmitted on the
DS1 side. This bit is inactive if the TSPZCS bit is set.
4 8KHSel 8 kHz Output Select. When set, the E8Ko pin is held high. When clear, the E8Ko generates an 8
kHz output derived from the E1.5i or C1.5 clock (see Pin Description for E8Ko).
3 XCtl External Control Pin. When set, the XCtl pin is held high. When clear, XCtl is held low.
2 ESFYL W ESF Yellow Alarm. V alid only in ESF mode. When set, a sequence of eight 1’s followed by eight 0’s
is sent in the FDL bit positions. When clear, the FDL bit contains data input at the TxFDL pin.
1 Robbed bit When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When clear, A, B,
C and D signalling bit insertion in bit 8 for all DS0 transmit channels in every 6
0 YLALR Yellow Alarm. When set, bit 2 of all DS1 channels is set low. When clear, bit 2 operates normally.
Table 1. Master Control Word 1 (Channel 15, CSTi0)
th
frame is enabled.
.
to the CRC received in the next multiframe. The
device will not declare itself to b e in s ynchro n ization
unless a valid framing pattern in the S-bit is detected
and a correct CRC is received. The CRC check in
this case provides protection against false framing.
The CRC check can be turned off by setting bit 1 in
Master Control Word 2.
The device can be forced to r esynchronize itself. If
Bit 3 in Master Contr ol Word 2 is set for one frame
and then sub sequently reset, the d evice will start to
search for a new frame position. The decision to
reframe is made by the user’s system processor on
the basis of the status conditions detected in the
received master status words. This may include
consideration of the number of errors in the received
CRC in conjunction with an indication of the presence
of a mimic. Wh en the devi ce attain s sy nchroniza tion
the mimic bit in Master Status Word 1 is set if the
device found anothe r poss ible can didate w hen it was
searching for the fram i ng pa tter n.
Note that the device will resynchronize automatically
if the errors in the terminal framing pattern (F
T
or
FPS) exceed the threshold set with bit 0 in Master
Control Word 2.
Standard D3/D4 framing is enabled when bit 4 of
Master Control Word 2 is reset (logic 0). In this
mode the device searches for and inserts the
framing pattern shown in Table 4. This mode only
supports AB bit signalling, and does not contain a
CRC check.
The CRC/MIMIC bit in Master Control Word 2, when
set high, allows the device to synchronize in the
presence of a mimic. If this bit is reset, the device
will not synchronize in the presence of a mimic (Also,
refer to section on Framing algorithm).
In the D3/D4 mode the device can also be made
compatible with SLC-96 by setting bit two of Master
Control Word 2. This allows the user to insert and
extract the signalling framing pattern on the DS1 bit
stream using the FDL input and output pins. The user
must format this 4 kbits of information externally to
meet all of the requirements of the SLC-96
specification (see Table 5). The device multiplexes
and demultiplexes this information into the proper
position. Thi s mo de of operation c an also be used for
any other application that uses all or part of the
signalling framing pattern. As long as the serial
stream clocked into the TxFDL contains two proper
sets of consecutive synchronization bits (a s shown in
Table 5 for frames 1 to 24), the device will be able to
insert and extract the A, B signalling bits. The TxSF
pin should be held high in this mode. Superframe
boundaries cannot be defined by a pulse on this
input. The RxSF
output functions normally and
indicates the superframe boundaries based on the
synchronization pattern in the F
received bit
S
position.
Zero Code Suppression
The combination of bits 5 and 6 in Master Control
Word 1 allow one of three zero code suppression
schemes to be selected. The three choices are:
none, binary 8 zero suppression (B8ZS), or jammed
bit (bit 7 forced high). No zero code suppression
4-105
MT8977 ISO-CMOS Preliminary Information
Bit Name Description
7 RMLOOP Remote Loopback. When set, the data received at RxA and RxB is looped back to TxB and T xA
respectively. The data is clocked into the device with E1.5i. The device still monitors t he received
data and outputs it at DSTo. The device operates normally when the bit is clear.
6 DGLOOP Digital Loopback. When set, the data input on DSTi is looped around to DSTo. The normal received
data on RxA
and TxB. The device frames up on the looped data using the C1.5i clock.
5 ALL1'S All One’s Alarm. When set, the chip transmits an unframed all 1's signal on TxA and TxB.
4 ESF/D4 ESF/D4 Select. When set, the device is in ESF mode. When clear, the device is in D3/D4 mode.
3 ReFR Reframe. If set for at least one frame and then cleared, the chip will begin to search for a new frame
position. Only the change from high to low will cause a reframe, not a continuous low level.
2 SLC-96 SLC-96 Mode Select. The chip is in SLC-96 mode when this bit is set. This enables input and
output of the F
use the same framing algorithm as D3/D4 mode. The user must insert the valid F
superframes to allow the receiver to find superframe sync, and the transmitter to insert A and B bits
in eve ry 6
Inactive in ESF mo de.
1 CRC/MIMIC In ESF mode, when set, the chip disregards the CRC calculation during synchronization. When
clear, the device will check for a correct CRC before going into synchronization. In D3/D4 mode,
when set, the device will synchronize on the f irst c orrect S-bit pattern detected. When this bit is
clear, the device will not synchronize if it has detected more than one candidate for the frame
alignment pattern (i.e., a mimic).
0 Maint. Maintenance Mode. When set, the device will declare itself out-of-sync if 4 out of 12 c onsecutive F
bits are in error. When clear, the out-of-sync threshold is 2 errors in 4 F
consecutive bits following an errored F
, RxB and RxD is ignored. However, the data input at DSTi is still transmitted on TxA
bit pattern using the same pins as the facility data link in ESF mode. The chip will
S
th
frame. The SLC-96 FDL completely replaces the FS pattern in the outgoing S bit position.
bits. In this mode, four
bit are examined.
T
T
bits in 2 out of 6
S
T
.
Table 2. Master Control Word 2 (Channel 31, CSTi0)
allows the device to interface with systems that have
already applied some form of zero code suppression
to the data input on DSTi. B8ZS zero code
suppression replaces all strings of 8 zeros with a
known bit pattern and a specific pattern of bipolar
violations. This bit pattern and violation pattern is
shown in Figure 7. The receiver monitors the
received bit pattern and the bipolar violation pat tern
and replaces all matching strings with 8 zeros.
Loopback Modes
Remote and digital loopback modes are enabled by
bits 6 and 7 i n M a ster C on tro l Wo rd 2 . These mo des
can be us ed for diagnostics in locating the source of a
fault condition. Remote loop around loops back data
received at RxA
and RxB back out on TxA and TxB,
thus effectively sending the received DS1 data back
to the far e nd unalte red so th at the tra nsmission l ine
can be tested. The received signal is still monitored
with the appropriate received channels on the DS1
side made available in the proper format at DSTo.
no transmission line or when there is a suspected
failure of the line.
The all one’s transmit alarm (also known as the blue
alarm or the keep alive signal) can be activated in
conjunction with the digital loop around so that the
transmission line sends an all 1's signal while the
normal data is looped back locally.
The MT8977 also has a per channel loopback mode.
See Table 6 and the following section for more
information.
Per Channel Control Features
In addition to the two master control words in C STi0
there are a lso 24 Per Chan nel Co ntrol Words. T hes e
control words only affect individual DS0 channels.
The correspondence between the channels on CSTi0
and the affected DS0 channel is shown in Fig. 6.
The digital loop around mode diverts the data
received at DSTi back out the DSTo pin. Data
received on DSTi is, however, still transmitted out via
TxA and TxB. This loop back mode can be used to
test the near end interface equipment when there is
4-106
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