MITEL MT8965AE, MT8966AS, MT8964AE, MT8963AE, MT8963AS Datasheet

...



ISO

-CMOS

MT8960/61/62/63/ 64/65/66/67

Integrated PCM Filter Codec

Features

•ST-BUS compatible

• Transmit/Rec eive f ilters & PCM Codec i n on e I.C

• Meets AT&T D3/D4 and CC ITT G7 11 and G712

• µ-Law: MT8960/62/64/67

• A-Law: MT8961/63/65/67

• Low power co nsu mpt ion:

Op.: 30 mW typ. Stby.: 2.5 mW typ.

• Digital Codi ng Opti ons : MT8964/65/66/67 CCITT Code

MT8960/61/62/63 Alternative Code

• Digitally cont rolled gain ad jus t of both f ilters

• Analog and digi tal loop bac k

• Filters and c odec in depen de ntly us er accessible for testing

• Powerdown mode available

• 2.048 MHz master clock input

• Up to six uncommitted control outputs

• ±5V ±5% power s upp ly

ISSUE 10 May 1995

Ordering Information

MT8964/65AC 18 Pin Ceramic DIP MT8960/61/64/65AE 18 Pin Plastic DIP MT8962/63AE 20 Pin Plastic DIP MT8962/63/66/67AS 20 Pin SOIC

0°C to+ 70°C

Descript io n

Manufac tured in IS O2-CMOS, these integrated filter/ codecs are designed to meet the demanding performance needs of the digital telecommunications industry, e.g., PABX, Central Office, Digital telephones.

ANUL

SD0 SD1 SD2 SD3 SD4 SD5

Transmit

Filter

Output

Receive

Filter

Ref

Analog to

Digital PCM

Encoder

A Register

B-Register

PCM Digita l

to Analog

Decoder

GNDA GNDD V

8-Bits

DDVEE

Output

Control

Logic

Input

DSTo

CSTi CA

F1i C2i

DSTi

Figure 1 - Functional Block Diagram

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MT8960/61/62/63/64/65/66/67 ISO

-CMOS

MT8960/61/64/65

CSTi DSTi

DSTo

VDD

SD3 SD2

1 2

C2i

4 5

F1i

7 8 9

18 PIN CERDIP/PDIP

18 17 16 15 14 13 12 11 10

GNDD VRef GNDA VR ANUL VX VEE SD0 SD1

CSTi DSTi

DSTo

VDD

MT8962/63/66/67

1 2

C2i

5 SD5 SD4

SD3

F1i

20 PIN PDIP/SOIC

20 19 18 17 16 15 14 13 12 11

GNDD VRef GNDA VR ANUL VX VEE SD0 SD1 SD2

Figure 2 - Pin Conne ctions

Pin Description

Pin Name Description

CSTi Control ST-BUS In is a TTL-compa tib le digit al inpu t used to control the functi on of the filter/cod ec.

Three modes of operation may be effect ed by applying to this input a logic high (V (GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i

Functions controlled are : powerdown, filter gain adjust, loopba ck, chip testing, SD outputs.

DSTi Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.

), logic low

C2i Clock Input is a TTL-compatible 2.048 MHz clock.

DSTo Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM

word.

F1i

Positi ve pow er Supp ly (+5V).

Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,

PCM output and digital cont rol input . It is internally sampled on every positive edge of the clock, C2i, and provides f rame and channel synchronization.

CA Control Address is a three-level digit al input which enabl es PCM input and output and determine s

into which control register (A or B) the serial data, presented to CSTi, is stored.

SD3 System Drive Output is an open drain output of an N-channel transistor which has its source tied to

GNDA. Inactive stat e is open circui t.

SD4-5 System Drive Outputs

are open drain outputs of N-channel transistors which have their source tied

to GNDD. Inactive state is open circuit.

SD0-2 System Drive Outputs

are “Totempole“ CMOS output s switching between GNDD and V

. Inactive

state is logic low.

ANUL Auto Nul l

Negative power supply (-5V).

Voice Transmit is the analog input to the transmit filter.

is used to integrate an internal auto-null signal. A 0.1µF capacitor must be connected

between this pin and GNDA.

Voice Receive is the analog output of the receive filter.

GNDA Analog ground (0V).

Vo ltag e Reference input to D to A converter.

Ref

GNDD Digital grou nd (0V ).

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ISO

-CMOS MT8960/61/62/63/64/65/66/67

MT8960/62

Digital Ou tput

11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000

10000000 00000000 00010000

00100000 00110000 01000000 01010000 01100000 01110000 01111111

Bit 7... 0 MSB LSB

-2.415V -1.207V 0V +1.207V +2.415V Analog Input Voltage (V

)

MT8964/66

Digital Output

10000000 10001111 10011111 10101111 10111111 11001111 11011111 11101111

11111111 01111111 01101111

01011111 01001111 00111111 00101111 00011111 00001111 00000000

Figure 3 - µ-Law Encoder Transfer Characteristic

MT8961/63

Digital Ou tput

11111111 11110000 11100000 11010000 11000000 10110000 10100000 10010000

10000000 00000000 00010000

00100000 00110000 01000000 01010000 01100000 01110000 01111111

-2.5V -1. 25 V 0V

+1.25V

MT8965/67

Digital Output

+2.5 V

1010 1010 1010 0101 1011 0101 1000 0101 1001 0101 1110 0101 1111 0101 1100 0101

1101 0101 0101 0101 0100 0101

0111 0101 0110 0101 0001 0101 0000 0101 0011 0101 0010 0101 0010 1010

Bit 7... 0 MSB LSB

Analog Input Voltage (V

)

Figure 4 - A-L aw E ncod er Transfer Char ac teristi c

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MT8960/61/62/63/64/65/66/67 ISO

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Functional Description

Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at V 8kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM encoding laws. Analog signals in the receive path leave the chip at V words.

Separate switched capacitor filt er sections are used for bandlimiting prior to digital encoding in the transmit path and after digital decoding in the receive path. All filter clocks are derived f rom the 2.048 MHz master clock input, C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A successive approximation technique is used with capacitor arrays t o define the 16 steps and 8 chords in the signal conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo pins, respectively.

after reconstruction from digital 8-bit

, are sampled at

are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above.

The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor ar ray, or alternatively, into an external capacitive load of 250 pF when the c hip is in the test mode. The digital encoder generates an eight-bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB) and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value. Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3 specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code corresponding to the analog voltage, V input.

The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bit s of the 125 µs sampling frame.

, at V

Tra n smit Path

Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz. This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at 8 kHz completes the transmit filter pat h. Accumulated DC offset is cancelled in this last section by a switched-capacitor auto-zero loop which integrates the sign bit of th e encoded PCM word, fed back from the codec and injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between 0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA).

The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by means of three binary controlled gain pads.

Receive P ath

An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz sample and hold circuit integrates this charge and holds it for the rest of the sampling period.

The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and sm oothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The absolute gain of the receive f ilter can be adjusted from 0 dB to

-7 dB in 1 dB steps by means of three binary controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and AT & T recommended specifications.

The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended specifications. Typical atttenuations

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Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits.

ISO

-CMOS MT8960/61/62/63/64/65/66/67

Ref

An external voltage must be supplied to the V

Ref

pin which provides the reference voltage for the digital encoding and decoding of the analog signal. For V

= 2.5V, the digital encode decision value for

Ref

overload (maximum analog signal detect level) is equal to an analog input V

= 2.415V (µ-Law

version) or 2.5V (A-Law version) and is equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the cod ec .

The analog output voltage from the decoder at V

defined as:

µ-Law:

Ref

-0.5 2

[( 128 )+( 128 )( 33 )]

16.5 + S

OFFSET

A-Law: 2

Ref

C+1

0.5 + S

[( 128 )( 32 )]

16.5 + S

[( 128 )( 32 )]

OFFSET

C=0

C≠0

driving a large number of codecs due to the high input impedance of the V

input. Normal

Ref

precautions should be taken in PCB layout design to minimize noise coupling to this pin. A 0.1 µF capacitor connected from V

to ground and located

Ref

as close as possible to the codec is recommended to minimize noise entering through V

. This capacitor

Ref

should have good high frequency characteristics.

Timing

The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive digital output at DSTo (which is a three-state output driver) will then change from a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next positive edge, when the next most significant bit will be output.

On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or V into the input shift register as the sign bit of the incoming PCM word.

edge of C2i af ter F1i has gone low. The

) the logic signal present at DSTi will be clocked

where C = chord number (0-7)

S = step number (0-15)

is a high impedance input with a varying

Ref

capacitive load of up to 40 pF.

The recommended reference volt age for the MT8960 series of codecs is 2.5V ±0.5%. The output voltage from the reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog Devices ’AD1403A voltage reference circuit is capable of

NC NC NC

5678

AD1403A

1234

The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i.

F1i

must ret urn to a high level after the eighth

clock pulse causing DSTo to enter high impedance

preven ti ng fur th e r input da ta to DS Ti. F1i will

and continue to be sampled on every positive edge of C2i. (Note: F1i

may subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs usually mid-frame, in conjunction with CA=V

, in order to enter an 8-bit

control word into Re g iste r B. In this case , PC M i n p ut and output are inhibited by CA at V

Ref

0.1 µF

MT8960-67

FILTER/CODEC

+5V

2.5V

Figure 5 - Typical Voltage Reference Circ uit

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MT8960/61/62/63/64/65/66/67 ISO

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Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog signal thus decoded will be updated 25 µs from the start of the c ycle. After this the analog input from the filter is sample d for 18 µs, after wh ich digital conversion takes place during the remaining 82 µs of the sampling cycle.

Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo, therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid for only 3.9 µs.

Digital Control Functions

CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input (F1i

) (see Table 1).

Mode 1

CA= -5 V (VEE); CSTi=0V (GNDD)

Mode 2

CA= -5V (VEE); CSTi receives an eight-bit control word

CSTi accepts a serial data stream synchronously with DSTi (i.e ., it accept s an eight-b it serial wo rd in a

3.9 µs timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control word is entered into Control Register A and enables programming of the following functions: transmit and receive gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes cannot be entered.

Mode 3

CA=0V (GNDD); CSTi receives an eight-bit control word

As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode, however, Register B is not reset, thus not affecting the states of the SD outputs.

The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their active states and the test modes cannot be entered.

CA = -5V (V

A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, VR is connected to GNDA and all analog sections have power r em o ve d.

MODE CA CSTi FUNCTION

(Note 1)

(Note 2)

); CSTi = +5V (VDD)

GNDD Serial Eight-bit control word int o registe r A. Register B is unaffected.

GNDD Norm al chip operation.

Serial Eight-bit control word into Register A. Register B is reset.

Data

Serial Eight -bit control word int o registe r A. Register B is unaffected.

Data

Powerdown.

CA=+5V (V

In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM data is inhibited.

The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0SD3, on MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip.

); CSTi receives an 8-bit control word

Note 1: When operating in Mode 1, there should be only one frame pulse (F1i Note 2: When operating in Mode 3, PCM input and output is inhibited by CA=V

Table 1. Digi ta l Con tr ol M o des

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) per 125 µ s fra me

ISO

-CMOS MT8960/61/62/63/64/65/66/67

Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low f or two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or V high (V

, and in the second period CA must be

DD)

Control Registers A, B

BIT 2 BIT 1 BIT 0

FILTER GAIN (dB)

000 0 001 + 1 010 + 2 011 + 3 100 + 4

TRANSMIT (A/D)

The contents of these registers control the filter/ codec functions as described in Tables 2 and 3.

Bit 7 of the registers is the M SB and is defined as the first bit of the serial data stream input (corresponding to the sign bit of the PCM word).

On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During this time it is impossible to change the data in these registers.

Chip Testing

By enabling Register B with valid data (eight-bit control wor d in put to CSTi when F1i

) the chip testing mode can be entered. Bits 6

=GNDD and CA=

and 7 (most sign bits) define states for testing the transmit filter, receive filter and the codec function. The input in each case is V each case is V

output. (See Table 3 for details.)

input and the output in

Loopback

101 + 5 110 + 6 111 + 7

RECEIVE (D/A)

BIT 5 BIT 4 BIT 3

FILTER GAIN (dB)

000 0 001 - 1 010 - 2 011 - 3 100 - 4 101 - 5 110 - 6 111 - 7

BIT 7 BIT 6 FUNCTION CONTRO L

0 0 Normal operation 0 1 Digital Loopback

Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits) provide either a digital or analog loopback condition. Digital loopback is defined as follows:

• PCM input da ta at DS Ti is latche d in to the P CM input regis ter an d the out put of this regis ter is connected to the input of the 3-state PCM output regist er.

• The digital input to the PCM digital-to-analog decoder is d isco nnect ed, for ced to ze ro (0).

• The outpu t of the PCM encoder is di sabled and thus the encoded data is lost . The PCM output at DSTo is determined by the PCM input data.

Analog loopback is defined as follows:

• PCM input data is latched, decoded and filtered as normal but not outp ut at V

1 0 Analog Loopback 1 1 Powerdown

Table 2. Con trol S tates - R eg ister A

• Analog o ut put buffer at V

has its input sh orted

to GNDA an d discon nec ted from the rec eive filter output.

• Analog inp ut at V

is disconnec ted f rom the

transmit filter input.

• The receive filter output is connected to the transmit fi lter inp ut. Th us the deco de sign al is fed back th rough the rec ei ve path and en c od ed in the normal way. The analog outp ut bu ffer at

is not tested by this configuration.

In both cases of loopback, DSTi

is the input

and DSTo is the output.

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