MITEL MT8950AC Datasheet



ISO-CMOS ST- B US FAMILY

MT8950

Data Codec

Features

• Transparent cod ing an d de codin g of 0 to 8 , 9. 6 and 19.2 k bps dat a

• Coding com pat ible to PCM voice c hann els at 56/64 kbps in ST-BUS format

• Automatic li ne pol arity det ec tion an d corre ction

• Loopback facility for test purposes

• Selectable data formats: RZ or NRZ

• Eight us e r s el ect able modes of operation

• Low power IS O-CM OS te chnol ogy

Applications

• Transparent cod er/dec oder fo r sync hrono us and async hrono us da ta

• Data terminal (RS-23 2C , etc.) to ST-BUS inter fac e

• Data switching on digital PBXs

• Channel banks/TD M m u lti ple x ers

ISSUE 4 November 1990

Ordering Information

MT8950AC 24 Pin Ce r am i c D IP

0°C to 70°C

Description

The MT8950 is a coder/decoder which uses the Transition Encoded Modulation (TEM) technique for encoding/decoding low speed data to and from a 56/ 64 kbps channel (equivalent to PCM Voice). The coding and decoding scheme is transparent and can accept either synchronous or asynchronous data up to 8 kbps (inclusive); at 9.6 kbps and 19.2 kbps.

The MT8950 is fabricated in MITEL’s ISO-CMOS technology.

SCLK

DR1

RxE

NRZo

SPi

Enable

Logic

NRZ/RZ

Output

Circuit

Timing

& Mode

Control

NRZ/RZ

Input

Circuit

Control

PRST

Decoder

Encoder

Monitoring

Interface

ST-BUS

Interface

C2i F1i CA

DSTi

DSTo

CSTi

SPo

Figure 1 - Functional Block Diagram

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MT8950 ISO-CMOS

CSTi DSTi

C2i

DSTo

F1i CA

DF RxE DX1 DX2

NRZo

VSS

1 2

3 4

5 6

7 8

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

VDD NC PRST NC NC DR1 DR2 DA SPo SPi DP SCLK

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1CSTiControl ST-BUS In (TTL Input) - This ST-BUS interface pin accept s a serial input

stream which loads th e Control Register. The mode of operation of the device, the bits in the Violation word, and, the resetting of Data Activity (DA Scan Point output (SPo are updated once every ST-BUS frame when the interface is enabled.

) are controlled by this register. The contents of the register

) and

2DSTiData ST-BUS I n (TT L Input) - Accepts the 8 bits of TEM Data when the ST-BUS

interface is enabled. 3C2i2.048 MHz Clock (TTL Input) - This is the input for the 2.048 MHz clock. 4 DSTo ST-BUS Output (Three-State Output) - This is the 2.048 Mbps serial output for

theTEM encoded word. It is enabled when both F1i 5F1i

Framing Type 1 Input (TTL Input) - This active low input, in conjunction with CA,

and CA are low.

enables the ST-BUS interface (DSTi, DSTo and CSTi). It is internally sampled on

every positive edge of the C2i clock and provides frame synchronization. 6CA

Control Address (TTL Input) - This active low input (in conjunction with F1i)

enables the ST-BUS interfa c e. 7DFData Format Select (CMOS In pu t ) - When HIGH, the Data Code c accepts and

delivers the data in unipolar Return to Zero (RZ) format. When LOW, the data

format is unipolar NRZ. 8RxE

1Data Transmit 1 (Schmitt Input) - If DF= LOW , accepts data in the NRZ format.

Received Energy Signal (Schmitt Input) - When RxE goes LOW it establishes the

polarity of the input pins D

last pulse before RxE

also enables the operation of DA

and 6) of the codec, RxE

condition. RxE

should be exerted LOW for the duration of a data call.

1 and DX2 in the RZ mode. The input which received the

goes LOW is established as the unipolar MARK input. RxE

and SPo outputs the loopback modes (Modes 4, 5

is forced to the LOW state internally independent of the pin

(HIGH = MARK, LOW = SPACE).

If DF=HIGH, accep ts active low unip olar pulses re presenting the dig ita l data in t he

RZ format. MARK or SPACE polarity is established by the RxE

input.

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ISO-CMOS MT8950

Pin Description (continued)

Pin # Name Description

10 DX2 Data Transmit 2 (Schmitt Input) - If DF = LOW, accepts data puls es which are

encoded only if there is no activity on the D restrictions on the use of this input is explained in the t ext. If DF= HIGH, accepts active low unipolar pulses representing the digital dat a in the RZ format. MARK or SPACE polarity is established by the RxE

1 pin - the data format and

input.

11 NRZo

Non-Return to Zero Output (Open Drain Outpu t) - The incoming data, in the RZ format or the NRZ format , is internally converted to inverted NRZ and appears on this open drain output. This output in conjunction with the SPi input can be used for long space detection.

12 V

Ground (0 V olt).

13 SCLK Secondary Clock (TTL Input) - This is an external clock input that determine s the

timing of the Violation Word and the synchronization pul se s. If these features are not to be utilized, this input can be tied to V

14 DP Drive Point Output (To tem -po le Outpu t) - This output is exerted high when the

Control Register bits b7, b6 and b5 are set to 110 (decimal 6). The operation of the Codec is normal in every other respect.

15 SPi Uncommitted Scan Point Input (V o ltage Comparator Input ) - A LOW to HIGH

16 SPo

transition on this input causes SPo SPACE condition in conjunction with NRZo

Uncommitted Scan Point Output (Totem-pole Output ) - This output is set LOW when the SPi input undergoes a LOW to HIGH transition. T h e SPo

to be set LOW. T his is used to detect a long

(pin 11).

is reset by the

presence of a logic "1" in bit b0 of Co ntrol Register. This function is active at all

17 DA

times except when RxE Data Activity (Totem-pole Ou tput ) - The NRZ/RZ input circuitry monito rs the

is false and during power reset conditions.

input signal (after polarity is established) and activates this output when it detects a SPA CE on the input. This output is reset by the presence of a logic "1" in bit 1 of the Control Register. The DA

function is active at all times except when RxE is false and

during power reset conditions.

18 D

2 Data Receive 2 (Totem-pole Output) - If DF = LOW ( NRZ form at ), outputs th e

secondary data signal in the NRZ form as explained in the text. If DF = HIGH (RZ format), outputs unipolar, active high MARK pulses.

19 D

1 Data Receive 1 (Totem-pole Output) - If DF = LOW (NRZ format) , outputs the

NRZ data signal. ( HIGH = MARK, LOW = SPACE)

If DF = HIGH (RZ format), outputs unipolar, active low SPACE pulses. 20 NC No connecti on . 21 NC No connecti on . 22 PRST

Power Reset (CMOS Schmitt Input ) - A LOW level on this input evokes the power

reset condition for the cod ec. 23 NC No connecti on . 24 V

Positi ve Sup pl y Voltage +5 volts ± 10% .

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MT8950 ISO-CMOS

Theory of Operation

The MT8950 is an encoder/decoder which operates on low baud rate data (up to 19.2 kbps) to convert it to the ST-BUS format. The data can subsequently be transparently switched or transm itted in a manner identical to PCM encoded voice. In this respect, the functional characteristics of the device are very similar to many industry standard voice codecs. Asynchronous and synchronous data from 0 to 8 kbps and at 9.6 kbps is accepted by the codec without any restrictions. Asynchronous data at 19.2 kbps should have at least two s top bits for the device to encode it properly. The data is encoded by the Codec into an eight bit word which occupies one 64 kbps channel on the ST-BUS. Conversely, it accepts an encoded 8 bit word from an incoming ST-BUS stream and regenerates the original digital signal. Mitel’s ST-BUS is a synchronous time division multiplexed serial stream with a bit rate of 2048 kbps. In a telecommunications environment, it is generally divided into 32 channels made up of 8 bits each, with an effective bandwidth of 64 kbps per channel. These channels may carry data or PCM encoded voice.

Low S pee d Da ta For ma t

The Data Codec can accept low speed data in eit her Non Return to Zero (NRZ) or Return to Zero (RZ) format. The NRZ format requires only one line to carry the data. This format is suitable for interfacing the data codec with RS-232 type terminals and microprocessor peripherals such as UARTS, ACIAs, etc. All signals have to be converted to TTL voltage levels before being input to the codec.

The RZ format requires two separate lines to represent the MARKs and SPACEs in the data as illustrated in Figure 4. This format is useful when the data terminal is located some distance from the codec and the data is to be transmitted over a line as a three level signal (a positive pulse for the beginning of MARKs, negative pulse for the beginning of SPACEs and zero level for no change in the signal). The three level signal is converted to its TTL-Compatible binary form as shown in Figure 4 before being applied to the codec. A pulse appears on one line of the input indicating the beginning of MARKs. This is followed by a pulse on the second line indicating the beginning of SPACEs. If two or more pulses appear consecutively on the same line before the second line of the pair receives or transmits another pulse, then these pulses can be considered to be v iolating the normal rule of the RZ format and are called "Violation Pulses". The data codec will accept these violations with the restriction that the time differenc e between a violation pulse

Data Rate

Bits/Sec

Asynchronous

Restrictions

Synchronous

Restrictions

Percentage

Distortion

†

0 - 80 00 9600 19200

None None Minimum

2 Stop Bits

None None None

±3.2 ±3.8 ±7.5

Table 1. Summary of Data Codec Capabilities.

† Refers to the maximum distortion in the bit period timing of the regenerated data. (Channel Bandwidth = 64kbps )

Percentage Distortion = |T where TBO = Origi na l Da ta Bi t Pe rio d

= Regenerated Data Bit Period

- T

| / T

X 100

and an actual data transition be at least 125µs. The violation pulses can be on the MARK or SPACE line. In a communications system, these violat ions can be used to carry other information when no data is being transmitted.

Encoding/Decoding Scheme

The Data Codec uses a Transition Encoded Modulation (TEM) technique to encode low speed data onto a 56 or 64 kbps equivalent PCM voice channel. This coding algorithm significantly reduces data bit distortion. The timing distortion in the regenerated data is summarized in Table 1. A simple sampling method for encoding the data would require a 256 kbps channel to obtain the same low distortion figures.

If the encoded information is to be transmitted over digital T1/DS1 trunks, the maximum percentage distortion in the regenerated data is effectively doubled. This is due to the fact that the least significant bit in specific channels on these trunks is used to transmit signalling information. Thus the bandwidth per channel is reduced to 56 kbps.

The encoder stage of the Data Codec observes data transitions in discrete timing windows which are 125µs wide. These timing frames are further divided into 32 timeslots of 3.906µs duration each (see Figure 3). The position of the first data transition, the total number of transitions, and, the time period between the transitions in this 125µs frame is encoded as an 8 bit word.

The first five bits (b0 to b4) indicate the position of the first data transition with respect to the 32 timeslots in the window. Bit 7 in the encoded word represents the absolute value of the data in the 31st timeslot. Bits 5 and 6 in conjunction with bit 7 are used to identify the total number of transitions and the time period between the transitions. Due to the fixed bit rate restrictions above 8 kbps, a maximum

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Internal Clock

ISO-CMOS MT8950

125 µs

0123456789

-1

b4b3b2b1b

01234 01234567

b1b

b4b3b2b1b

22• • •

b4b3b2b1b

Figure 3 - TEM Coding Scheme

(Note: Wavef orm s s ho w n ar e bi po la r RZ equiva le nt of s eparate R Z/ N RZ inputs)

24 25 26 27 28 29 30

b4b3b2b1b0=11111

b4b3b

023

Frame Type

Frame

Description

Level

†

Frame Type

b6 b5

First Transition

b4 b3 b2 b1 b0

Notes

1 No Pul se 1/0 1 1 1 1 1 1 1 2 2 Data Pulses (T =52 µs ) 1/0 1 1 X X X X X X X X X X ≤ 10001 (17) 3 3 Data Pulses (T =52 µs ) 1/0 1 1 X X X X X X X X X X ≤ 00100 (4) 4 1 Data P u lse 1/0 1 0 X X X X X X X X X X = 0 to 31 5 Violat io n Pulse 1/0 1 0 X X X X X X X X X X = 0 to 31 6 2 Data Pulses (T=104 µs)

1/0 0 1 X X X X X X X X X X > 00011 (3)

(Timeslot 4 to 31)

7 2 Data Pulses (T=104 µs)

(Timeslot 0 to 3)

1/0 0 0 Y Y Y X X XX = 0 to 3

YYY = 0 to 7

Table 2. TEM Coding Summary

† Note: The Level bit (b7) indicates the level (HIGH or LOW) of the input data in timeslot 31 of the current frame.

of seven frames types are possible as shown in Figure 3. In frame t ype 7, th e fi rs t five bits (b0 to b 4 ) are used to represent two transitions instead of the normal first transition. Not e that the data transitions in Figure 3 are shown as a three level signal. A positive transition indicates the beginning of one or more continuous MARKs and a negative transition indicates the beginning of one or more continuous SPACEs.

The decoder stage regenerates the original data from the 8 b i t T EM word. T h e a bs o lute values of th e data signal in the present and previous frames as given by b7(n) and b7(n-1) are EX-ORed and the result in combination with the remaining bits of the TEM word is us ed to reproduce the original data with an accuracy of ± 3.906µs (see Table 2). Due to the data speed restriction above 8 kbps, the second and third transitions (if any) will be reproduced at

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