MITEL MT8941AE, MT8941AP Datasheet

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CMOS ST-BUS FAMILY

MT8941

Advanced T1/CEPT Digital Trunk PLL

Features

• Provides T1 clock a t 1 .544 MHz locked to an 8 kHz reference clock (frame pulse)

• Provides CEPT clo ck at 2.04 8 MHz and S TBUS clock and tim ing si gnal s lock ed to a n internal or external 8 kHz reference clock

• Typical inherent ou tput jitt er (unfil tered )= 0.07 UI peak-to-p eak

•Typical j itter attenu atio n at: 10 Hz=2 3 dB ,100 Hz=43 dB, 5 to 40 kH z ≥ 64 dB

• Jitter-free “FRE E-RUN” mode

• Uncommitted two-input NAND gate

• Low power CM OS tech nolog y

Applications

• Synchronization and timing control for T1 and CEPT digi tal trun k tran smissi on lin ks

• ST- BUS clock and f rame pulse s ourc e

ISSUE 5 July 1993

Ordering Information

MT8941AE 24 Pin Plastic DIP MT8941AP 28 Pin PLCC

-40°C to + 85°C

Descript io n

The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS. The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz. The timing sign a l s fo r the CEPT transmi ss i on l i nk and th e ST-BUS are provided by the second PLL locked to an internal or an external 8 kHz frame pulse signal.

The MT8941 offers improved jitter performance over the MT8940. functional differences, which are listed in the section on “Differences between MT8941 and MT8940”.

The two devices also have some

F0i

C12i

MS0 MS1 MS2 MS3

C8Kb

C16i

DPLL #1

2:1 MUX

Mode

Selection

Logic

DPLL #2

Ai Bi

Yo V

Input

Selector

Clock

Generator

RST

Variable

Clock

Control

Frame Pulse

Control

4.096 MHz Clock

Control

2.048 MHz

Clock

Control

CVb CV ENCV

F0b

C4b C4o ENC4o

C2o C2o ENC2o

Figure 1 - Functional Block Diagram

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MT8941 CMOS

F0i

F0b

1 2

3 4

5 6

7 8

9 10 11 12

ENVC

MS0 C12i MS1

MS2 C16i

ENC4o

C8Kb

C4o

VSS

Pin Description

24 23 22 21 20 19 18 17 16 15 14 13

VDD RST CV CVb Yo Bi Ai MS3 ENC2o C2o C2o C4b

Figure 2 - Pin Connections

MS1

F0b MS2 C16i

ENC4o

5 6

7 8 9 10 11

28 PIN PLCC24 PIN PDIP

S M

•

S S V

CVb

23 22

MS3

ENC2o

C N

Pin #

Name Description

DIP PLCC

11ENCVVariable clock enable (TTL compatible input) - This input directly controls the three states

of CV (pin 22) under all modes of operation. When HIGH, enables CV

and when LOW, puts it in high impedance condition. It also controls the three states of CV b signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.

22MS0Mode sel ect ‘0’ input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects

the major mode of operati on for bot h DPLLs. (Refer to Tabl es 1 and 2.)

33C12i12.352 MHz Clock input (TTL com pa tible) - Master clock input for DPLL #1. 46MS1Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects

the major mode of operati on for bot h DPLLs. (Refer to Tabl es 1 and 2.)

57 F0i

Frame pu lse inp ut (TTL com pati ble) - This is the frame pulse input at 8 kHz. DPLL #1 locks to the falling edge of this input to generate T1 (1.544 MHz) cloc k.

68F0b

Frame pu lse Bi directi on al (TT L comp atib le inp ut and Totem-pole outp ut) - Depending on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as an input to an external frame pulse.

79MS2Mode se l ec t -2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects

the minor mode of operati on for DP LL #2. (Refer to Table 3.)

810C16i16.384 MHz Clock input (TTL compa tibl e) - Master clock input for DPLL #2. 911EN

Enable 4.096 MHz clock (TTL comp atib le input) - This active high input enables C4o (pin

C4o

11) output. When LOW, the output C4o is in high impedance condition .

10 12 C8K b Clock 8 kHz Bidirectional (TTL com pati ble input and Totem-pole output) - This is the 8

kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mo de. When DPLL #2 is in SINGLE CLO CK mode, this pin output s an 8 kHz internal signal provided by DPLL #1 which is also connected internally to DPLL #2.

11 13 C4o Clock 4.096 MH z (Three state outp ut) - This is the inverse of the signal appearing on pin

13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b

) window. The high

impedance state of this out put is cont rolled by ENC 4o (pi n 9).

12 14 V

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Ground (0 Volt)

Pin Description (continued)

CMOS MT8941

Pin #

Name Description

DIP PLCC

13 15 C4b Clock 4.096 M Hz - Bidirecti ona l (TTL comp atib le inpu t and Totem-pole outpu t) - When

the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the falling edge in the frame pulse (F0b

) window. When pin 17 is LOW, C4b is an input to an

external clock at 4.096 MHz.

14 16 C2o

15 17 C2o Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b

16 19 EN

Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and has a falling edge in the frame pulse (F0b is controlled by EN

C2o

(pin 16).

) window. The high impedance state of this output

(pin 13) and has a rising edge in the frame pulse (F0b controlled by EN

Enable 2.048 MHz clock (TTL compatible input) - This active high inp ut enables both C2o

C2o

(pin 16).

) window. The high impedance state of this output is

and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance condition.

17 20 MS3 Mode select 3 inpu t (TTL com pati ble) - This input in conjunction with MS2 (pin 7) selects

the minor mode of operation for DP LL #2. (Ref er to Table 3.)

18,1921,22Ai, Bi Inputs A and B (TTL compa tib le) -These are the two inputs of the uncomm itted NAND

gate

20 23 Y

Output Y (Totem pole output) - Output of the uncommitted NAND gate.

21 24 CVb Variable clock Bidirecti on al (TTL comp atib l e input and Totem-pole output) - When

acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the

1.544 MHz clock locked to the input frame pulse F0i

(pin 5). When MS1 is HIGH, it is an input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz to DPLL #2.

22 26 CV

23 27 RST

24 28 V

DDVDD

NC No Connection.

5, 18, 25

Variable clock (Three state output) - This is the inverse output of the signal appearing on pin 21, the high impedance state of which is control led by EN

(pin 1).

Reset (S chmitt trigger input) - This input (active LOW) puts the MT8941 in its reset state. To guarantee proper operation , the device must be reset afte r power-up. The time constant for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time of the power supply. In normal operation , the RST

pin must be held low for a minimum of

60nsec to reset the device.

(+5V) Power supply .

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MT8941 CMOS

Functional Description

The MT8941 is a dual digital phase-locked loop providing the timing and synchronization signals to the interface circuits for T1 and CEPT (30+2) Primary Multiplex Digital Transmission links. As shown in the functional block diagram (see Figure 1), the MT8941 has two digital phase-locked loops (DPLLs), associated output controls and the mode selection logic circuits. The two DPLLs, although similar in principle, operate independently to provide T1 (1.544 MHz) and CEPT (2.048 MHz) transmission clocks and ST-BUS timing signals.

The principle of operation behind the two DPLLs is shown in Figure 3. A master clock is divided down to 8 kHz where it is compared with the 8 kHz input, and depending on the output of the phase comparison, the master clock frequency is corrected.

Master clock

(12.352 MHz /

16.384 MHz)

Input (8 kHz)

The MT8941 achieves the frequency correction in both directions by using three methods; speed-up, slow-down and no-correction.

As shown in Figure 4, the falling edge of the 8 kHz input signal (C8Kb for DPLL #2 or F0i is used to sample the internally generated 8 kHz clock and the correction signal (CS) once in every frame (125 µs). If the sampled CS is “1”, then the DPLL makes a speed-up or slow-down correction depending upon the sampled value of the internal 8 kHz signal. A sampled ”0” or “1” causes the frequency correction circuit to respectively stretch or shrink the master clock by half a period at one instant in the frame. If the sampled CS is “0”, then the DPLL makes no correction on the master clock input. Note that since the internal 8 kHz signal and the CS signal are derived from the master clock, a correction will cause both clocks to stretch or shrink simultaneously by an amount equal to half the period of the master clock.

Once in synchronization, the falling edge of the reference signal (C8Kb or F0i) will be aligned with either the falling or the rising edge of CS. It is aligned with the rising edge of CS when the reference signal is slower than the int ernal 8 kHz signal. On the other hand, the falling edge of the

Frequency Correction

Phase

Comparison

÷ 8

÷ 193 /

÷ 256

Figure 3 - DPLL Principle

for DPLL # 1)

Output

(1.544 MHz /

2.048 MHz)

C8Kb (DPLL #2)

(DPLL #1)

or F0i

Interna 8 kHz

correction

F0b (DPLL #2)

DPLL #1: DPLL #2:

where, T for DPLL #1 and T for DPLL #2.

speed-up

region

= 4 × T

tCS = 512 × T t

CSF

is the 12.352 MHz master clock oscillator period

P12

no-correction

± 0.5 × T

P12

± 0.5 × T

= 766 × T

P16

is the 16.384 MHz master clock period

P16

sampling edge

correction

CSF

P12

P16

slow-down

region

Figure 4 - Phas e Com par ison

reference signal will be aligned with the falling edge of CS if the reference signal is faster than the internal 8 kHz signal.

Input-to-Ou tput Ph ase Re lationsh ip

The no-correction window size is 324 ns for DPLL #1 and 32 µs for DPLL #2. It is possib le for the relative phase of the reference signal to swing inside the nocorrection window depending on its jitter and the relative drift of the master clock. As a result, the phase relationship between the input signal and the output clocks (and frame pulse in case of DPLL #2) may vary up to a maximum of window size. This situation is illustrated in Figure 4. The maximum phase variation for DPLL #1 is 324 ns and for DPLL #2 it is 32µs. However, this phase difference can be absorbed by the input jitter buffer of Mitel’s T1/CEPT devices.

The no-correction window acts as a filter for low frequency jitter and wander s ince the DPLL does not track the reference signal inside it. The size of the no-correction window is less than or equal to the size of the input jitter buffer on the T1 and CEPT devices to guarantee that no slip will occur in the received T1/CEPT fra m e .

The circuit will remain in synchronization as long as the input frequency is wit hin the lock-in range of the DPLLs (refer to the section on “Jitter Performance and Lock-in Range” for further details). The lock-in range is wide enough to meet the CCITT line rate specification (1.544 MHz ±32 ppm and 2.048 MHz ±50 ppm) for the High Capacity Terrestrial Digital Service.

The phase sampling is done once in a frame (8 kHz) for each DPLL. The divisions are set at 8 and 193 for DPLL #1, which locks to the falling edge of the input

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CMOS MT8941

at 8 kHz to generate T1 (1.544 MHz) clock. For DPLL #2, the divisions are set at 8 and 256 to provide the CEPT/ST-BUS clock at 2.048 MHz synchronized t o the falling edge of the input signal (8 kHz). The master clock source is specified to be

12.352 MHz for DPLL #1 and 16.384 MHz for DPLL #2 over the entire temperature range of operation.

The inputs MS0 to MS3 are used to select the operating mode of the MT8941, see Tables 1 to 4. All the outputs are controlled to the high impedance condition by their respective enable controls. The uncommitted NAND gate is available for use in applications involving Mitel’s M T8976/ MH89760 (T1 Interfaces) and MT8979/MH89790 (CEPT Interfaces).

Modes of Operat ion

The operation of the MT8941 is categorized into major modes and minor modes. The major modes are defined for both DPLLs by the mode select pins MS0 and MS1. The minor modes are selected by pins MS2 and MS3 and are applicable only to DPLL #2. There are no minor m odes for DPLL #1.

Major modes of DPLL #1

DPLL #1 can be operated in three major modes as selected by MS0 and MS1 (Table 1). When MS1 is LOW, it is in NORMAL mode, which provides a T1 (1.544 MHz) clock signal locked to the falling edge of the input frame pulse F0i requires a master clock input of 12.352 MHz (C12i). In the second and third major modes (MS1 is HIGH), DPLL #1 is set to DIVIDE an external 1.544 MHz or

2.048 MHz signal applied at CVb (pin 21). The division can be set by MS0 to be either 193 (LOW) or 256 (HIGH). In these modes, the 8 kHz output at C8Kb is connected internally to DPLL #2, which operates in SINGLE CLOCK mode.

Major modes of DPLL #2

There are four major modes for DPLL #2 selectable by MS0 and M S1, as s hown in Table 2. In all these modes DPLL #2 provides the CEPT PCM30 timing, and the ST-BUS clock and framing signals.

In NORMAL mode, DPLL #2 provides the CEPT/STBUS compatible timing signals loc ked to the falling edge of the 8 kHz input signal (C8Kb). These signals are 4.096 MHz (C4o and C4b MHz (C2o and C2o pulse (F0b

) derived from the 16.384 MHz master

) clocks, and the 8 kHz frame

clock. This mode can be the same as the FREERUN mode if the C8Kb pin is tied to V

(8 kHz). DPLL #1

) and 2.048

or VSS.

Mode of

Operation

Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i).

DPLL #1 divides the CVb input by

193. The divided output is connected to DPLL #2.

DPLL #1 divides the CVb input by

256. The divided output is connected to DPLL #2.

S 0

X 0 NORMAL

0 1 DIVIDE-1

1 1 DIVIDE-2

Note: X: indicates don’t care

Function

Table 1. Major Modes of DPLL # 1

S 1

Mode of

Operation

SINGLE

CLOCK-1

SINGLE

CLOCK-2

S 0

0 0 NORMAL

1 0 FREE-RUN

Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz input signal at C8Kb.

Provides CEPT/ST-BUS timing and framing signals with no external inputs, except the master clock.

Provides CEPT/ST-BUS timing signals locked to the falling edge of the 8 kHz internal signal provided by DPLL #1.

Function

Table 2. M ajor M odes of DP LL #2

Provides CEPT/ST-BUS 4.096 MHz and 2.048 MHz clocks and 8kHz frame pulse dependi n g on the major mode selected.

Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz clocks depending on the major mode selected while F0b F0b

has no effect on the operation of DPLL #2

unless it is in FREE-RUN mode. Overrides the major mode selected and accepts

properly phase related external 4.096 MHz clock and 8 kHz frame pulse to provide the ST-BUS compatible clock at 2.048 MHz.

Overrides the major mode selected a nd acc epts a

4.096 MHz external clock to provide the ST-BUS clock and frame pulse at 2.048 MHz and 8 kHz, respectively.

Functional Description

acts as an input. However, the input on

Table 3. Minor Modes of DPLL #2

In FREE-RUN mode, DPLL #2 generates the standalone CEPT and ST-BUS timing and framing signals with no external inputs except the master clock set at

16.384 MHz. The DPLL makes no correction in this configurat ion and provides the t iming signals without any jitte r.

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MT8941 CMOS

The operation of DPLL #2 in SINGLE CLOCK-1 mode is identical to SINGLE CLOCK-2 mode, providing the CEPT and ST-BUS compatible timing signals synchro-nized to the internal 8 kHz signal obtained from DPLL#1 in DIVIDE mode. When

10) and DPLL #2 locks to the falling edge to provide the CEPT and ST-BUS compatible timing signals. This is in contrast to the Normal mode where these timing signals are synchronized with the fallin g edge

of the 8 kHz signal on C8Kb. SINGLE CLOCK-1 mode is selected for DPLL #2, it automatically selects the DIVIDE-1 mode for DPLL #1, and thus, an external 1.544 MHz clock signal

Minor modes of DPLL #2

applied at CVb (pin 21) is divided by DPLL #1 to generate the internal signal at 8 kHz on to which DPLL #2 locks. Similarly when SINGLE CLOCK-2 mode is selected, DPLL #1 is in DIVIDE-2 mode,

The minor modes for DPLL #2 depends upon the

status of the mode select bits MS2 and MS3 (pins 7

and 17). with an external signal of 2.048 MHz providing the

internal 8 kHz signal to DPLL #2. In both these modes, this internal signal is available on C8Kb (pin

Mode

0 0000

1 0 0 0 1 NORMAL MODE

2 0010

3 0011 4 0 1 0 0 DIVIDE-1 MODE Same as mode ‘0’.

5 0 1 0 1 DIVIDE-1 MODE 6 0 1 1 0 DIVIDE-1 MODE Same as mode 2.

7 0111 8 1 0 0 0 NORMAL MODE Same as mode ‘0’.

9 1001

10 1 0 1 0 NORMAL MODE Same as mode 2.

11 1011 12 1 1 0 0 DIVIDE-2 MODE Same as mode ‘0’.

13 1101 14 1 1 1 0 DIVIDE-2 MODE Same as mode 2.

15 1111

NORMAL MODE: Provides the T1 (1.544 MHz) clock synchronized to the falling edge of the input frame pulse (F0i

NORMAL MODE

NORMAL MODE NORMAL MODE:

DIVIDE-1 MODE: Divides the CVb input by 193. The divided output is connected to DPLL #2.

NORMAL MODE F0b

NORMAL MODE

DIVIDE-2 MODE SINGLE CLOCK-2 MODE:

DIVIDE-2 MODE: Divides the CVb input by 256. The divided output is connected to DPLL# 2.

DPLL #1 DPLL #2

Operating Modes

Properly phase related External 4.096 MHz clock and 8 kHz frame pulse provide the STBUS clock at 2.048 MHz.

NORMAL MODE:

is an input but has no function in this mode.

F0b External 4.096 MHz provides the ST-BUS clock

and Frame Pulse at 2.048 MHz and 8 kHz, respectively.

Provides the CEPT/ST-BUS compatible timing signals locked to t h e 8 kHz input signal (C8Kb).

SINGLE CLOCK-1 MODE F0b

is an input but has no function in this mode.

SINGLE CLOCK-1 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1.

is an input and DPLL #2 locks on to it only if it is at 16 kHz to provide the ST-BUS control signals.

FREE-RUN MODE: Provides the ST-BUS timing signals with no external inputs except the master clock.

F0b

is an input but has no function in this mode.

SINGLE CLOCK-2 MODE: Provides the CEPT/ST-BUS compatible timing signals locked to the 8 kHz internal signal provided by DPLL #1.

Table 4. Sum mary o f Mo des o f Op eratio n - DP LL #1 and #2

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