MITEL MT8926AE, MT8926AP Datasheet

ISO-CMOS ST-BUS FAMILY



MT8926

T1 Performance Monitoring

Adjunct Circuit (PMAC)

Features

• ANSI T1.403 and T1 .408 Perfo rmance Monitoring and Main t ena nc e Functions

• Operates in c onjun ction wi th Mitel 's T1/ES F framer circu its (M T897 6/77 and MH 89760 B)

• D3/D4 (SF), and ESF modes of operation

• One and two second timers

• Supports bit-oriented and message-oriented data transfe r over the F acility D ata Link (FDL )

• ESF and D3/D4 Yellow Alarms, Alarm Indication Signal an d Loss of Sig nal Indi cati on

• Framing Error, CRC Error and Bipolar Violation Error counters

• Alarm interrup t s and counter overfl ow i nt er r up ts

Applications

• T1 line perfor mance data collect ion

• CSU performa nce monitori ng

• ISDN Primary Rate maintenance controller

ISSUE 3 July 1993

Ordering Information

MT8926A E 28 Pin Plast ic DIP MT8926A P 28 Pin PLC C

-40°C to 85°C

Description

The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features.

It meets the performance monitoring and maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements.

FDLi E8Ki

IRQ

C2i CSTi0 CSTi1

CSTo

RESET

DSTi0 DSTi1

DSTo

F0i

ST-BUS

Interface

Payload

& Li ne

Loopback

Control

Transmit BOM

Receive BOM Registe r &

RAI Debounce

Snap -

Shot

Registers

8 Bit CRC

Counter

CSI

Timer

Figure 1 - Functional Block Diagram

SEI

FSI

BSI

4 Bit SE Counter

4 Bit FE Counter

8 Bit BPV

Counter

E8K/FDL

Extractor

Framer,

Detector

Loopback Integrator

B8ZS

Recovery,

BPV Detector

AIS/LOS Detector

Mux

FDL

SE/FE

Line

E8Ko

FDLo

RxA RxB ECLK

1SEC

4-3

MT8926

VSS

ECLK

RxA RxB

E8Ki

E8Ko

VSS

CSTo CSTi0 CSTi1

VSS

1 2

3 4 5

6 7 8

9 10 11

F0i

C2i

13 14

28 PIN PLASTIC DIP

28 27 26 25 24 23 22 21 20 19 18 17 16 15

VDD IC DSTi1 DSTi0 DSTo IC VSS IC IRQ 1SEC FDLo FLDi RESET

VDD

E8Ki

E8Ko

VSS

CSTo CSTi0 CSTi1

RxB

432 5

6 7 8

9 10 11

12 13 14 15 16 17 18

28 PIN PLASTIC J-LEAD

F0i

C2i

VSS

VDD

RESET

DSTi1

262728

25 24 23 22 21 20 19

FLDi

FLDo

VSS

ECLK

RxA

DSTi0 DSTo

IC VSS IC IRQ 1SEC

Figure 2 - Pin Connections

Pin Description

Pin # Name Descrip tio n

1V 2ECLKExtracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is

3RxA

4RxB

5ICInternal Connection. Must be tied to V 6E8KiExtracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the

7E8Ko8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn)

8V 9 CSTo Con trol ST-BUS Output. The data that enters the PMAC on CSTi0 will exit th e device on

10 CSTi0 Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the

11 CSTi1 Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control

12 F0i

System Ground.

used to clock in the data on pins RxA

and RxB.

See Figure 11 for timing informati o n. Receive A Input. A unipolar active low signal deco ded from the received T1 signal. See

Figure 11 for timing information. Receive B Input. A unipolar active low signal decoded from the rece ived T1 signal. See

Figure 11 for timing information.

for normal operation.

framing bit in the received signal. The device use s this inform ation t o detect errors in the received framing bits. Connect to E8Ko of the MT8976/ 77. See Figure 12 for timing information.

of the PMAC Control Word is set. The output is pulled high when 8KE n is reset. See Figure 12 for timing informat ion.

System Ground.

this pin. Data derived by the PMAC will be inserted into specific channels of this output stream. See Figures 13 and 14 for timing informati on and Figu re 5 for channel allocation.

MT8976/77. The data tha t ente rs the PMAC on this pin exit s the device on CSTo. The contents of specific CSTi0 channels is replaced by data derived by the PMAC. See Figures 13 and 14 for timing information and Figure 4 for channel allocat ion .

specific features in the device (Table 14). Channel 7 is used for the transmit bit-oriented message (Table 13), and channel 15 is used to control loopback functions (Table 4). See Figure 13 for timing information and Fig ure 3 for channel allocation.

Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the S TBUS frame boundary. See Figure 15 for timing information.

4-4

MT8926

Pin Description (Con t inued)

Pin # Name Descrip tio n

13 C2i 2.048 MHz Clock I nput. This input accepts a 2.048 MHz clock signal, which is used to

clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and

14 for tim i ng in fo rmation. 14 V 15 V

16 RESET

17 FDLi Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit

18 FDLo Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC

19 1SEC 1 Second Output. A one second timing signal derived from the ST-BUS F0i

System Ground.

Supply Voltage Input (+5 V).

RESET Input. Must be high for normal operation. When low, the functions of the

MT8926 will be suspended.

signal, which is routed back out transparently on FDLo if message-oriented signal

transmis sion is enabl ed (i.e., PMAC Co ntrol Word bit 0, FDL En, is low). This s ignal is

not clocked into the PMAC. If bit-oriented messaging is enabled (FDLEn high), data on

this input will not be routed to FDLo (see pin 18, FDLo, below).

Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended

to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing

for this s ignal is shown in Figure 18. When bit-oriented messaging is disabled (FDLEn

low), data received at the FDLi pin is routed back out transparently on this pin (it is not

re-timed). See Figure 19 for timing information.

output on this pin. The output is low for 0.5 seconds and high for 0.5 seconds. It can be

used as an interrupt source to generate T1.403 message-oriented performance reports.

See Figure 16 for t iming information.

signal is

20 IRQ

Interrupt Request Ou tput. An open drain output that is to be externally connected to

through a pull-up resistor. The PMAC will pull this pin low to assert an interrupt

request. Interrupting events and their groupings are described in Tables 16 and 17. IRQ

is released by making bit 1 (Interrupt Acknowledge - INTA) of the PMAC Control Word

low. Once INTA is set, all interrupting signals of a particular group must be inactive

before the next interrupt of that group can assert IRQ

. See Figure 17 for functional

timing information. 21 IC Internal Connection. Must be left open for normal operation. 22 V

System Ground.

23 IC Internal Connection. Must be left open for normal operation. 24 DSTo Data ST-BUS Output. A 2.048 MBit/sec. serial output stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk. This data stream is

multiplexed from either input DSTi0 (Normal Mode) or input DSTi1 (Payload Loopback

Mode). The selection of either the Normal or Payload Loopback mode is made through

the Loopback Control Word. This output should be connected to DSTi of the MT8976/

77. When the loopback control word is set for line loopback code generation, the 24

PCM channels will contain the line loopback activate or deactivate code stream. See

Figure 14 fo r ti mi n g information. 25 DSTi0 Data ST-BUS Input 0. A 2.048 MBit/sec. serial input stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk in Normal Mode. This input

should be connected to the system side output stream. 26 DSTi1 Data ST-BUS Input 1. A 2.048 MBit/sec. serial input stream, which contains the 24

PCM or data channels to be transmitted on the T1 trunk in Payload Loopback Mode.

This input should be connected to DSTo of the MT8976/77. 27 IC Internal Connection. M u st be tied to V 28 V

Supply Voltage Input (+5 V).

for normal operation.

4-5

MT8926

Functional Description

The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1 interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408. Performance data collection includes CRC errors, severely errored framing events, frame synchronization-bit errors, line code violations, and controlled slips. Maintenance functions include the detection of alarms, SF line loopback code generation and detection, ESF payload loopback, as well as the transport of bit-oriented and messageoriented signals over the Facility Data Link (FDL).

The control and status data of the MT8926 is transported over spare channels of the existing MT8976/77 ST-BUS streams. Therefore, no new STBUS streams are required to upgrade with the PMAC.

The PMAC has an on-board framer that uses the received signal and extracted 8 kHz clock to achieve synchronization. The result of this frame alignment is logically ANDed with the SYN bit of the MT8976/77 CSTo stream to give FECV (see Table 5). This will ensure that the PMAC can only declare synchronization after the framer is synchronized. The MT8926 will align to SF or ESF framing without user selection.

An interrupt (IRQ output) system is also provided to reduce the requirement to monitor ST-BUS channels continuously for exception conditions. Interrupt sources are divided into group one (G1) for service affecting events and group two (G2) for counter overflows.

A timer has been included to allow scheduling of T1.403/408 message-oriented performance reports for transmission over the facility data link. This timer

provides a two second output (register accessed) and a one second output pin.

Two eight bit counters with overflow bits and resets (resets counter and overflow bit) are provided to record line code violations (BPV) and CRC errors. The BPV counter will not count B8ZS encoding violations. When either overflow bit goes high it will generate a group two (G2) interrupt.

Two four bit counters are used to record framing error events (FE) and severely errored framing events (SE). The FE counter has an overflow indication bit and can be cleared (resets counter and overflow bit) by the user. Its overflow bit will generate a group two (G2) interrupt when it goes high. A G2 interrupt will also be issued whenever the SE co unter is incremented.

The alarms that the PMAC monitors are alternate SF yellow ala rm (i.e., twelfth SF fr aming bit =1, ALR M), ESF facility data link yellow alarm (RAI), loss of signal (i.e., reception of 128 or more consecutive zeros), and alarm indication signal (AIS, blue alarm or all ones alarm). Theref ore, the MT8926/MT8976/ 77 combination supports a comprehensive alarm package.

The PMAC alarm registers and counters are updated as the corresponding events occur. Once per frame (8000 times a second) the state of these registers and counters is recorded in a set of snap-shot registers. This data in the snap-shot registers is then inserted into the appropriate bit positions of the STBUS status stream CSTo.

FDL bit-oriented messages can be communicated via the PMAC transmit and receive bit-oriented message registers. The user gains access to these register s th rough the S T-BUS co ntro l stre ams. Valid bit-oriented messages consist of a series of

0-2

3X4-6

CSTi1

T1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24

PCCW = Per Channel Control Word

PCCW

Bit

PCCW

Transmit Bit-Oriented Message Register

7 0

Function Transmitted First Transmitted Last

8-10

PCCW

BOM

12-14

PCCW

PMAC Control Word

Bit

7 6 5 4 3 2 1 0

Function

SER FER CRCR BPVR FSel 8KEn INTA FDLEn

15 LC

16-18

PCCW

Bit 1

0 0 1 1

19X20-22

PCCW

Loopback Control

Word

Bit 0

0 1 0 1

Normal Payload Loopback Line Loopback Enable Code (00001) Line Loopback Disable Code (001)

23X24-26

PCCW

Function

FIgure 3 - C STi1 Ch anne l A llo cat ion Versus T1 C han ne ls

4-6

27X28-30

PCCW

MT8926

repeating 16 bit code words of the form: 11111111 0XXXXXX0, where X XXXXX is the message content. The PMAC will automatically append the prefix byte 11111111 to the transmit message and remove it fro m the receive message. It will also indicate the reception of a valid message. When bit-oriented messages are not being transported, messageoriented facility data link signals, assembled by an external HDLC controller (i.e., MT8952), can be passed through the PMAC to the MT8976/77 for transmission.

The PMAC can implement an ESF payload loopback by routing the MT8976/77 DSTo stream to the MT8976/77 DSTi input (see Figure 6). The payload loopback is controlled through the loopback control word, Channel 15 of CSTi1 (see Figure 3). When the payload loopback is disabled, data entering the PMAC’s DSTi0 pin is transferred to the PMAC DSTo. DSTo of the PMAC should be connected to the DSTi pin of the MT8976/77 framer.

PMAC - Framer Interw orking

The MT8926 PMAC is designed to function with the MT8976/77 T1 framer. Figure 9 illustrates a typical application and the connections involved in realizing this interface . Bo th th e P MAC a nd framer receive th e extracted clock and data from the T1 line interface. This allows the MT8926 to perform B8ZS recovery and BPV detection, as well as SF or ESF synchronization, framing error det ection, facility data link extraction, and line loopback code detection.

Some of the CSTi1 channels that are not used to control the MT8976/77 are used to control the PMAC, therefore, CSTi1 will connect to both devices. Figure 3 shows the channels of CSTi1 that carry the MT8976/77 Per Channel Control Words, as well as the MT8926 control dat a. C2i and F0i

supply timing

references for both d e vices.

The CSTo stream of the MT8976/77 framer enters the PMAC on CSTi0 (see Figure 4). The PMAC adds its performance data to form the CSTo stream of the PMAC. Figure 5 shows the channels and status bits that the PMAC has added to CSTo. E8Ko of the

framer will also pass through the PMAC, E8Ki to E8Ko, under control of CSTi1.

It should be noted that the PMAC will replace some of the data of MT8976/77 Master Status Words 1 and

2. This is outlined in Tables 1 and 2.

Bit MT8976/77 CSTo MT8926 CSTo

7 YLALR YLALR 6 MIMIC MIMIC 5 ERR ALRM 4 ESFYLW RAI 3 MFSYNC 2 B PV LOS 1 SLIP SLIP 0SYN

MFSYNC

SYN

Table1. Maste r Status Word 1 Data Su bstitu tion

Bit

7 BlAlm BlAlm 6FrCnt FrCnt 5 Xst Xst 4 BPVCnt SEI 3 BPVCnt FSI 2 CRCCNT CSI 1 CRCCNT BSI 0 CRCCNT AIS

MT8976/77 CSTo MT8926 CSTo

Table 2. Master Stat us Wo rd 2 Data Su b stitution

The MT8926 can be programmed to either pass data through from FDLi to FDLo and on to the MT8976/77 input TxFDL, or insert bit-oriented messages into the FDL via the transmit bit-oriented message register, channel 7 of CSTi1. This function is under control of the FDLEn bit of the PMAC Control Word. See Application section Figure 9 for FDL connections.

Channel 15 of CSTi1, the Loopback Control Word, is used to control the line loopback code generation and payload loopback functions of the PMAC. This is done by internally connecting the MT8926 DSTo to either a line loopback enable code generator, a line loopback disable code generator, DSTi0 or DSTi1. Figure 6 illustrates the connections required to support these functions. The DSTo of the framer

CSTi0

MT8976/77

CSTo T1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24 PCSW

PSW MSW

0-2

PCSW3PS

Per Channel Status Word

Phase Status Word

Master Status Word

PCSW7X

4-6

8-10

PCSW11X

12-14

PCSW15MS

16-18

PCWS19X

20-22

PCSW23X

24-26

PCSW27X

24-26

PCSW31MS

FIgure 4 - MT 8926 CSTi0 (M T897 6/77 C STo) Channel Alloc atio n Versus T1 Chan nels

4-7

MT8926

0-2

4-6

CSTo

T1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24

PCSW

PCSW7PM

8-10

PCSW11CRC

12-14

PCSW15MS

16-18

PCSW19EF

20-22

PCSW23BPV

24-26

PCSW

27 Rx

BOM

28-30

PCSW31MS

Cyclic Redundancy

PMAC Miscellaneous

Status Word

Bit

7-5

4 3 2 1 0

PCSW = Per Channel Status Word PSW = Phase Status Word * MT8976/77 Data unaltered by the MT8926

Function Not Used LLDD (001) LLED (00001) FECV TMR (2SEC) BOMV

Check-6 Error Counter

Bit

Function

7MSB 0

LSB

Master Sta tus Word 1

Bit

7* 6* 5 4

3* 2 1* 0*

Function YLALR

MIMIC ALRM RAI (ESF YELLOW)

MFSYNC LOS SLIP SYN

Figur e 5 - CSTo Chan ne l All oca t ion Versus T1 C han ne ls

connects to DSTi1 of the PMAC and to the receive side of the system. This allows the PMAC to perform a payload loopback by internally connecting DSTi1 to DSTo. In normal operation, transmit data will flow from DSTi0 to DSTo of the PMAC to DSTi of the MT8976/77.

Errored Frame Event Counter

Bit 7-4 3-0

Function SE (MSB-LSB) FE (MSB-LSB)

Bipolar Violation Counter Master Status Word 2

Function

Bit

7MSB 0

LSB

Received Bit-Oriented

Message Register

Bit

Function

Received First

0 Received Last

Bit

7* 6* 5* 4 3 2 1 0

Function

BlAlm FrCnt Xst SEI FSI CSI BSI AIS

normal operation). In the reset state, data entering the PMAC on FDLi, DSTi0 and CSTi0 will pass through unaltered to FDLo, DSTo and CSTo respectively. E8Ko will be high, IRQ

will be high impedance and the 1SEC output (and TMR bit) will be low.

PMAC RESET

The MT8926 functions may be suspended by making the RESET

input low (RESET must be high for

MT8926

To PMAC Control

4 to 1 MUX

LCW

ST-BUS Transmi t

Data Stream

ST-BUS Receive Data Stream

LCW = Loopback Control Word

Repeating

DSTi0

DSTi1

001

00001

Figure 6 - Payload and Line Loopback Operation

After the MT8976/77 has acquired frame synchronization and RESET

returns high, the MT8926 will require two superframes to acquire synchronization and two ST-BUS frames to align to the ST-BUS. RESET

can be used to prevent DS1 interface

RxA

RxB

CSTi1

DSTo

From System Control

LCW 0 0 0 1 1 0 1 1

DSTi0 to DSTo DSTi1 to DSTo 00001 to DSTo (activate ) 001 to DSTo (deactivate)

MT8976/77

CSTi1

DSTi

DSTo

Function

ECLK

TxA

TxB

4-8

Bit Name Description

MT8926

7-6 YLALR

MIMIC

5 A LRM Alarm . This bit will be set if the MT8926 detect s a 1 in the F

These bits (Yellow Alarm Indication and Mi mi c) contain informa tio n from the MT8976/77 that is unalte red by the MT8 926. See Master Stat us Word 1 of the MT8976/77 data sheet.

bit position of the

twelfth frame of an SF superframe (alternate yellow alarm indication). ALRM will be low when the F

bit is 0.

When receiving an ESF signal or if bit 3 (FSEL) of the PMAC Control Word (CSTi1 Channel 11) is low, the ALRM bit will always be low.

4 RAI Rem ot e Alarm In dicat ion (also kn own as ESF Yellow Alarm). This bit is set if an

RAI code word (repeating hex FF00 pattern) is received on the ESF facilit y data link. This code must be correctly detected in seven out of 10 messages. RAI will be reset if more than three of 10 messages are in error. When receiving an SF signal, this bit will always be low.

3MFSYNC

This bit (Multiframe Synchronization) contains information from the MT8976 that is unaltered by the MT8926. See Master S tatus Word 1 of the MT8976 data sheet.

2 LOS Loss of Signal. This bit will go high when the MT8926 detects 128 or more

consecutive zeros in the line signal. It will be reset after the device detects a 12.5% ones density (48 ones in two or less frames) in the received signal.

1-0 SLIP

SYN

These bits (Slip Ind ication and Synchron izati on) contain inform at ion from the MT8976/77 that is unalte red by the MT8 926. See Master Stat us Word 1 of the MT8976/77 data sheet.

Table 3. M aster S tat us Word 1 (CSTo Channe l 15)

Bit 1 Bit 0 Description

0 0 Normal operation. The transmit data applied to DSTi0 will pass through the PMAC, and be

output on DSTo.

0 1 Payload Loopback mode. Connect as per Figure 6. The received data on DSTo of the

MT8976/77 is routed through th e PMAC to the DSTi input of the MT8976/77.

1 0 Transmit Line Loopback Enable. Connect as per Figure 6. DSTo of the PMAC will be internally

connected to an SF line loopback enable code generat or. That is, a repeating 00001 code is placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer.

1 1 T ransmit Line Loopback Disable. Connect as per Figure 6. DSTo of the PMAC will be internally

connected to an SF line loopback disable code generator. That is, a repeating 001 code is placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer.

Table 4 - Loopback Control Word (CSTi1 Cha nne l 15)

Note: Bits 2 to 7 of the Loopback Control Word are not used.

interrupts from occurring during system initialization. It should be noted that when the

an ESF signal is being received or when FSel is low,

ALRM will always be low. MT8926 is acquiring synchronization the CRC and BPV counters may record errors.

A low to high transi tion of the ALR M bit will in itiate a

group one (G1) interrupt.

ALRM (SF Yellow Alarm)

Remote Alarm Indica tion (RAI)

The MT8926 will recognize the sixth F superframe as an alternate Yellow Alarm indicator, if FSel of the PMAC Control Word is high. That is, when this F

bit is high/low, the ALRM bit of Master

Status Word 1 will be high/low (see Table 3). When

bit of an SF

The PMAC will decode the bit-oriented priority

codeword 11111111 0000 0000 received on the FDL

as a Remote Alarm Indication (RAI or Yellow Alarm)

signal as per T1.403/408. See the section on

4-9

MT8926

MT8926 FDL message transfer. This 16 bit pattern must be detected in seven out of 10 codewords in

(approximately 48 ones is received in two or less

frames). order for the RAI bit of Master Status Word 1 (CSTo channel 15 bit 4) to go high (see Table 3). If more than three out of 10 codewords are in error, then RAI

Payload Loopback

will remain low.

The payload of a T1 signal consists of the 192 data A low to high transition of the RAI bit will initiate a

group one (G1) interrupt. See the section on interrupts fo r t he control of th e R AI interrupt.

bits of each frame and excludes the framing bit (the

first bit of 193). Therefore, a T1.403 or T1.408 ESF

payload loopback extracts the payload of a receive

T1 signal and transmits it back to the originator with

new framing bits. This allows the transport of

Loss of Signal Indication (LOS)

maintenance and performance data over the facilit y

data link while the payload loopback is activated. The LOS bit of M aster Status Word 1, Table 3, will be

high if the MT8926 receives 128 or more consecutive zeros from the T1 interface. LOS will return low when

The CRC-6 multiframe alignment remainder will not

be looped around, but will function normally (i.e.,

calculated for each direction of transmission). a ones density of 12.5% has been achieved

Bit Name Description

7-5 --- Not Used.

4 LLDD Line Loopback Disable Detect. This bit is set when a repeating 001 pattern (either

framed or unframed) is detected in the received T1 signal for at least five frames. In order to comply with T1.403, the user's operating system will ensure that this code is present for at least five seconds before deactivating the S F line loopback (MT8976/77 Remote Loopback).

)

The MT8926 will detect this repeating bit pattern even in the presence of a BER of 3 errors in 1000 bits.

3 LLED Lin e Loopback Ena ble Det e ct. This bit is set when a repeating 00001 pattern

(either framed or unfram ed) is detect ed in the received T1 signal for at least five frames. In order to comply with T1.403, the user's operating system will ensure that this code is present for at least five seconds before activating the SF line loopback (MT8976/77 Remote Loopback).

The MT8926 will detect this repeating bit pattern even in the presence of a BER of 3 errors in 1000 bits.

2 FECV Framing Error Count Validation. This bit is set when the MT8926 has synchronized

to a framed T1 signal. The framing error count is frozen if this bit is not set. Synchronization (FECV =1) is reported when the MT8926 det ects two consecuti ve

superframes with correct framing bits, and bit 0 in CSTi0 channel 15 (SYN When receiving an SF signal, both F the PMAC Control word is set. In this case the sixth F checking for framing bits. If bit FSel is reset, then only F

and FT bits are examined if bit 3 (FSel) in

bit is not examined when

bits are examined.

Loss of synchronization (FECV=0) is reported when either two out of four errors have been detected in the received framing bit position (S F F bits) or if bit 0 in CSTi0 channel 15 (SYN

) is set indicating the MT8976/77 has lost

bits or ESF FPS

synchronization. 1 TMR Two Second Timer. This bit changes state once per second. 0 BOM V Bit-Oriented Messa g e Validation. This bit will be set when a valid bit-oriented

message is present in the receive BOM register (T able 12, CSTo, channel 27). It is

reset when a valid message is not being received. A valid bit-oriented message

has the form 111111110XXXXXX0, where XXXXXX co ntains the messag e

information.

Table 5. PMAC Miscell ane ous Sta tus Word (C STo Channel 7)

4-10

) is zero.

+ 18 hidden pages