MITEL MT8924AE Datasheet
MT8924
PCM Conference Circuit (PCC)
Preliminary Information
Features
• Supports up to 10 independent conferences for
up to 32 PCM Voice Channels
• ST-BUS compatible 2.048 Mb/s PCM Serial
Interface (also supports 1.536 Mb/s and 1.544
Mb/s data rates)
• Per channel digital gain control (0/-3/-6 dB)
• Parallel microprocessor port for device control
• Programmable noise suppression
• External Tone Input
• Pin selectable A/µ-Law format
• Low power CMOS technology
• Available in 24 Pin PDIP and SOIC packages
Applications
• Digital PBX / KTS
• Conference bridges
• Digital C.O. switches
ISSUE 1 April 1994
Ordering Information
MT8924AE 24 Pin Plastic DIP (600 mil)
MT8924AS 24 Pin SOIC
0°C to +70°C
Description
The MT8924 is designed to provide conference call
capability in digital switching systems. It allows up to
10 independent conferences to be set for up to 32
PCM voice channels.
A/µ-Law companded data from the PCM input port is
converted to linear format, processed by a dedicated
arithmetic unit, re-converted to companded format
and then sent to the PCM output port.The PCM
output signal contains all the information of each
channel connected in conference except its own.
Programmable attenuation and noise suppression
are provided for channels connected in conference
or transparent mode. Additionally, an input for an
external tone is featured that can be used as a signal
to indicate to connected parties that they are on a
conference call.
DSTi
OS
Overflow
Attenuation/Noise Suppression
Channel RAM
µ/A-Law
to
Linear
Serial-to-Parallel
Conversion
PCM Mode
Control
RESET WRRD
µ
A/
Timebase
F0i Cko D0-D7TDTF
Cki
and
Adder
PCM Tone
Generator
MUX
Figure 1 - Functional Block Diagram
Linear
to
µ/A-Law
Parallel-to-Serial
Conversion
Control
CS
DSTo
D
C/
8-3
MT8924 Preliminary Information
TD
TF
RESET
OS
DSTo
D7
D6
D5
D4
D3
D2
D1
10
11
12
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
VSS
A/
µ
DSTi
Cko
Cki
F0i
WR
RD
CS
C/
D
VDD
D0
Figure 2 - Pin Connections
Pin Description
Pin # Name Description
1TDTone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all
channels have the same tone during the same frame number. When TD is Low, normal
operation is enabled.
2TFTone Frequency (Input). This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the
same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale
value, and is activated when TD is High.
3 RESET Master RESET (Input). This input is used for system reset after power up, or when the
companding law format has been changed. The RESET pin is strobed by the rising edge of
clock Cki. Complete circuit initialization takes two frame periods. Resetting the device
disables the output drivers of the microprocessor interface and DSTo.
4 OS Overflow Signalling (Output). When OS is Low , a conference is in the overflo w condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of
the conference in overflow (see Figure 9).
5 DST
ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon
o
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.
6-13 D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are
transferred to and from the microprocessor (where D0 is the least significant bit). The bus is
in a high impedance state when RESET is Low and/or CS is High.
14 V
DD
Positive Supply Voltage. Nominally 5 volts.
15 C/D Contr ol/Data Select (Input). The signal on this input defines whether the inf ormation on the
data bus should be interpreted as opcode or data. During a write operation a Low signal
defines the bus content as data, while a High signal defines it as opcode. During a read
operation this input differentiates overflow status between the first eight channels for C/D
being LOW, and the last two channels f or C/D being HIGH (see Instruction 4). This input also
allows status monitoring (see Instruction 6) during a read operation.
16 CS Chip Select (Input). This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the
microprocessor, and when CS is High, the data bus is in a high impedance state.
17 RD Read (Input). This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.
18 WR Write Input. This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.
8-4
Preliminary Information MT8924
Pin Description (continued)
Pin # Name Description
19 F0i Frame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the
PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i
determines the start of a new frame and must correspond to the first bit of the first channel.
When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the
Extra (193rd) bit.
20 Cki Clock (Input). This signal is the timing reference used for all internal operations. The PCM
bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable
clock frequency is 4096 kHz.
21 Cko Clock (Output). This pin provides the master clock for a digital crosspoint switch (e.g.,
MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is
identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two
cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924
to operate in 1544 kbit/s systems.
22 DSTiST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable
bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the
rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating
mode is selected, the first bit of the first channel defines the extra bit.
23 A/µ A/µ - Law Select Input. When A/µ is High, A-Law is selected, and when A/µ is Low ,µ-Law is
selected. The companding law selection must be done before initializing the de vice using the
RESET pin.
24 V
Functional Description
Negative Power Supply Voltage. Nominally 0 Volts.
SS
channel N+1, frame M and subtracted during the
second half of channel N-1, frame M+1. After Linear-
The MT8924 is a device designed to provide
conferencing in a digital switching system in any
combination for up to all 32 channels of a 2048 kbit/s
ST-BUS stream (see Figure 3).
The information of channel N, frame M is first
converted to Linear PCM and then added to the
signal from other conferencees during the first half of
to-PCM conversion the subtraction result goes to the
parallel-to-serial converter, and appears at the
output on the N+1 channel, M+1 frame with respect
to the corresponding sending party information (see
Figure 4).
To a microprocessor the MT8924 appears as a
memory mapped peripheral device that can be
controlled by a set of six instructions. These
commands can be used to establish or cancel
Microcontroller
conferences between the PCM channels and also to
transmit control messages on specific operating
modes. The microprocessor can initiate and receive
status messages or check conference connections
STi0
.
.
.
.
STix-1
STix
MT8980/81/82
Digital Switch
MT8924
PCM Conference
Circuit (PCC)
STo0
.
.
.
.
STox-1
STox
that are currently in operation.
Input
Information
B
A
DSTi
Input Channels
Frame M
C
MT8924
N+2N+1N
Output
Information
B+C A+C A+B
N+2 N+3N+1
Output Channels
Frame M+1
DSTo
Figure 3 -Typical Conference Connection
Figure 4 - Input/Output Channel Relationship
8-5
MT8924 Preliminary Information
Noise
Threshold
A-Law 1/4096 1000 0000 0000 0000
9/4096 1000 0100 0000 0100
16/4096 1000 1000 0000 1000
32/4096 1000 1111 0000 1111
µ-Law 1/8159 1111 1111 0111 1111
9/8159 1111 1011 0111 1011
16/8159 1111 0111 0111 0111
32/8159 1111 0000 0111 0000
Table 1 - PCM Noise Suppression Threshold Levels
Overflow Detection / Input Channel Attenuation
If the sum of the channels involv ed in one conference
exceeds the full scale value of the accumulator, an
overflow condition is generated which can be
monitored specifically by reading the status of the
overflow register. If an overflow condition occurs,
then each channel in a conference can be
independently attenuated if desired.
PCM Byte
+ve input -ve input
B7 - B0 B7 - B0
Alternatively, a conference in the overflow condition
can be detected using the OS signal in conjunction
with frame pulse F0i. OS will be low during the
second half of a general output channel slot time N,
if channel N belongs to a conference in overflow (see
Figure 11). This information can be used to control
input channel attenuation through software control.
F1 F0 B7 B6 B5 B4 B3 B2 B1 B0 Comments
0 0 + Full Scale 11111111No Inversion
+ 0 Level 10000000
- 0 Level 00000000
- Full Scale 01111111
0 1 + Full Scale 10101010Even Bit Inversion
+ 0 Level 11010101
- 0 Level 01010101
- Full Scale 00101010
1 0 + Full Scale 11010101Odd Bit Inversion
+ 0 Level 10101010
- 0 Level 00101010
- Full Scale 01010101
1 1 + Full Scale 10000000Bit Inversion
+ 0 Level 11111111
- 0 Level 01111111
- Full Scale 00000000
B7 (sign bit) is the MSB and B0 is the LSB
F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5
Table 2 - PCM Byte Format
8-6
Preliminary Information MT8924
Noise Suppression
When noise suppression is enabled for a specific
input channel then the PCM bytes for this channel,
when below the selected threshold level, are
converted to PCM bytes corresponding to the
minimum PCM code level before being added to the
conference sum.
The four threshold levels available correspond to the
first, fifth, ninth and sixteenth step of the first
segment. These are 1/4096, 9/4096, 16/4096, and
32/4096 with respect to full scale A-Law, and 1/8159,
9/8159, 16/8159, and 32/8159 with respect to full
scale µ-Law (see Table 1).
PCM Format Selection
PCM digital code assignment is register
programmable and achieved through the use of
Instruction 5 (see Table 2). The available formats are
CCITT G.711 A-Law or µ-Law, with true-sign
Alternate Digit Inversion or true-sign/Inverted
Magnitude coding.
Output clock Cko provides a reference time base for
a digital time/space crosspoint switch. Normally this
signal is identical to the master clock input Cki.
When operating with the extra bit selection, through
Instruction 5, Cko is low for two clock periods, which
allows operation of the MT8924 with the 1.544 MHz
PCM frame format (see Figure 10).
Testing and Diagnostic Feature
For testing and diagnostic purposes, a status
instruction has been provided that indicates
conference location and attenuation level for each
channel requested. This data appears on the
databus upon status request.
Programmable Control
Instruction 1 : Conference Mode Connection
This function connects a PCM channel to a
conference. The control information from the
microprocessor consists of two data bytes and one
control byte. The first byte contains the conference
number (bits D0-D3) and the Start bit S (D4). When
S is High, the accumulator registers connected to a
conference are initialized. S set to High is only
required in Instruction 1 of the first channel
connected to a new conference, otherwise S is set
LOW to bring other channels into the conference.
The second byte contains the number of the
channel to be connected (D0-D4), and the Insert
Tone Enable bit IT (D5). When IT and TD are both
High all the channels belonging to that conference
are enabled using the insert tone function. The
third byte contains a four bit opcode (D0-D3) plus
information about the attenuation level and noise
suppression to be applied to the specific channel.
Transparent Mode
The MT8924 can operate in transparent mode. In
this case the PCM input (DSTi) is passed unmodified
through the MT8924 to the output (DSTo) with a
delay of one frame and one channel. This feature
allows attenuation of specific channels that are not
connected to a conference.
Tone Insertion
The MT8924 provides for tone insertion into PCM
output channels by using the two input pins TD and
TF. An externally generated square wave tone
applied to the TF input will generate a level
corresponding to 1/10 of the full scale accumulator
value when TD is High. Only channels connected in
a conference with the insertion tone bit (IT) active
will have the PCM coded tone at their output (see
Instruction 1).
Instruction 2 : Transparent Mode Connection
This function sets up a PCM channel for
transparent mode operation. The control
information from the microprocessor consists of
one data byte and one control byte.
The first byte contains the channel number, and
the second byte contains a four bit opcode (D0-D3)
and information about attenuation and noise
suppression levels to be applied to the specific
channel. PCM data on this channel is not added to
any conference, but is transferred to the PCM
output after a full frame pulse plus one channel
delay. It is not affected by the tone control pins (TF,
TD).
Instruction 3 : Disconnection
This function disconnects a PCM channel from a
conference. The control information from the
microprocessor consists of one data byte and one
8-7
MT8924 Preliminary Information
control byte. The data byte contains the number of
the channel to be disconnected. The second byte
contains the opcode (D0-D3). One frame pulse
must pass between disconnection and
reconnection of the same channel.
Instruction 4 : Overflow Status Monitoring
This function extracts overflow status information
on all existing conferences and transfers it to the
microprocessor data bus. This instruction consists
of two control bytes which are differentiated by the
C/D control signal. C/D set Low reads the status of
the first eight conferences, while C/D set High
reads the status of the remaining two conferences.
A conference is in overflow when the
corresponding status bit is high.
Instruction 5 : PCM Mode Select
This function is used to set the PCM format. The
control byte from the microprocessor consists of
one data byte. It contains the Extra Bit E (D6), the
Format Bits F1-F0 (D5, D4), and the opcode (D0D3). The E bit must be high when the PCM frame
contains an extra bit (i.e. 1.544 Mb/s). Normally E
is Low. Bits F1-F0 are used to select the PCM byte
format, according to Table 2. After RESET the
default values correspond to F1 at Low and F0 at
High if A-Law is selected, and F1 at High and F0 at
High if µ-Law is selected. All channels must be
disconnected when the PCM mode select
instruction is sent. They must remain disconnected
for at least two frame pulses after the instruction is
sent. It is recommended that this instruction be
used immediately following a system reset (see
RESET pin description).
Instruction 6 : Status Monitoring
This function is a read operation which consists of
a data byte, a control byte, and a status byte. It
extracts information for test and diagnostic
purposes and transfers it to the microprocessor
bus. The first byte contains the channel number,
while the second byte contains the opcode (D0D3). The third byte contains the status information
about the operating mode of the channel (D4-D7);
the attenuation level (D2-D3); and the noise
suppression level (D0-D1).
8-8
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