MITEL MT88L85AE, MT88L85AP, MT88L85AN Datasheet

MT88L85



3V Integrated DTMFTransceiver

with Power Down & Adaptive

Features

• External power down pin

• Low vol tage ope rati on (2. 7V - 3.6V)

• Central office quality DTMF transmitter/ receiver

• Low pow er co nsump tion

• High sp eed ada pti ve micr o in terface

• Adjustable guard time

• Automa tic ton e burs t mode

• Call prog ress t one de tectio n to -3 0dBm

• DTMF transmitter/receiver power down via register control

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interco nnect dialers

• Persona l comp uters

Description

The MT88L85 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.

Advance Information

ISSUE 1 May 1995

Micro Interface

Ordering Information

MT88L85AE 24 Pin Plastic DIP MT88L85A N 24 Pin SSO P MT88L85AP 28 Pin PLCC

-40°C to +85°C

The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones.

The MT88L85 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT88L85 provides enhanced power down features. The transmitter and receiver may independently be powered down via register control. A full chip power down pin provides simple power and control capability.

TONE

IN+

INGS

OSC1 OSC2

∑

Tone Burst Gating Cct.

DDVRefVSS

Tone Filter

Oscillator

Circuit

Bias

Circuit

Dial

Converters

PWDN

D/A

Control

Logic

High Group

Filter

Low Group

Filter

Control

Logic

Figure 1 - Functional Block Diagram

Row and

Column

Counters

Digital

Algorithm and Code Converter

Steerin g

Logic

ESt St/GT

Transmit Data

Status

Control

Receive Data

Data

Bus

Buffer

Interrupt

Logic

I/O

Control

D0 D1 D2 D3

/CP

IRQ

DS/RD CS R/W/WR RS0

4-71

MT88L85 Advance Information

GSNCIN-

IN+

VDD

St/GT

24 23 22 21 20 19 18 17 16 15 14 13

VDD St/GT ESt D3 D2 D1 D0 NC PWDN

/CP

IRQ DS/RD RS0

VRef

VSS OSC1 OSC2

NC NC

432

5 6 7 8 9 10 11

1213141516

TONE

•

/WRCSRS0 R/W

28 PIN PLCC

R/W

IN+

IN-

VRef

VSS OSC1 OSC2

NC NC

TONE

/WR

1 2

3 4

5 6

7 8

9 10 11 12

24 PIN DIP/SSOP

Figure 2 - Pin Connections

Pin Description

Pin #

24 28

1 1 IN+ Non-inverting op-am p input. 22 IN- Inverting op-amp input. 34 GS Gai n Select. Gives ac cess to output of front end differentia l amplif ier for connecti on of

46 V 57 V 68 OSC1Oscillator input. This pin can also be driven directl y by an external clock. 79 OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes

10 12 TONE Output from internal DTMF transmitter. 11 13 R/W 12 14 CS

13 15 RS0 Register Selec t input. Refer to Table 3 for bit interpretation. CMOS co mpa tible. 14 17 DS (RD

15 18 IRQ

16 19 PWDN Power Down (input). Active High. Powers down the device and inhibits the oscillator. IRQ

14-1718-21D0-D3 Microprocessor dat a bus. High impedance when CS

18 22 E St Early Steering output. Presents a logic high once the digital algorithm has detected a valid

19 23 S t/GT Steering Input/Gu ard Time output (bidirect ional ). A voltage greater than V

20 24 V

4-72

Name Descrip tion

feedback resistor. Reference Vo ltage output (VDD/2).

Ref

Ground (0V).

the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.

(WR) (Motorola) Read/Write or (Intel ) Write microprocessor input. CMOS compatible.

Chip Select input. This signal m ust be quali fied externall y by either address strobe (AS),

valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.

) (Motorola) Data Stro be or (Intel) Read microprocessor input. Activit y on t his input is only

required when the device is being accessed. CMOS compatible.

/CP Inte rrupt Request/Call Progress (ope n drain) outpu t. In interrupt mode, this output goes

low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth lim it s of the call progress filte r, see Figure 8.

and TONE output are high impedance. Data bus is held in tri-stat e. This pin is internally pulled down.

= 1 or DS =0 (Motorola) or RD = 1

(Intel). TTL compatible.

tone pair (signal condition). Any momentary loss of signal condit ion will cause ESt to return to a logic low.

St causes the device to register the detected tone pair and updat e the output latch. A voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (3V typ.).

ESt

NC PWDN

DS/RD

IRQ/CP

detected at

TSt

Advance Information MT88L85

Pin Description

Pin #

24 28

8,9

Name Descri ption

3,5,

10,11

16, 20,

NC No Connection.

Functional Description

The MT88L85 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT88L85 internal registers.

Power Down

The MT88L85 provides enhanced power down functionality to facilitate minimization of supply current consumption. DTMF transmitter and receiver circuit blocks may be independently powered down via register control. When asserted, the RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only with the DTMF transmitter in power down mode. With the TOUT control bit asserted, the TONE output pin is held in a high impedance (floating) state. When both power down control bits are asserted, circuits utilized by both the DTMF transmitter and receiver are also powered down. This includes the crystal oscillators, and the VRef generator. In addition, the IRQ

, TONE output and DATA pins are held in a high impedance state. Finally, the whole device is put in a power down state when the PWDN pin is asserted.

Input Configuration

The input arrangement of the MT88L85 provides a differential-input operational amplifier as well as a bias source (V V

/2. Provision is made for connection of a

feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3.

), which is u s ed to b i a s the i npu ts at

Ref

Receiver S ec tio n

Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters , the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

MT88L85

IN+

VOLTAGE GAIN

) = RF / R

Figure 3 - Single-Ended Input Configuration

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) - R5/R1

INPUT IMPEDANCE

IN-

Ref

MT88L85

IN+

IN-

Ref

diff) = 2 R12 + (1/ωC)

Figure 4 shows the necessary connections for a differential input configuration.

Figure 4 - Differential Input Configuration

4-73

MT88L85 Advance Information

) of the steering logic to register the tone pair,

TSt

LOW

HIGH

DIGIT D

6971209 1 0001 6971336 2 0010 6971477 3 0011 7701209 4 0100 7701336 5 0101 7701477 6 0110 8521209 7 0111 8521336 8 1000 8521477 9 1001 9411336 0 1010 9411209 * 1011 9411477 # 1100 6971633 A 1101 7701633 B 1110 8521633 C 1111 9411633 D 0000

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Dec ode Table

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

Steering Circuit

latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives v

to VDD. GT

continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ

/CP pin will pull low when the

delayed steering flag is active.

The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirect ional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

MT88L85

St/GT

ESt

= (R1C1) In (VDD / V

GTA

= (R1C1) In [VDD / (VDD-V

GTP

TSt

)

)]

TSt

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7):

Before registration of a decoded tone pair, the receiver checks f or a valid signal duration (referred to as character recognition condition). This check is performed by an external R C time constant driven by ESt. A logic high on ESt causes v

(see Figure 5) to

rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (t

4-74

), vc reaches the threshold

GTP

≥ t

REC

≤ t

REC

≥ t

tDO ≤ t

DPmax

DPmin

DAmax

DAmin

+ t + t + t + t

GTPmax GTPmin

GT Amax

GT Ami n

- t

DPmin

DAmin

DAmax

DPmax

The value of tDP is a device parameter (see AC Electrical Characteristics) and t

is the minimum

REC

Advance Information MT88L85

signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most

St/GT

ESt

St/GT

ESt

= (RPC1) In [VDD / (VDD-V

GTP

= (R1C1) In (VDD/V

GTA

= (R1R2) / (R1 + R2)

a) d ecrea sing tGTP; (tGTP < tGTA)

= (R1C1) In [VDD / (VDD-V

GTP

= (RpC1) In (VDD/V

GTA

RP = (R1R2) / (R1 + R2)

b) decreasing tGTA; (tGTP > tGTA)

TSt

)]

)

)]

)

Figur e 6 - G ua rd Ti me A dj ust m ent

applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (t tone absent (t

) guard times. This may be

GTA

GTP

) and

necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustm ent also allows the designer to tailor system parameters such as talk off and noise immunit y.

Increasing t

improves talk-off performance since

REC

it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t

with a long tDO would be appropriate for

REC

extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.

Call Progress Filter

A call progress mode, using the MT88L85, can be selected allowing the detection of various tones, which ident ify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP mode has been selected.

EVENTS

ESt

St/GT

-RX

Read Status Register

/CP

IRQ

ABCDEF

REC

DECODED TONE # (n-1)

REC

TONE #n

GTP

PStRX

PStb3

# n

TONE #n + 1

GTA

TONE #n + 1

# (n + 1)

TSt

Figure 7 - R ece iver Tim ing Diag ram

4-75

MT88L85 Advance Information

AAAA

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATI ON INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALI D, INFORMATION IN RX DATA REGISTER

D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DE TECTED, TONE A BSENT DURATION VALI D, I NFORMATION IN RX DATA REGISTER

EXPLANATION OF SYMBOLS

ESt EARLY S TEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STE ERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX

b3 DELAYED STEERING. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE

b2 INDICATES THAT VALI D DATA IS IN THE RE CEIVE DATA RE GISTER. THE BIT IS CLEARED AFTER THE STATUS

IRQ

REC

GTP

GTA

RETAINE D UNTI L NEXT VALID TONE PAIR.

DTMF COMPOSITE INPUT SIG NA L.

-RX34-BIT DECODED DATA IN RECEIVE DATA REGISTER

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL.

/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STAT US R EGI STER IS READ. MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. MINIMUM TIME BET WEEN VALID SEQUENTI AL D TMF SIG NAL S. MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TIME TO DETECT VALID FREQUENCIES PRESENT. TIME TO DETECT VALID FREQUENCIES ABSENT. GUARD TIME, TO NE PR ESEN T. GUARD TIME, TO NE ABSEN T.

Figur e 9 - De scri pt ion of Tim in g Ev en ts

DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accep t’ bandwidth limits of the filter, are hardlimited by a high gain comparator with the IRQ/CP pin serving as the output. The squarewave output obtained from the schmitt trigger c an be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ

/CP

pin will remain low.

DTMF Generator

The DTMF transmitter employed in the MT88L85 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format s hown in Table 1 must be written to

the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f

LOW

and f

HIGH

) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to com-pensate for high group attenuation on long loops.

LEVEL

(dBm)

AAA

AAAA

AAA

AAAA

-25

AAA

AAAA

0250500750

= Reject

FREQUENCY (Hz)

= May Accept

AAA

AAAA

= Accept

AAA

Figure 8 - Call Progress Response

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