MITEL MT88E39AS Datasheet

CMOS

MT88E39

Calling Number Identification Circuit

Advance Information

(CNIC1.1)

Features

• 1200 baud Bell 202 and CCITT V.23 Frequency
Shift Keying (FSK) demodulation

• Compatible with Bellcore GR-30-CORE,
SR-TSV-002476, TIA/EIA-716 and
ETSI 300 778-1

• High input sensitivity

• Dual mode 3-wire data interface (Serial FSK
data stream or MT88E43 compatible 1 byte
buffer)

• Internal gain adjustable amplifier

• Carrier detect status output

• Uses 3.579545 MHz crystal or ceramic
resonator

• 3 to 5V ±10% supply voltage

• Low power CMOS with power down mode

• Direct pin to pin replacement of MT8841 and
MT88E41

Applications

• Global (North America, Japan, Europe) FSK
based CID (Calling Identity Delivery) / CLIP
(Calling Line Identity Presentation)

• Feature phones, adjunct boxes

• FAX machines

• Telephone answering machines

• Computer Telephony Integration (CTI)

• Battery powered applications

DS5035 ISSUE 3 November 1998

Ordering Information

MT88E39AS 16 Pin SOIC

-40 to +85 °C

Description

The MT88E39 Calling Number Identification Circuit
(CNIC1.1) is a CMOS integrated circuit which
provides an interface to calling line information
delivery services that utilize 1200 baud Bell 202 or
CCITT V.23 FSK data transmission schemes. The
MT88E39 receives and demodulates the FSK signal
and outputs the data into a simple dual mode 3-wire
serial interface which eliminates the need for an
UART.

The MT88E39 is Bellcore, ETSI and NTT compatible
and can operate in 3V and 5V applications. It is a pin
to pin replacement of the MT8841 and MT88E41 by
operating in the MT88E41 FSK interface mode
(mode 0) when placed in a MT88E41 socket. New
designs may also choose the MT88E43 compatible
interface (mode 1) where the microcontroller reads
the FSK byte from a 1 byte buffer.

GS

IN-

IN+

CAP
V

Ref

-

+

Bias

Generator

PWDN OSC1 OSC2 V

Receive

Bandpass

Filter

Clock

Generator

Figure 1 - Functional Block Diagram

FSK

Demodulator

Carrier

Detector

to other
circuits

SSVDD

Data and Timing

Recovery

MODE IC

DATA
DR
DCLK

CD

5-1

MT88E39 Advance Information

IN+

IN-

GS

VRef

CAP
OSC1
OSC2

VSS

1
2

3
4

5
6

7
8

16 PIN SOIC

16
15
14
13
12
11
10

9

VDD
IC**
MODE*
PWDN
CD

DR
DATA
DCLK

* Was IC1 in MT88E41
** Was IC2 in MT88E41

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

1 IN+ Non-inverting Op-Amp (Input).
2 IN- Inverting Op-Amp (Input).
3GSGain Select (Output). Gives access to op-amp output for connection of feedback resistor.
4V
5 CAP Capacitor. Connect a 0.1µF capacitor to VSS.
6 OSC1 Oscillator (Input). Crystal connection. This pin can be driven directly from an external

7 OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin

8VSSPower supply ground.
9 DCLK 3-wire FSK Interface: Data Clock (CMOS Output/Schmitt Input). In mode 0 (MT88E41

10 DATA 3-wire FSK Interface: Data (CMOS Output). In mode 0 (MT88E41 compatible mode - when

11 DR 3-wire FSK Interface: Data Ready (Open Drain/CMOS Output). Active low. In mode 0

12 CD Carrier Detect (Open Drain/CMOS Output). Active low. In mode 0 (MT88E41 compatible

13 PWDN Power Down (Schmitt Input). Active high. Powers down the device including the input

Voltage Reference (Output). Nominally V

Ref

/2. This is used to bias the op-amp inputs.

DD

clocking source.

should be left open.

compatible mode - when the MODE pin is logic low) this is a CMOS output which denotes the
nominal mid-point of a FSK data bit.
In mode 1 (when the MODE pin is logic high) this is a Schmitt trigger input used to shift the
FSK data byte out to the DATA pin.

the MODE pin is logic low) the FSK serial bit stream is output to DATA as demodulated. Mark
frequency corresponds to logical 1. Space frequency corresponds to logical 0.
In mode 1 (when the MODE pin is logic high) the start and stop bits are stripped off and only
the data byte is stored in a 1 byte buffer. At the end of each word signalled by the DR pin, the
microcontroller should shift the byte out to DATA pin by applying 8 read pulses at the DCLK pin.

(MT88E41 compatible mode - when the MODE pin is logic low) this is an open drain output. In
mode 1 (when the MODE pin is logic high) this is a CMOS output.
This pin denotes the end of a word. Typically, DR is used to interrupt the microcontroller. It is
normally hi-Z or high (modes 0 and 1 respectively) and goes low for half a bit time at the end of
a word. But in mode 1 if DCLK begins during DR low, the first rising edge of the DCLK input
will return DR to high. This feature allows an interrupt requested by DR to be cleared upon
reading the first DATA bit.

mode - when the MODE pin is logic low) this is an open drain output. In mode 1 (when the
MODE pin is logic high) this is a CMOS output.
A logic low indicates that a carrier has been present for a specified time on the line. A time
hysteresis is provided to allow for momentary discontinuity of carrier. The demodulated FSK
data is inhibited until the carrier has been detected.

op-amp and the oscillator. Must be low for operation.

5-2

Advance Information MT88E39

Pin Description

Pin # Name Description

14 MODE Mode select (Input). This pin selects the 3-wire FSK interface mode. To select mode 0

(MT88E41 compatible mode) this pin should be logic low. To select mode 1 this pin should be
logic high.
Because this pin is already connected to Vss in ’E41 applications, the MT88E39 can replace
the ’E41 without any circuit or software change.

15 IC Internal Connection. Internal connection. Leave open circuit. In MT88E41, this was IC2

which was also left open in the application circuit.

16 V

Positive power supply voltage.

DD

Functional Description

The MT88E39 is a FSK demodulator compatible with
FSK based Caller ID services around the world, such
as in North America, France, Germany, and Japan.
Caller ID is the generic term for a group of services
offered by telephone operating companies whereby
information about the calling party is delivered to the
subscriber. In the FSK based methods, the
information is modulated in either Bell 202 (in North
America) or CCITT V.23 (in Europe) FSK format and
transmitted at 1200 baud from the serving end office
to the subscriber’s terminal.

In North America, Caller ID uses the voiceband data
transmission interface defined in the Bellcore
document GR-30-CORE. The terminal or CPE
(Customer Premises Equipment) requirements are
defined in Bellcore document SR-TSV-002476.
Typical services are CND (Calling Number Delivery),
CNAM (Calling Name Delivery), VMWI (Visual
Message Waiting Indicator) and CIDCW (Calling
Identity Delivery on Call Waiting).

The MT88E39 provides an interface to the Caller ID
physical layer. It bandpass filters and demodulates
the 1200 baud FSK signal. It also provides a
convenient interface to extract the demodulated FSK
data. Although the main application of the MT88E39
is Caller ID, it can also be used wherever 1200 baud
Bell 202 and/or CCITT V.23 FSK reception is
required.

3 to 5V operation

The MT88E39 can operate from 5.5V down to 2.7V,
but the FSK reject level will change with Vdd. In a
battery powered CPE, the FSK accept level will
become lower as the batteries are run down. If the
CPE is designed for 4.5V, the accept level will be
lowered when the batteries drain to 3V. In North
America there is a requirement for rejecting FSK
signals which are below 3 mVrms when data is not
preceded by ringing, such as VMWI (Visual Message
Waiting Indicator) applications. When the batteries
are drained, the CPE will not meet the reject level.
For on-hook Caller ID, there is no reject level and the
CPE will meet all requirements.

In on-hook Caller ID, such as CND and CNAM, the
information is typically transmitted from the end
office before the subscriber picks up the phone.
There are various methods such as between the first
and second rings (North America), between an
abbreviated ring and the first true ring (Japan,
France and Germany). On-hook Caller ID can also
occur without ringing for services such as VMWI.
The MT88E39 is suitable for these for ms of alerting.

In off-hook Caller ID, such as CIDCW, information
about a new calling party is sent to the subscriber
who is already engaged in a call. Bellcore’s method
uses a special dual tone known as CAS (CPE
Alerting Signal) which should be detected by the
CPE. After the CPE has acknowledged with a DTMF
digit, the end office will send the FSK data. The
MT88E39 is suitable for receiving the FSK data but a
separate CAS detector is required.

Input Configuration

The input arrangement of the MT88E39 provides an
operational amplifier, as well as a bias source (V
which is used to bias the inputs at V

/2. Provision is

DD

Ref

made for connection of a feedback resistor to the
op-amp output (GS) for adjustment of gain.

Figure 3 shows the necessary connections for a
differential input configuration. In a single-ended
configuration, the input pins are connected as shown
in Figure 4.

5-3

)

MT88E39 Advance Information

Mode 0

R1

C1

R4

C2

R3

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2
R1 = R4
R3 = (R2 x R5) / (R2 + R5)
For unity gain, R5 = R1

VOLTAGE GAIN

(AVdiff) = R5/R1

R2

INPUT IMPEDANCE

(ZINdiff) = 2

R5

IN+

IN-

GS

V

Ref

MT88E39

R1

Figure 3 - Differential Input Configuration

IN+

R

C

IN

R

F

IN-

GS

2

+ (1/ωC)

This mode is selected when the MODE pin is low. It
is the MT88E41 compatible mode where the FSK
data stream is output as demodulated. Since the
MODE pin was IC1 in MT88E41 and connected to
Vss, the MT88E39 will work in mode 0 when placed
in a MT88E41 socket.

In this mode, the MT88E39 receives the FSK signal,
demodulates it, and outputs the data directly to the
DATA pin (see Figure 11). For each received stop
and start bit sequence, the MT88E39 outputs a fixed
frequency clock string of 8 pulses at the DCLK pin.
Each DCLK rising edge occurs in the nominal centre

2

of a data bit. DCLK is not generated for the stop and
start bits. Consequently, DCLK will clock only valid
data into a peripheral device such as a serial to
parallel shift register or a microcontroller. The
MT88E39 also outputs an end of word pulse (Data
Ready) on the DR pin, which indicates the reception
of every 10-bit word (counting the start and stop bits)
sent from the end office. DR can be used to interrupt
a microcontroller or cause a serial to parallel
converter to parallel load its data into a
microcontroller. The mode 0 DATA pin can also be
connected to a personal computer’s serial
communication port after converting from CMOS to
RS-232 voltage levels.

V

VOLTAGE GAIN

) = RF / R

(A

V

IN

Ref

MT88E39

Figure 4 - Single-Ended Input

Configuration

3-wire FSK Data Interface

The MT88E39 provides a powerful dual mode 3-wire
interface so that the 8-bit data words in the
demodulated FSK bit stream can be extracted
without the need either for an external UART or for
the microcontroller to perform the UART function in
software. The interface is specifically designed for
the 1200 baud rate and is comprised of the DATA,
DCLK (data clock) and DR (data ready) pins. Two
modes (0 and 1) are selectable via control of the
device’s MODE pin. In mode 0 the FSK bit stream is
output as demodulated. In mode 1 the FSK data byte
is store in a 1 byte buffer. Note that in mode 0 DR
and CD are open drain outputs; in mode 1 they are
CMOS outputs. DCLK is an output in mode 0, an
input in mode 1.

Mode 1

This mode is selected when the MODE pin is high. In
this mode, the microcontroller supplies read pulses
at the DCLK pin (which is now an input) to shift the
8-bit data words out of the MT88E39, onto the DATA
pin. The MT88E39 asserts DR to denote the word
boundary and indicate to the microprocessor that a
new word has become available (see Figure 12).

Internal to the MT88E39, the demodulated data bits
are sampled and stored. The start and stop bits are
stripped off. After the 8th bit, the data byte is parallel
loaded into an 8 bit shift register and DR goes low.
The shift register’s contents are shifted out to the
DATA pin on the supplied DCLK’s rising edge in the
order they were received.

If DCLK begins while DR is low, DR will return to high
upon the first DCLK. This feature allows the
associated interrupt to be cleared by the first read
pulse. Otherwise DR is low for half a nominal bit time
(1/2400 sec). After the last bit has been read,
additional DCLKs are ignored.

5-4

Note that in both modes, the 3-pin interface may also
output data generated by speech or other voiceband

Advance Information MT88E39

signals. The user may choose to ignore these
outputs when FSK data is not expected, or force the
MT88E39 into its power down mode.

Power Down Mode

For applications requiring reduced power
consumption, the MT88E39 can be forced into power
down when it is not needed. This is done by pulling
the PWDN pin high. In power down mode, the
oscillator, op-amp and internal circuitry are all
disabled and the MT88E39 will not react to the input
signal. DR and CD are at high impedance or at logic
high (modes 0 and 1 respectively). In mode 0, DATA
and DCLK are at logic high. The MT88E39 can be
awakened for reception of the FSK signal by pulling
the PWDN pin low.

Carrier Detect

The carrier detector provides an indication of the
presence of a signal in the FSK frequency band. It
detects the presence of a signal of sufficient
amplitude at the output of the FSK bandpass filter.
The signal is qualified by a digital algorithm before
the CD output is set low to indicate carrier detection.
A 10ms hysteresis is provided to allow for
momentary signal drop out once CD has been
activated. CD is released when there is no activity at
the FSK bandpass filter output for 10 ms.

When CD is inactive (high), the raw output of the
demodulator is ignored by the data timing recovery
circuit (see Figure 1). In mode 0, the DATA pin is
forced high. No DCLK or DR signal is generated. In
mode 1, the internal shift register is not updated and
no DR is generated. If DCLK is clocked (in mode 1),
DATA is undefined.

The crystal specification is as follows:

Frequency:
Frequency tolerance:
Resonance mode

: Parallel

Load capacitance:
Maximum series resistance
Maximum drive level (mW):

3.579545 MHz
±0.2%(-40°C+85°C)

18 pF

: 150 ohms

2 mW

e.g. CTS MP036S

MT88E39 MT88E39 MT88E39

OSC1 OSC2 OSC1 OSC2

3.579545 MHz

OSC1 OSC2

to the

next MT88E39

(For 5V application only)

Figure 5 - Common Crystal Connection

For 5V applications any number of MT88E39 devices
can be connected as shown in Figure 5 such that
only one crystal is required. The connection between
OSC2 and OSC1 can be DC coupled as shown, or
the OSC1 input on all devices can be driven from a
CMOS buffer (dc coupled) with the OSC2 outputs left
unconnected.

V

and CAP Inputs

Ref

V

is the output of a low impedance voltage source

Ref

equal to V
A 0.1µF capacitor is required between CAP and V
to suppress noise on V

/2 and is used to bias the input op-amp.

DD

Ref.

SS

Applications

Note that signals such as CAS, speech and DTMF
tones also lie in the FSK frequency band and the
carrier detector may be activated by these signals.
They will be demodulated and presented as data. To
avoid false data, the PWDN pin should be used to
disable the FSK demodulator when no FSK signal is
expected.

Ringing, on the other hand, does not pose a problem
as it is ignored by the carrier detector.

Crystal Oscillator

The MT88E39 uses either a 3.579545MHz ceramic
resonator or crystal oscillator as the master timing
source.

Table 1 shows the Bellcore and ETSI FSK signal
characteristics. The application circuit in Figure 6 will
meet these requirements.

For 5V designs the input op-amp should be set to
unity gain to meet the Bellcore requirements and

-2.5 dB gain for ETSI requirements.

As supply voltage (VDD) is decreased, the FSK
detect threshold will be lowered. Therefore for
designs operating at other than 5V nominal voltage,
to meet the FSK reject level requirement the gain of
the op-amp should be reduced accordingly.

For 3V designs the gain settings for Bellcore and
ETSI should be -3dB and -5.5dB respectively.

5-5