MITEL MT8889CS-1, MT8889CE-1, MT8889CN, MT8889CN-1, MT8889CC Datasheet

...

MT8889C/MT8889C-1



Integrated DTMFTransceiver

with Adaptive Micro Interface

Features

• Central office quality DTMF transmitter/ receiver

• Low power c onsu mpt ion

• High speed ada ptiv e micr o interf ace

• Adjustable guard time

• Automat ic ton e burst mode

• Call prog ress ton e det ection t o -30dBm

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radio

• Interconn ect di alers

• Persona l comp uters

Description

The MT8889C is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability.

ISSUE 2 May 1995

Ordering Information

MT8889CE/CE- 1 20 Pin Plast ic D IP MT8889CC/CC-1 20 Pin Ceramic DIP MT8889CS/CS- 1 20 Pin SOI C MT8889CN/C N-1 24 Pin SSOP

-40°C to +85°C

The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones.

The MT8889C utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT8889C-1 is functionally identical to the MT8889C except the receiver is enhanced to accept lower level signals, and also has a specified low signal rejection level.

TONE

IN+

INGS

OSC1 OSC2

∑

Tone Burst Gating Cct.

DDVRefVSS

Tone Filter

Oscillator

Circuit

Bias

Circuit

Dial

D/A

Converters

Control

Logic

High Group

Filter

Low Group

Filter

Control

Logic

Row and

Column

Counters

Digital

Algorithm and Code Converter

Steerin g

Logic

ESt St/GT

Transmit Data

Status

Control

Receive Data

Figure 1 - Functional Block Diagram

Data

Bus

Buffer

Interrupt

Logic

I/O

Control

D0 D1 D2 D3

IRQ

/CP

DS/RD CS R/W/WR RS0

4-107

MT8889C/MT8889C-1

IN+

IN-

4 5

6 7 8 9

VRef

VSS OSC1 OSC2

TONE

/WR

R/W

20 PIN CERDIP/PLASTIC DIP/SOIC

20 19 18 17 16 15 14 13 12 11

VDD St/GT ESt D3 D2 D1 D0 IRQ DS/RD RS0

/CP

R/W

IN+

IN-

VRef

VSS OSC1 OSC2

NC NC

TONE

/WR

1 2

3 4

5 6

7 8

9 10 11 12

24 PIN SSOP

24 23 22 21 20 19 18 17 16 15 14 13

VDD St/GT ESt D3 D2 D1 D0 NC NC

/CP

IRQ DS/RD RS0

Figure 2 - Pin Connections

Pin Description

Pin #

20 24

11 IN+Non-inverting op-am p input. 22 IN- In vertin g op-am p input. 33 GSGain Select. Gives access to output of front end differential amplifier for co nnecti on of

44 V 55 V 66OSC1Oscillator input. This pin can also be driven directl y by an external clock.

Name Description

feedback resistor. Reference Vo ltage output (VDD/2).

Ref

Ground (0V).

77OSC2Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes

the internal oscillator circuit. Leave open circuit when OS C1 is driven externally. 8 10 TONE Output from internal DTMF transmitter. 911 R/W

)

(WR

10 12 CS

Chip Select input. This signal must be quali fie d externally by either address strobe (AS),

or (Intel) Write microprocessor input. TTL compatible.

(Motorola) Read/Write

valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.

11 13 RS0 Register Selec t input. Refer to Table 3 for bit interpretation. TTL compatible. 12 14 DS (RD

) (Motorola) Data Strobe or (Intel) Read microprocessor input. Act ivity on this input is only

required when the device is being accessed. TTL compatible.

13 15 IRQ

/CP Interrupt Request/Call Progress (ope n drain) outpu t. In interrupt mode, this output goes

low when a valid DTMF tone burst has been transmitted or received. In call progress mode,

this pin will output a rectangular signal representative of the input signal applied at the input

op-amp. The input signal must be within the bandwidth lim it s of the call progress filte r, see

Figure 8.

14-1718-21D0-D3 Microprocessor data bus. High impedance when CS

= 1 or DS =0 (Motorola) or RD = 1

(Intel). TTL compatible.

18 22 ESt Early Steering output. Present s a logic high once the digital algo rithm has detected a valid

tone pair (signal condition). Any moment ary loss of signal con dition will cause ESt to return

to a logic low.

19 23 St/GT Steering Input/Guard Time output (bidirect ional ). A voltage great er than V

detected at

TSt

St causes the device to register the detected tone pair and updat e the output latch. A

voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-const ant; its stat e is a function of ESt and the volt age on St.

20 24 V

8,9 16,

4-108

Positive power supply (5V typ.).

NC No Connection.

Functional Description

MT8889C/MT8889C-1

The MT8889C/MT8889C-1 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the MT8889C/MT8889C-1 internal registers.

Input Configuration

The input arrangement of the MT8889C/MT8889C-1 provides a differential-input operational amplifier as well as a bias source (V inputs at V

/2. Provision is made for connection of

a feedback resistor to the op-amp output (GS) for gain adjustment. In a single-ended configuration, the input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a differential input configuration.

), which is used to bias the

Ref

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF R1 = R4 = R5 = 100 kΩ R2 = 60kΩ, R3 = 37.5 kΩ R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) - R5/R1

INPUT IMPEDANCE

diff) = 2 R12 + (1/ωC)

IN+

IN-

Ref

MT8889C/ MT8889C-1

Receiver Se ction

Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

IN+

VOLTAGE GAIN

) = RF / R

Figure 3 - Single-Ended Input Configuration

IN-

Ref

MT8889C/ MT8889C-1

Figure 4 - Differential Input Configuration

LOW

HIGH

DIGIT D

697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 A 1 1 0 1 770 1633 B 1 1 1 0 852 1633 C 1 1 1 1 941 1633 D 0 0 0 0

0= LOGIC LOW, 1= LOGIC HIGH

Table 1. Functional Encode/Decode Table

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MT8889C/MT8889C-1

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state.

MT8889C/ MT8889C-1

St/GT

ESt

= (R1C1) In (VDD / V

GTA

= (R1C1) In [VDD / (VDD-V

GTP

Figure 5 - Basic Steering Circuit

Guard Time Adjustment

TSt

)

)]

TSt

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes v rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (t (V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1) into the Receive D ata Regist er. At thi s point the GT output is activated and drives v continues to drive high as long as ESt remains high. Finally, after a short de lay to a ll ow th e o ut put latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ

/CP pin will pull low when the

delayed steering f l ag is activ e.

The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

(see Figure 5) to

to VDD. GT

The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7):

≥ t

REC

≤ t

REC

tID ≥ t

tDO ≤ t

DAmax

DPmax

DPmin

DAmin

+ t + t + t + t

GTPmax

GTPmin

GTAmax

GTAmin

- t

DAmin

DAmax

DPmin

DPmax

The value of tDP is a device parameter (see AC Electrical Characteristics) and t

is the minimum

REC

signal duration to be recognized by the receiver. A value for C1 of 0.1 µF is recommended for most

St/GT

ESt

St/GT

ESt

= (RPC1) In [VDD / (VDD-V

GTP

= (R1C1) In (VDD/V

GTA

= (R1R2) / (R1 + R2)

a) d ecrea sing tGTP; (tGTP < tGTA)

= (R1C1) In [VDD / (VDD-V

GTP

= (RpC1) In (VDD/V

GTA

= (R1R2) / (R1 + R2)

b) decreasing tGTA; (tGTP > tGTA)

TSt

)]

)

)]

)

Figure 6 - Guard Time Adjustment

4-110

MT8889C/MT8889C-1

AAAA

applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (t tone absent (t

) guard times. This may be

GTA

GTP

) and

necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity.

Increasing t

improves talk-off performance since

REC

it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short t

with a long tDO would be appropriate for

REC

extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 9.

Call Progress Filter

A call progress mode, using the MT8889C/ MT8889C-1, can be selected allowing the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF input are common, however, call progress tones can only be detected when CP

mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table

7). Figure 8 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the ‘accept’ bandwidth limits of the filter, are hard-limited by a high gain comparator with the IRQ

/CP pin serving as the output. The squarewave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the ‘reject’ area will not be detected and consequently the IRQ

LEVEL

(dBm)

-25

0 250 500 750

= Reject = May Accept

AAA

AAAA

= Accept

AAA

/CP pin will remain low.

AAAA

AAA

AAAA

FREQUENCY (Hz)

Figure 8 - Call Progress Response

EVENTS

ESt

St/GT

-RX

Read Status Register

/CP

IRQ

ABCDEF

REC

TONE #n

GTP

DECODED TONE # (n-1)

PStRX

PStb3

# n

TONE #n + 1

GTA

TONE #n + 1

TSt

# (n + 1)

Figure 7 - R ece iver Tim ing Diag ram

4-111

MT8889C/MT8889C-1

EXPLANATION OF EVENTS

A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DE TECTED, TONE A BSENT DURATION VALID, INFORMATION IN RX DATA REGISTER

EXPLANATION OF SYMBOLS

ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX

b3 DEL AYED STEERING. INDICATES THAT VALID FREQUENCIES H AVE BEEN PRESENT/ABSENT FOR THE

b2 INDICATES THAT VALID DATA IS IN THE RECEIVE DATA RE GISTER. THE BIT IS CLEARED A FTER THE STATUS

IRQ

REC

GTP

GTA

RETAINED UNTIL NEXT VALID TONE PAIR.

DTMF COMPOSITE INPUT SIG NAL.

-RX34-BIT DECODED DATA IN RE CEIVE DATA REGISTER

REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. ACTIVE LOW FOR THE DURATION OF A VALID DTMF SIGNAL.

/CP INTERRUPT IS ACTIVE INDICATING THAT NEW DATA IS IN THE RX DATA REGISTER. THE INTERRUPT IS

CLEARED AFTER THE STATUS REGISTER IS R EAD.

MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. MINIMUM TIME BET WEEN VALID SEQUENTI AL D TMF SIG NAL S. MAXIMUM ALLOWABLE DROPOUT DURING VALID DTMF SIGNAL. TIME TO DETECT VALID FREQUENCIES PRESENT. TIME TO DETECT VALID FREQUENCIES ABSENT. GUARD TIME, TO NE PR ESEN T. GUARD TIME, TO NE ABSEN T.

Figur e 9 - De scri pt ion of Tim in g Ev en ts

DTMF Generator

The DTMF transmitter employed in the MT8889C/ MT8889C-1 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered providing a DTMF signal with low total harmonic distortion and high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that this is the same as the receiver output code. The individual tones which are generated (f Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to compensate for high group attenuation on long loops.

The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During

LOW

and f

) are referred to as Low

HIGH

write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM.

The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summing amplifier. The oscillator described needs no “start-up” time as in other DTMF generators since the crystal oscillator is running continuously thus providing a high degree of tone burst accuracy. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. It can be seen from Figure 6 that the distortion products are very low in amplitude.

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