MITEL MT8880CC-1, MT8880CS-1, MT8880CC, MT8880CS, MT8880CP Datasheet



ISO2-CMOS

MT8880C/MT8880C-1

Integrated DTMFTransceiver

Features

• Complete DTMF transmitter/receiver

• Centr al office qualit y

• Low pow er co nsump tion

• Micropro cesso r por t

• Adjustable guard time

• Automa tic ton e bu rst mode

• Call prog ress m ode

Applications

• Credit card systems

• Paging systems

• Repeater systems/mobile radi o

• Interco nnect dial ers

• Persona l comp uters

Description

ISSUE 2 May 1995

Ordering Information

MT8880CE/CE-1 20 Pin Plastic DIP
MT8880CC/CC-1 20 Pin Ceramic DIP
MT8880CS/CS-1 20 Pin SOIC
MT8880CN/C N-1 24 Pin SSO P
MT8880CP/CP-1 28 Pin Plastic LCC

-40°C to +85°C

based upon the industry standard MT8870
monolithic DTMF receiver; the transmitter utilizes a
switched capacitor D/A converter for low distortion,
high accuracy DTMF signalling. Internal counters
provide a burst mode such that tone bursts can be
transmitted with precise timing. A call progress filter
can be selected allowing a microprocessor to
analyze call progress tones. A standard
microprocessor bus is provided and is directly
compatible with 6800 series microprocessors. The
MT8880C-1 is functionally identical to the MT8880C
except for the performance of the receiver section,
which is enhanced to accept and reject lower signal
level s.

The MT8880C/C-1 is a monolithic DTMF transceiver
with call progress filter. It is fabricated in Mitel’s

2

ISO

-CMOS technology, which provides low power

dissipation and high reliability. The DTMF receiver is

Row and

Column

Counters

Digital
Algorithm
and Code
Converter

Steering

Logic

ESt St/GT

TONE

IN+

IN-

GS

OSC1
OSC2

∑

Tone Burst

Gating Cct.

+

-

V

DDVRefVSS

Tone
Filter

Oscillator

Circuit

Bias

Circuit

D/A

Converters

Control

Logic

Dial

High Group

Filter

Low Group

Filter

Control

Logic

Figure 1 - Functional Block Diagram

Transmit Data

Register

Status

Register

Control

Register

A

Control

Register

B

Receive Data

Register

Data

Bus

Buffer

Inter rupt

Logi c

I/O

Control

D0
D1
D2
D3

IRQ

Φ2
CS
R/W
RS0

/CP

4-33

MT8880C/MT8880C-1 ISO

1

IN+

2

IN-

3

GS

VRef

VSS
OSC1
OSC2
TONE

R/W

4
5

6
7
8
9

CS

10

20 PIN CERDIP/PLASTIC DIP/SOIC

20
19
18
17
16
15
14
13
12
11

VDD
St/GT
ESt
D3
D2
D1
D0
IRQ
Φ2
RS0

/CP

IN+

IN-

GS

VRef

VSS
OSC1
OSC2

NC
NC

TONE

R/W

CS

2

-CMOS

1
2

3
4
5

6
7
8

9
10
11
12

24 PIN SSOP

24
23
22
21
20
19
18
17
16
15
14
13

VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ
Φ2
RS0

/CP

NC

VRef

VSS
OSC1
OSC2

NC
NC

5
6
7
8
9
10
11

S
G

4

2

1

E
N
O
T

T

D

G

+

-

C
N

3

3

1

W

/
R

28 PIN PLCC

/

t

D

N

N

I

S

V

I

2

1

8

2

•

4

5

7

6

1

1

1

1

0

S

C

S

C

N

R

T
S
E

7

6

2

2

NC

25

NC

24

NC

23

D3

22

D2

21

D1

20
19

D0

8

1

2

P

Φ

C

/
Q
R

I

Figure 2 - Pin Connections

Pin Description

Pin #

20 24 28

1 1 1 IN+ Non-inverting op-amp input.
2 2 2 IN- Inverting op-amp input.
334 GSGain Select. Give s access to output of front end differential am plif ier for connection of

446V
557V
6 6 8 OSC1 DTMF clock/oscillator input.
7 7 9 OSC2 Clock output. A 3.579545 MHz crystal connected between OSC1 and OSC2 com plet es the

81012TONETone output (DTMF or single tone).
91113R/W

10 12 14 CS
11 13 15 RS0 Register Select input. See register decode table. TTL compatible.
12 14 17 Φ2 System Cloc k input . TTL co mpa tib le. N.B. Φ2 clock input need not be active when the

13 15 18 IRQ

14-1718-2119-22D0-D3 Microprocessor Data Bus (TTL compatible). High impedance when CS

Name Description

feedback resistor.
Reference Voltage output, nominally VDD/2 is used to bias inputs at mid-rail (see Fig. 13).

Ref

Ground input (0V).

SS

internal oscillator circuit. Leave open circuit when OS C1 is clock input.

Read/Write input. Cont ro ls the directi on of data transf er to and from the MPU an d the
transceiver registers. TTL compa tible.

Chip Select, TT L input (CS=0 t o select the chip).

device is not being accessed.

/CPInterrupt Request to MPU (open drain out put ). Also, when call progress (CP) mode has

been selected and interrupt enabled the IRQ/CP pin will output a rectangular wave signal
representative of the input signal applied at the input op-amp. The input signal must be within
the bandwidth limits of the call progress filter. See Figure 8.

= 1 or Φ2 is low.

18 22 26 ESt Early Steering outp ut. Presents a logic high once the digi tal algorit hm has detected a valid

tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.

19 23 27 St/GT Steering Input/Guard Time output (bidirection al). A voltage greater tha n V

causes the device to register the detected tone pair and upda te the output latch. A voltage

20 24 28 V

8,9

3,5,

16,

10,

17

11,
16,
23-

25

4-34

less than V
external steering time-constant; its state is a function of ESt and the voltage on St.

Positive power supply input (+5V typical).

DD

NC No Connect ion.

frees the device to accept a new tone pair. The GT output acts to reset the

TSt

detected at St

TSt

ISO

Functional Description

The MT8880C/C-1 Integrated DTMF Transceiver
architecture consists of a high performance DTMF
receiver with internal gain setting amplifier and a
DTMF generator which employs a burst counter such
that precise tone bursts and pauses can be
synthesized. A call progress mode can be selected
such that frequencies within the specified passband
can be detected. A standard microprocessor
interface allows access to an internal status register,
two control registers and two data registers.

Input Configuration

2

-CMOS MT8880C/MT8880C-1

C1

C2

R1

R4

R3

R5

R2

IN+

IN-

GS

V

Ref

The input arrangement of the MT8880C/C-1 provides
a differential-input operational amplifier as well as a
bias sou rce (V
V

/2. Provision is made for connection of a

DD

) which is used to bias the inputs at

Ref

feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 3.

Figure 4 shows the necessary connections for a
differential input configuration.

IN+

C

VOLTAGE GAIN

(A

) = RF / R

V

IN

R

IN

R

F

IN-

GS

V

Ref

MT8880C/C-1

Figure 3 - Single-Ended Input Configuration

Receiver Se ction

Separation of the low and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies (see Fig. 7). These filters
also incorporate notches at 350 Hz and 440 Hz for
exceptional dial tone rejection. Each filter output is
followed by a single order switched capacitor filter
section which smooths the signals prior to limiting.
Limiting is performed by high-gain comparators

MT8880C/C-1

DIFFERENTIAL INPUT AMPLIFIER

C1 = C2 = 10 nF
R1 = R4 = R5 = 100 kΩ
R2 = 60kΩ, R3 = 37.5 kΩ
R3 = (R2R5)/(R2 + R5)

VOLTAGE GAIN

diff) = R5/R1

(A

V

INPUT IMPEDANCE

(Z

diff) = 2 R12 + (1/ωC)

IN

2

Figure 4 - Differential Input Configuration

which are provided with hysteresis to prevent
detection of unwanted low-level signals. The outputs
of the comparators provide full rail logic swings at
the frequencies of the incoming DTMF signals.

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while
providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the “signal condition” in
some industry specifications) the “Early Steering”
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive s tate .

4-35

MT8880C/MT8880C-1 ISO

2

-CMOS

Steering Circuit

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v
rise as the capacitor discharges. Provided that the
signal condition is maintained (ESt remains high) for
the validation period (t
(V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Figure 7)
into the Receive D ata Regist er. At this point t he GT
output is activated and drives v
continues to drive high as long as ESt remains high.
Finally, after a short de lay to a ll ow th e o ut put latch to
settle, the delayed steering output flag goes high,
signalling that a received tone pair has been
registered. The status of the delayed steering flag
can be monitored by checking the appropriate bit in
the status register. If Interrupt mode has been
selected, the IRQ

/CP pin will pull low when the

delayed steering f l ag is activ e.

(see Figure 5) to

c

to VDD. GT

c

Guard Time Adjustment

The simple steering circuit shown in Figure 5 is
adequate for most applications. Component values
are chosen according to the formula:

t

= tDP+t

REC

tID=tDA+t

The value of tDP is a device parameter (see AC
Electrical Characteristics) and t
signal duration to be recognized by the receiver. A
value for C1 of 0.1 µF is recommended for most
applications, leaving R1 to be selected by the
designer. Different steering arrangements may be
used to select independently the guard times for tone
present (t

) and tone absent (t

GTP

necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters such
as talk off and noise immunity.

GTP

GTA

is the minimum

REC

). This may be

GTA

The contents of the output latch are updated on an
active delayed steering transition. This data is
presented to the four bit bidirectional data bus when
the Receive Data Register is read. The steering
circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver
will tolerate signal interruptions (drop out) too short
to be considered a valid pause. This facility, together
with the capability of selecting the steering time
constants externally, allows the designer to tailor
performance to meet a wide variety of system
requirements.

V

DD

V

DD

St/GT

ESt

R1

C1

Vc

V

DD

St/GT

ESt

V

DD

St/GT

R1

= (RPC1) In [VDD / (VDD-V

t

GTP

t

= (R1C1) In (VDD/V

GTA

R

= (R1R2) / (R1 + R2)

P

C1

R2

a) decreasing tGTP; (tGTP < tGTA)

= (R1C1) In [VDD / (VDD-V

t

GTP

= (RpC1) In (VDD/V

t

GTA

= (R1R2) / (R1 + R2)

R

P

C1

TSt

TSt

TSt

TSt

)]

)

)

)

MT8880C/C-1

4-36

t

= (R1C1) In (VDD / V

GTA

t

= (R1C1) In [VDD / (VDD-V

GTP

TSt

)

Figure 5 - Basic Steering Circuit

TSt

R1

)]

ESt

R2

b) decreasing tGTA; (tGTP > tGTA)

Figure 6 - Guard Time Adjustment

ISO

AAAA

AAAA

A

A

A

A

AAAA

A

A

A

AA

2

-CMOS MT8880C/MT8880C-1

Increas ing t

improves talk-off performance since

REC

it reduces the probability that tones simulated by
speech will maintain a valid signal condition long
enough to be registered. Alternatively, a relatively
short t

with a long tDO would be appropriate for

REC

extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required.
Design information for guard time adjustment is
shown in Figure 6. The receiver timing is shown in
Figure 9 with a description of the events in Figure 11.

Call Progress Filter

A call progress mode, using the MT8880C/C-1, can
be selected allowing the detection of various tones
which identify the progress of a telephone call on the
network. The call progress tone input and DTMF
input are common, however, call progress tones can
only be detected when CP mode has been selected.
DTMF signals cannot be detected if CP mode has
been selected (see Table 5). Figure 8 indicates the
useful detect bandwidth of the call progress filter.
Frequencies presented to the input, which are within
the ‘accept’ bandwidth limits of the filter, are hard­limited by a high gain comparator with the IRQ

/CP
pin serving as the output. The squarewave output
obtained from the schmitt trigger can be analyzed by
a microprocessor or counter arrangement to
determine the nature of the call progress tone being
detected. Frequencies which are in the ‘reject’ area
will not be detected and consequently the IRQ

/CP
pin will remain low.

DTMF Generat or

F

LOW

F

HIGH

DIGIT D

D

D

3

2

D

1

0

6971209 1 0001
6971336 2 0010
6971477 3 0011
7701209 4 0100
7701336 5 0101
7701477 6 0110
8521209 7 0111
8521336 8 1000
8521477 9 1001
9411336 0 1010
9411209 * 1011
9411477 # 1100
6971633 A 1101
7701633 B 1110
8521633 C 1111
9411633 D 0000

0= LOGIC LOW, 1= LOGIC HIGH

Figure 7 - Functional Encode/Decode Table

LEVEL

(dBm)

The DTMF transmitter employed in the MT8880C/C­1 is capable of generating all sixteen standard DTMF
tone pairs with low distortion and high accuracy. All
frequencies are derived from an external 3.579545
MHz crystal. The sinusoidal waveforms for the
individual tones are digitally synthesized using row
and column programmable dividers and switched
capacitor D/A converters. The row and column tones
are mixed and filtered providing a DTMF signal with
low total harmonic distortion and high accuracy. To
specify a DTMF signal, data conforming to the
encoding format shown in Figure 7 must be written to
the transmit Data Register. Note that this is the same
as the receiver output code. The individual tones
which are generated (f

LOW

and f

) are referred to

HIGH

as Low Group and High Group tones. As seen from
the table, the low group frequencies are 697, 770,
852 and 941 Hz. The high group frequencies are
1209, 1336, 1477 and 1633 Hz. Typically, the high
group to low group amplitude ratio (pre-emphasis) is
2dB to compensate for high group attenuation on
long loops.

AAA

AAAA

AAAA

AAA

AAAA

-25

AAA

AAA

AAAA

AAAA

AAAA

AAAA

AAAA

0 250 500 750

FREQUENCY (Hz)

= Reject
= May Accept

AAA

AAAA

A

AAA

AAAA

A

AAAA

= Accept

A

AAA

Figure 8 - Call Progress Response

The period of each tone consists of 32 equal time
segments. The period of a tone is controlled by
varying the length of these time segments. During
write operations to the Transmit Data Register the 4
bit data on the bus is latched and converted to 2 of 8
coding for use by the programmable divider circuitry.
This code is used to specify a time segment length
which will ultimately determine the frequency of the
tone. When the divider reaches the appropriate
count, as determined by the input code, a reset pulse
is issued and the counter starts again. The number

4-37

MT8880C/MT8880C-1 ISO

2

-CMOS

EVENTS

V

in

ESt

St/GT

RX

-RX

0

b3

b2

Read
Status
Register

/CP

IRQ

ABCDEF

t

t

REC

t

DP

3

DECODED TONE # (n-1)

REC

TONE #n

t

GTP

t

PStRX

t

PStb3

t

ID

# n

t

DO

TONE
#n + 1

t

DA

t

GTA

TONE
#n + 1

# (n + 1)

V

TSt

Figure 9 - R ece iver Tim ing Diag ram

of time segments is fixed at 32, however, by varying
the segment length as described above the tone
output signal frequency will be varied. The divider
output clocks another counter which addresses the
sinewave lookup ROM.

The lookup table contains codes which are used by
the switched capacitor D/A converter to obtain
discrete and highly accurate DC voltage levels. Two
identical circuits are employed to produce row and

column tones which are then mixed using a low
noise summing amplifier. The oscillator described
needs no “start-up” time as in other DTMF
generators since the crystal oscillator is running
continuously thus providing a high degree of tone
burst accuracy. A bandwidth limiting filter is
incorporated and serves to attenuate distortion
products above 8 kHz. It can be seen from Figure 10
that the distortion products are very low in amplitude.

Scaling Information

10 dB/Div
Start Frequency = 0 Hz
Stop Frequency = 3400 Hz
Marker Frequency = 697 Hz and
1209 Hz

4-38

Figure 10 - Spectrum Plot