MITEL MT8870DS-1, MT8870DT, MT8870DT-1, MT8870DN-1, MT8870DC Datasheet

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ISO2-CMOS

MT8870D/MT8870D-1

Integrated DTMF Receiver

Features

• Complet e DTMF R eceiv er

• Low power co nsu mptio n

• Internal gai n sett ing a mplif ier

• Adjustable guard time

• Central office qua lity

• Power-down m ode

• Inhibit m o de

• Backward compatible with MT8870C/M T88 70C -1

Applications

• Receiver system for British Telecom (BT) or CEPT Spec (MT8870 D-1)

• Paging systems

• Repeater systems/mobile radio

• Credit card systems

• Remote con trol

• Personal com put ers

• Telephone ans werin g mach in e

ISSUE 3 May1995

Ordering Information

MT8870DE/DE-1 18 Pin Plastic DIP MT8870DC/DC-1 18 Pin Ceramic DIP MT8870DS/DS-1 18 Pin SOIC MT8870DN/D N-1 20 Pin SSOP MT8870DT /DT-1 20 Pin TSS OP

-40 °C to +85 °C

Descript io n

The MT8870D/MT8870D-1 is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tonepairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.

PWDN

IN +

IN -

VDD VSS VRef INH

Bias

Circuit

Chip

Power

Bias

Dial Tone Filter

OSC1 OSC2 St/GT ESt STD TOE

High Group

Filter

Low Group

Filter

to all Chip Clocks

VRef Buffer

Zero Crossing Detectors

Digital Detection Algorithm

St GT

Steering Logic

Code Converter and Latch

Figure 1 - Functional Block Diagram

4-11

MT8870D/MT8870D-1 ISO

-CMOS

IN+

IN-

INH

4 5

6 7 8 9

VRef

PWDN

OSC1 OSC2

VSS

18 PIN CERDIP/PLASTIC DIP/S OIC

18 17 16 15 14 13 12 11 10

VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE

IN+

IN-

VRef

INH

PWDN

NC OSC1 OSC2

VSS

1 2

3 4 5

6 7 8 9

20 PIN SSOP/TSSOP

20 19 18 17 16 15 14 13 12 11

VDD St/GT ESt StD NC

Q4 Q3 Q2 Q1 TOE

Figure 2 - Pin Connections

Pin Description

Pin #

18 20

11 IN+ Non-Inverting Op-Amp (Input). 2 2 IN- Inverting Op-Amp (Input). 33 GS Gain Select. Gives access to output of front end differential amplifier for connection of

44 V

Name Description

feedback resistor. Reference Voltage (Output). Nominall y VDD/2 is used to bias inputs at mid-rail (see Fig. 6

Ref

and Fig. 10).

55 INH Inhibit (Input). Logi c high inhibi ts the det ection of tones repre senti ng chara cters A, B, C

and D. This pin input is internally pulled down.

66PWDNPower Down (Input). A ctive high. Powers down the device and inhi bits the oscillat or. This

pin input is internally pulled do wn. 78 OSC1Clock (Input). 89 OSC2Clock (Output). A 3.579545 MHz crystal connect ed between pins OS C1 and OS C2

completes the internal oscillator ci r cuit. 910 V

Ground (Inpu t). 0V typical.

10 11 TOE Th ree S tate Outpu t Ena ble (Inp ut). Log ic high enables th e outpu ts Q1-Q4. This pin is

pulled up internally.

11-1412-15Q1-Q4 Three State Data (Outpu t). When enabled by TOE, provide the code corresponding to the

last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high

impedance.

15 17 StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been

registered and the output latch updated; returns to logic low when t he voltage on St/GT falls

below V

TSt

16 18 ESt Early Steering (Output). Prese nts a logic high once the digit al algorit hm has detect ed a

valid tone pair (signal condition ). Any mome ntary loss of signal conditio n will cause ESt to

return to a logic low.

17 19 St/GT Steering Input/Guard time (Output) Bidirectional. A voltage greater than V

detected at

TSt

St causes the device to register the detected tone pair and update the output latch . A

voltage less than V

frees the device to accept a new tone pair. The GT output acts to

TSt

reset the external steering time-constant ; its state is a function of ESt and the voltage on St.

18 20 V

4-12

Positive power supply (Input). +5V typical .

NC No Connection.

ISO

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Functional Descripti on

The MT8870D/MT8870D-1 monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus.

-CMOS MT8870D/MT8870D-1

St/GT

ESt

StD

Filter Section

Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection (see Figure 3). Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.

Decoder Section

Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by ex traneous signals su ch as voice whi le

MT8870D/

MT8870D-1

=(RC)In(VDD/V

GTA

=(RC)In[VDD/(VDD-V

GTP

TSt

)

)]

TSt

Figure 4 - B asic Steer ing Circ uit

providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the “signal condition” in some industry specifications) the “Early Steering” (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an in ac tive s ta te ( see “S te er in g Cir cu it”) .

Steering Circuit

Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt caus es v

(see Figure 4) to

rise as the capacitor discharges. Provided signal

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PRECISE DIAL TONES

X=350 Hz Y=440 Hz

DTMF TONES

ATTENUATION

(dB)

A=697 Hz B=770 Hz C=852 Hz D=941 Hz E=1209 Hz F=1336 Hz G=1477 H z H=1633 H z

1kHz

XY ABCD

EF G H

FREQUENCY (Hz)

Figure 3 - Filter Response

4-13

MT8870D/MT8870D-1 ISO

-CMOS

condition is maintained (ESt remains high) for the validation period (t (V

) of the steering logic to register the tone pair,

TSt

), vc reaches the threshold

GTP

latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives v

to VDD. GT continues to drive

high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.

Guard Time Adjustment

In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 4 is applicable. Component values are chosen according to the formula:

REC=tDP+tGTP

tID=tDA+t

GTA

The valu e of tDP is a device parameter (see Figure

11) and t

is the minimum signal duration to be

REC

recognized by the receiver. A value for C of 0.1 µF is

St/GT

ESt

St/GT

=(RPC1)In[VDD/(VDD-V

GTP

=(R1C1)In(VDD/V

a) decreasing t

GTP

GTA

=(R1R2)/(R1+R2)

; (t

GTP

=(R1C1)In[VDD/(VDD-V

=(RPC1)In(VDD/V

GTA

=(R1R2)/(R1+R2)

)]

TSt

)

TSt

GTP<tGTA

)]

TSt

)

TSt

)

Digit TOE INH ESt Q ANYLXHZZZZ

1HXH0001 2HXH0010 3HXH0011 4HXH0100 5HXH0101 6HXH0110 7HXH0111 8HXH1000 9HXH1001 0HXH1010

*HXH1011

#HXH1100 AHLH1101 BHLH1110 CHLH1111 DHLH0000 AHHL BHHL CHHL DHHL

undetected, the output code will remain the same as the previous detected code

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON‘T CARE

recommended for most applications, leaving R to be selected by the designer.

Different steering arrangements may be used to select independently the guard times for tone present (t

) and tone absent (t

GTP

). This may be

GTA

necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short t a long t

would be appropriate for extremely noisy

REC

with

environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 5.

4-14

ESt

b) decreasing t

Figure 5 - Guard Time Adjustment

GTA

; (t

GTP>tGTA

)

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