MITEL MH8980DC, MH8980DE, MH8980DL, MH8980DP Datasheet
2-3
Features
• Mitel ST-BUS compatibl e
• 8-line x 32-c hanne l inpu ts
• 8-line x 32-c hanne l outpu ts
• 256 ports non-blocking switch
• Single power s upp ly (+5 V )
• Low power co nsu mpt ion: 30 m W Typ.
• Microprocess o r-c on t rol i nterface
• Three-state serial outputs
Description
This VLSI ISO-CMOS device is designed for
switching PCM-encoded voice or data, under
microprocessor control, in a modern digital
exchange, PBX or Central Office. It provides
simultaneous connections for up to 256 64 kbit/s
channels. Each of the eight serial inputs and outputs
consist of 32 64 kbit/s channels multiplexed to form a
2048 kbit/s ST-BUS stream. In addition, the MT8980
provides microprocessor read and write access to
individual ST-BUS channels.
Figure 1 - Functional Block Diagram
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
CS
R/W A5/A0DTA D7/
D0
CSTo
C4i
F0i
VDDV
SS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
DS
ISSUE 6 May 1995
MT8980D
Digital Switch
ISO-CMOS ST-BUS FA MILY
Ordering Information
MT8980DC 40 Pin Ceramic DIP
MT8980DE 40 Pin Plastic DIP
MT8980DP 44 Pin PLCC
MT8980DL 44 Pin QFP
-40°C to +85°C
MT8980D
2-4
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
40
DIP44PLCC44QFP
1240DTAData Acknowledgeme nt (Open Drain Outpu t). This is the data acknowled gem ent
on the microprocessor interface. This pin is pulled low to signal that the chip has
processed the data. A 909 Ω, 1/4W, resistor is recommended to be used as a pullup.
2-4 3-5 41-43STi0-
STi2
ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input
streams.
5-9 7-11 1-5 STi3-
STi7
ST-BUS Input 3 to 7 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input
streams.
10 12 6 V
DD
Power Inpu t. Positive Supply.
11 13 7 F0i
Framing 0-Type (Input). This is the input for the frame synchronization pulse
for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter
to reset on
the next negative transit ion of C4i.
1
65432
4443424140
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
23
1819202122
2425262728
17
29
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
STi1
DTA
ODE
STo1
NC
NC
A4
DS
CS
D6
NC
A3
A5
R/W
D7
D5
44 PIN PLCC
DTA
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
A3
A4
A5
DS
CSTo
ODE
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
R/W
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40 PIN CERDIP/PLASTIC DIP
STi2
STi0
CSTo
STo0
STo2
39
4443424140
3837363534
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
17
1213141516
1819202122
11
23
44 PIN QFP
STi3
STi4
STi5
STi6
STi7
VDD
F0i
C4i
A0
A1
A2
NC
A4
DS
CS
D6
NC
A3
A5
R/W
D7
D5
STo3
STo4
STo5
STo6
STo7
VSS
D0
D1
D2
D3
D4
NC
STi1
DTA
ODE
STo1
NC
STi2
STi0
CSTo
STo0
STo2
MT8980D
2-5
12 14 8 C4i 4. 096 M H z Clock (Inpu t ). ST-BUS bit cell boundaries lie on the alternat e falling
edges of this clock.
13-1515-179-11 A0-A2 Address 0 to 2 (Inputs). These are the inputs for th e address lines on the
microprocessor interface.
16-1819-2113-15A3-A5 Addres s 3 to 5 (Inputs). These are the inputs for th e address lines on the
microprocessor interface.
19 22 16 DS Data Strob e (Inp ut). This is the input for the active high data strobe on the
microprocessor interface.
20 23 17 R/W
Read or Write (Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.
21 24 18 CS
Chip Select (Input). This is the input for the active low chip select on the
microprocessor interface
22-2425-2719-21D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirection al data pins on the
microprocessor interface.
25-2929-3323-27D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirection al data pins on the
microprocessor interface.
30 34 28 V
SS
Power Inpu t. Negative Supply (Ground).
31-3535-3929-33STo7-
STo3
ST-BUS Output 7 to 3 (Three-state Outputs). These are the pins for the eight 2048
kbit/s ST-BUS output streams.
36-3841-4335-37STo2-
STo0
ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the eight 2048
kbit/s ST-BUS output streams.
39 44 38 ODE Output Drive Enable (Input). If this input is held high, the STo0-STo7 output drivers
function normally. If this input is low, the STo0-STo7 output drivers go into their high
impedance state . NB: Even when ODE is high, channels on the STo0-STo7 outputs
can go high impedance under software control.
40 1 39 CSTo Control ST-BUS Output (Comp lemen tary Output). Each frame of 256 bits on this
ST-BUS output contains the values of bit 1 in the 256 locations of the Connection
Memory High.
6, 18,
28,
40
12,
22,
34,
44
NC No Connection.
Pin Description (continued)
Pin #
Name Description
40
DIP44PLCC44QFP
MT8980D
2-6
Functional Description
In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.
In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus). This bus
architectur e can be used both i n software-contr olled
digital voice and data switching, and for
interprocessor communications. The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.
The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
µs wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT8980 chip.
The MT8980 can switch data from channels on STBUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT8980 looks like a memory
peripheral. The microprocessor can write to the
MT8980 to establish switched connections between
input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output STBUS channels. By reading from the MT8980, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.
By integrating both switching and interprocessor
communications, the MT8980 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS architecture.
Hardware Descr iption
Serial data at 2048 kbit/s is received at the eight STBUS inputs (STi0 to STi7), and serial data is
transmitted at the eight ST-BUS outputs (STo0 to
STo7). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL’s
MT8964).
This serial input word is converted into parallel data
and stored in the 256 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams.
These locations can be read by the microprocessor
which controls the chip.
Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.
The Connection Memory data is received, via the
Control In terface, at D7 to D0. Th e Contr ol Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS
,
DTA
, R/W and DS. There are two parts to any
address in the Data Memory or Connection
Figure 3- Address Memory Map
A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION
0
1
1
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
0
•
•
•
1
X
0
1
•
•
•
1
00 - 1F
20
21
•
•
•
3F
Control Register *
Channel 0
†
Channel 1
†
•
•
•
Channel 31
†
* Writing to the Control Register is the only fast transaction.
†
Memory and stream are specified by the contents of the Control Regi ster.
MT8980D
2-7
Memory. The higher order bits come from the
Control Register, which may be written to or read
from via the Control Interface. The lower order bits
come from the address lines directly.
The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory and
writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT8980s to be constructed. It also controls the
CSTo pin.
All ST-BUS timing is derived from the two
signals C4i
and F0i.
Software Control
The address lines on the Control Interface give
access to the Control Register directly or, depending
on the co ntents of the Control Regi ster, to the High
or Low sections of the Connection Memory or to the
Data Mem o ry.
If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.
The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.
Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.
The other mode control bit , bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1, regardless
of the actual valu es.
Figure 4 - Control Register Bits
BIT NAME DESCRIPTION
7Split
Memory
When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, th e Stream
Address Bits select the subsection of the memory which is made available.
6 Message
Mode
When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.
5 (unused)
4-3 Memory
Select Bits
0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High
2-0 Stream
Address
Bits
The number expressed in binary notation on these bits refers to the input or output ST -BUS
stream which corresponds to the subsection of memor y made accessible for subsequent
operations.
76 543210
Mode
Control
Bits
(unuse d)
Memory
Select
Bits
Stream
Address
Bits
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