Mita-Kyocera FS5900C Electrical Circuit Description

6. Electrical Circuit Description

6.3 Basic engine functions

This section presents a general functional overview of the engine system of the printer. It was intended to
provide a comprehensive knowledge on basic functions that the engine system performs during printing.
The following printer functions are covered:

• Engine controller system

• Main logic controller system

• Paper feed system

• Power supply system

6.4 Engine controller system

The engine controller provides control over all print engine activities. It drives laser depending on the video
data transmitted from the main controller, provides control over the devices for paper transportation, such
as motors, clutches, solenoids, the heater lamp, the eraser, etc., and collects information given by the sen­sors.

The engine controller is also responsible for the following systems, explained step by step through the fol­lowing pages:

6.4.1 Configuration memory

The engine controller us es a fl ash me mory to st ore the user-selected parame te rs f or confi gurin g th e pri nt er.
The flash memory is driven by +5 V power and designed to stand rewriting operations of at least 100,000
times at an identical address.

6.4.2 High-voltage generator

The engine controller produces clocks (HVCLK1 and HVCLK2) and apply programmed divisor to generate
high-voltage outputs for main charging. The clock oscillation can be toggled on and off by the engine control­ler CPU.

The engine controller generates analog outputs that control the high voltage potential generated by the
high voltage unit. The high voltages unit uses the combination of this analog output and an on/off control
signal to control its generation of the high voltage o utput.

6.4.3 Laser scanner control

In order to activate the laser scanner, the engine controller does the following tasks:

• Generation of laser timing

• Polygon motor activation (start-up and stabilized states)

• Monitoring laser beam paths

6.4.4 Polygon motor control

The output frequency signal to the polygon motor is generated by the engine gate array as it divi des the
engine system clock (18.0762 5 MHz).

The revolution of the polygon motor (N) = 10*f, where f is the clock frequency (2519.7 Hz) = 25,197 rpm.
As the laser beam reaches the beam detector sensor, the sensor board generates the horizontal synchro sig-

nal (NBDLD*). This signal makes the engine gate array consequently turn the video output signal (N
VIDEO*) and the APC signal (NADJUST*) low which respectively activate the laser light and the APC con­troller.

The engine CPU attempts to detect the horizontal synchronization signal so that the laser diode is normally
triggered. If the horizontal synchronization output is not found after the laser driving current control (N
ENABLE*) is set low, the engine CPU reco gni zes it as th e fail ure on the laser driver b oar d and gi ves the E 3
error.

6.5 Safety interlock

For safety purpose, and in order for the product to conform to the safety standards required by the U.S.
FDA and several European regulations (IEC 825), the printer is facilitated with safety interlock. Safety

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FS-5900C Service Manual

interlock is provided by microswitches that work in conjunction with the right side cover, left side cover, and
front covers.

If either of these covers is open, the 24V DC input is cut off except at the following areas, ceasing the laser
emission in LSU:

•PSU fan

• Fuser/toner developers fan

• IC29 (Vcc), IC30 reference voltage controller
Those circuits including the fan motor drivers, high voltage controller, and the fuser controller are deacti-

vated.
The laser emission is also deactivated while the imaging unit is removed from the printer for maintenance,

etc., because the 5V DC input for the la ser driver board i s cut off. If the either of the covers mentioned above
is opened during the imaging unit is remov ed from the printe r, the enable signal from the laser diode driver
is automatically disabled by means of software.

6.5.1 The engine gate array

The engine gate array is a supplementary device to the engine CPU. It is a 208-pin CMOS-type QFP type
that has the internal blocks of function ality as shown below.

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6. Electrical Circuit Description

Gate Array (IC3 )

IC3 serves in the major functions of the printer engine. Pins and their definitions for this gate array is dia­grammed as follows.

Gate Arra

(IC3)

Address (Low) A7-0 VCLK16 Video Clock

CPU Interface

Toner Empty Sensor

Power Supply Unit

Toner Developer Drive

Motor (Sleeve Motor)

Toner Developer

Toner Developer Selector/

Paper Eject Unit

Paper

Feed Unit

Duplex

Dta/Address (Low) D7-0 VD3-0 Video Data

Address (High) A16-8 HSZ

Read RD VSZ

Write WR

Address Strobe ASTB UPSZ2-0 Cassette Detection Sensor

Vertical Interrupt INTVS UPEMP Cassette Empty

Horizontal Interrupt INTHS

SRAM Chip Selec t CSWSRAM CLBPS Cleaning Blade Posittion

Program ROM Chip Select CSPROM

Left Side Door Open DOPNPF MMCLK Extemal Clock

Front Cover Open DOPNFR MMP/S Motor Start/Stop

Toner Empty Detection Signal B(C,M,Y)TECLK

Toner Empty Sensor Control B(C,M,Y)TECTL CHGNOT No Charger

System Clock VCLK64

Reset RS T HVLD Data Load

Fuser Lamp Control FSRCTL HVDATA Data

Motor Start/Stop SLMP/S STRCTL Second Transfer Voltafe Control

Extemal Clock SLMCLK FTRCTL First Transfer Control

Main Motor Speed

Detection Signal

Drive Unit

Fuser Fan

Fuser Unit

Paper Feed Motor

M.P.T Pickup Roller Movement Sensor MPPKUP

Sleeve Clutch Control B(C,M,Y)SLVCTL HPS Transfer Roll Postition

Fuser Fan Error CFMDERR

Fuser fan Control CFMDCTL OPS OPC Postion

Thermistor Open THOPNCK ERSCTL Eraser LED Control

Temperature High THHIGHCK

No Fuser FSRNOT OZMCTL Ozon Fan Control

Motor Start/Stop FMP/S

Extemal Clock FMCLK VIDEO Video Data

Main Motor Speed

Detection Signal

Toner Developer Sensor Signal B(C,M,Y)CMPS PSEL Laser Power Select

Cam Motor Drive Signal B(C,M, Y)CMCTL BDLD B ea m Detect

Paper Ejection/Exit Sensor EXITSEN 1, 2

Output Paper Tray Sensor EXITFULL SCNCTL Control Signa l

Switchback Solenoid Drive Signal FUDCTL SCNCLK Extemal Clock Signal

Duplex Solenoid Power Coltrol DPXSOL 1

Solenoid Power SOLPWR SCNLK Lock Detection Signal

Paper Detection Signal MPPSEN CFMPERR PSU Fan Error

M.P.T Paper Feed Motor MPNA PTLCTL Pre-transfer LED Control

Drive Signals MPB

Transfer Roller Control TRUDCTL OPSCLK Serial Clock Signal

Registration Roller Control RE GCTL OPSLD Data Load Signal

Pickup Control UPUCTL OPMCTL Option Paper Feeder Motor Control

No Paper Feeder Unit PFUNOT PFMSET 1 Option Feeder Motor Speed Control

Transfer Roller Cam Sensor TRRPS 01PCTL Upper Option Cassette Pick Up Con-

Paper Empty Sensor UPNOT 02PCTL Lower Option Cassette Pick Up Con-

Registration Sensor REGSEN

Duplex Top Sensor TOPSEN
Duplex JAM Sensor DJAMSEN
Duplex Fan Control DPXFAN

Duplex On Control DPXUON
Duplex Off Control DPXUOFF

Duplex Fan Error DPXFNS

SLMLD STRSEL Second Transfer Contro l Select

FMLD ENABLE Laser Enable

MPA

MPNB OPSRDD 0, 1 Serial Data Signal

CLBCTL Cleaning Blade Control

MMLD Main Motor Speed Detection Signal

HVERR High Voltage Error

HVCLK Cl ock

DEVCTL Development Bias Control

CHGCTL Scorotron Charger Control

CIKNOT Color Imaging Uni t Detection Signal

OZMERR Ozon Fan Error

ADJUST Laser Power Adjust

Print Control

trol

trol

Video Interface

Voltage Control

Ozon Fan

Cassette

Cleaning Blade

Erraser

Laser Scanning
Unit

Polygon Motor

PTL

Main Motor

High Voltage
Unit

Accumulator B el t home
Detecting Signal

Option Paper
Feeder

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FS-5900C Service Manual

Pin assignment

Pin assignment for the engine gate array is table on the followi ng pages. The device in Remarks column
means those which the signal is forwarded to.

Note that only the pins with meaningful assignment ar e shown below and those for the power line and
ground are excluded.

Engin Gate Array Pin Asignment

Pin No Name I/O Description Termination

1GND
2GND
3 NVCLK16 O Video Clock
4 OPIN0 I GND
5OPOUT16 O Open
6 OPIN1 I GND
7NVD0 I Video Data 0
8 OPIN2 I GND

9NVD1 I Video Data 1
10 OPIN3 I GND
11 NVD2 I Video Data 2
12 OPIN4 I GND
13 NVD3 I Video Data 3
14 UPSZ0 I Default Cassette Size Detection
15 UPSZ1 I Default Cassette Size Detection
16 UPSZ2 I Default Cassette Size Detection
17 UPEMP I GND
18 ITCM O Open
19 CLBPS I Int. Transfer Cleaning
20 NMMLD I Main Motor Lock Detection
21 MMPS O Main Motor Start Pulse
22 MMCLK O Main Motor Clock Output
23 CHGNOT I Charger Installation Detection
24 HVERR I HV error status
25 NHPS I Int. Transfer Home Position Detection
26 GND
27 Vdd
28 OPS I OPC Home Position Detect
29 SLSTPB I Pull-up
30 ERSCTL O Discharger Control
31 HVLD O D/A Data Load (High Voltage Unit)
32 NHVCLK O D/A Shift Clock (High Volta ge Unit)
33 HVDATA O D/A Serial Data Output (High Voltage Unit)

Continued on next page

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6. Electrical Circuit Description

Pin No Name I/O Description Termination

34 PSPSEL O Open
35 FTRSEL O Open
36 DEVCTL O Dev. Bias Control
37 STRCTL O Second Transfer Bias
38 FTRCTL O First Transfer Bias
39 STRSEL O Second Transfer Bias Select
40 CHGCTL O Charger Output Control
41 OPOUT1 O Open
42 NCIKNOT I CIK Installation Detect
43 OZMERR I Ozone Fan Error
44 OZMCTL O Ozone Fan Control
45 OPOUT2 O Open
46 OPOUT3 O Open
47 OPOUT0 O Open
48 OPIN5 I Duplex Top Sensor
49 OPIN6 I Duplex Jam Detect
50 NVIDEO O NVIDEO
51 GND
52 GND
53 Vdd
54 NC
55 ENABLE O Laser-on Enable
56 ADJUST O Laser APC
57 NPSEL O Laser Output Select
58 OPOUT4 O Sensor Power Control
59 OPOUT5 O PSU Fan Control
60 OPOUT6 O Not Used
61 OPOUT7 O Duplex Fan Control
62 OPOUT8 O Duplex ON Control
63 OPOUT9 O Duplex OFF Control
64 OPOUT10 O Open
65 OPOUT11 O Duplex Solenoid Contr ol
66 DIPSE0 I GND
67 DIPSE1 I GND
68 OPPUT12 O Open
69 OPOUT13 O Open
70 OPOUT14 O Open
71 CFMPERR I PSU Fan Error
72 NMANUSEN I GND
73 CTECLK I Cyan Toner Gauge (Reception)

Continued on next page

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FS-5900C Service Manual

Pin No Name I/O Description Termination

74 BTECLK I Black Toner Gauge (Reception)
75 YTECLK I Yellow Toner Gauge (Reception)
76 MTECLK I Magenta Toner Gauge (Reception)
77 OPOUT15 O Not Used
78 Vdd
79 GND
80 VCLK64 I Base Oscillation Clock Input
81 OPIN7 I Duplex Fan Error
82 NCTECTL O Cyan Toner Gauge (Emitter)
83 NMTECTL O Magenta Toner Gauge (Emitter)
84 NYTECTL O Yellow Toner Gauge (Emitter)
85 NBTECTL O Black Toner Gauge (Emitter)
86 LCDE O Not Used
87 NLEDSET O Not Used
88 LCDRS O Not Used
89 NKEYRD Not Used
90 24VCTL O Not Used
91 DOPNFR I Front Door Status Detection
92 DOPNPF I Left Door Status Detection
93 NCSPROM O Program ROM Chip Select
94 OPIN8 I CIK Charger Detection
95 NFSRCTL O Fuser Control
96 OPIN9 I GND
97 NBOLD I HSYNC Detection
98 OPIN10 I GND
99 NSCNLK I Scanner Motor Lock Detection

100 SCNCTL O Scanner Motor Control
101 OPIN11 I GND
102 SCNCLK O Sca nner Motor Clock Output
103 NC
104 Vdd
105 GND
106 GND
107 A0 O Address 0
108 D0 1 O Data 0
109 SLMP/S O Sleeve Motor Control
110 NSLMLD I O Sleeve Motor Lock Detection
111 SLMCLK I O Sleeve Motor Clock Output
112 CSLVCTL I O Cyan Clutch Control
113 YSLVCTL I O Y ellow Clutch Control

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6. Electrical Circuit Description

Pin No Name I/O Description Termination

114 BSLVCTL I O Black Clutch Control
115 MSLVCTL O Magenta Clutch Control
116 NSLV2B O Open
117 A16 I Address 16
118 A15 I Address 15
119 A14 I Address 14
120 A13 I Address 13
121 A12 I Address 12
122 A11 I Address 11
123 A10 I Address 10
124 A9 I Address 9
125 A8 I Address 8
126 NCSWSRAM O SRAM Chip Select
127 CFMDERR I Fixing Fan Error
128 D1 I O Data 1
129 A1 O Address 1
130 Vdd
131 GND
132 A2 O Address 2
133 D2 I O Data 2
134 NPTLCTL O Pre-transfer Static Elimination Control
135 CFMDCTL O Fixing Fan Control
136 THOPNCK I Thermistor Open Detection
137 THHIGHCK I Fixing Overheat Detection
138 NFSRNOT I Fixing Unit Installation Detection H = Not

Detected
139 NOSRNOT I GND
140 NRD I Read
141 NWR I Write
142 ASTB I Address Strobe
143 INTVS O Int. Transfer Home Clutch Clear
144 NINTHS O BD Clutch Clear
145 NFMLD I Feed Motor Lock Detect
146 FMP/S O Feed Motor Control
147 FMCLK O Feed Motor Clock Output
148 MPPSEN I Multi-purpose Paper Detection
149 BCMPS I Developer Position Detection (Black)
150 YCMPS I Developer Position Detection (Yellow)
151 MCMPS I Developer Position Detection (Magenta)
152 CCMPS I Developer Position Detection (Cyan)
153 D3 I Data 3

Continued on next page

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FS-5900C Service Manual

Pin No Name I/O Description Termination

154 A3 I Address 3
155 GND
156 GND
157 Vdd
158 NC
159 A4 O Address 4
160 D4 I O Data 4
161 EXITSEN1 I Fixer Outlet Paper Detection
162 EXITSEN2 I Outlet Paper Detection
163 EXITFULL I Outlet Overstack Detection
164 NYCMCTL O Cam Motor Control (Yellow)
165 NMCMCTL O Cam Motor Control (Magenta)
166 NCCMCTL O Cam Motor Control (Cyan)
167 NBCMCTL O Cam Motor Control (Black)
168 NFUDCTL O Face Up/Down Control
169 NSOLPWR O FD Solenoid Power Control
170 TRUDCTL O No. 2 Transfer Roller Up/Down Control
171 REGCTL O Registration Roller Control
172 UPUCTL O Default Cassette Pickup Control
173 MPA I O Multi-purpose Motor Control (A)
174 MPNA I O Multi-purpose Motor Control (NA)
175 MPB I O Multi-purpose Motor Control (B)
176 MPNB I O Multi-purpose Motor Control (NB)
177 PFUNOT I Paper Feed Unit Installation Detect
178 D5 I O Data 5
179 A5 O Address 5
180 OPIN12 I GND
181 NRST I System Reset
182 GND
183 Vdd
184 A6 O Address 6
185 D6 I O Data 6
186 NTRRPS I Transfer Roller Po sition Detect
187 NUPNOT I Default Cassette Paper Detect
188 NMPPKUP I Multi-purpose Pickup Roller Position Detect
189 NREGSEN I Registration Position Paper Detect
190 OPSRDD1 I Option Feeder Data
191 OPSRDD0 I Option Feeder Data
192 OPMCTL O Option Feeder Motor Control
193 NO1PCTL O Option Feeder Pickup 1

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6. Electrical Circuit Description

Pin No Name I/O Description Termination

194 NO2PCTL O Option Feeder Pickup 2
195 NOPSCLK O Option Feeder Data Clock
196 NOPSLD O Option Feeder Data Load Pulse
197 PFMSET1 O Option Feeder Motor Speed Control
198 CLBCTL O Cleaning Blade Control
199 NVSZ O Vertical Size
200 OPIN13 I GND
201 NHSZ2 O Not Used
202 OPIN14 I GND
203 NHSZ O Horizontal Size
204 OPIN15 I GND
205 D7 I O Data 7
206 A7 O Address 7
207 NC
208 Vdd

6.5.2 Power supply

The power supply contains the AC and DC power inputs and outputs. The high voltage bias generator cir­cuit is mounted on a separate board. A simplified power distribution diagram is shown on page 86.

AC INPUT AND RECTIFIER

The primary AC input power arrives at CN201 following the power switch and fuse F201, and enters AC
line filter circuit (L222, L201, C201, etc.). D203 rectifies it to DC; Q201 and Q202 provide switching on it for
downverting by T201 to develop +24V and +5V DC.

24V DC POWER LINE

The 24V DC appearing at the secondary side of T201 is rectified by D302 and smoothed by C305, C306, etc.,
and distributed through CN301. The +24V power is regulated by means of the feedback loop using IC301
and PC202. The 24V DC line is represe nted as VDD or VDDCOM and used to fee d the foll owing engine com­ponent:

• Face-up/down stack solenoids, MP tray paper feed solenoid

• Clutches (registration, intermediate)

•Fans

• High-voltage generator (board)

• Main motor, laser polygon motor, toner motor

• Clutches, motors, solenoids within the option units

• Laser APC, fuser heater control, eraser LED
The 24V DC power is forcibly interrupted for safety whenever the front cover, right side cover, or left side

cover is open. For details, see the

Safety interlock

section, page 77.

5V DC POWER LINE

The +5V DC line is generated by switching (IC302 and D301) the +24V DC to develop the 5V DC which is
subsequently rectified and smoothed by D40, C40, etc. It is also distributed through CN301. The main con­troller circuits, sensors, engine controller circuits, etc., are fed by the +5V DC line (also referred to as VCC).

The +5VDC power is downverted from the +24V power and regulat ed by IC302, Q301, et c.

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FS-5900C Service Manual

POWER PROTECTION CIRCUIT

A fraction of the +24V DC power is connected to the protection diode PC1 for provides protection action for
the power supply. The output of +24V is protected from short-circuiting by F303 as well as detection in the
primary circuit.

FUSER HEATER POWER CONTROL

In the primary circuit, the fuser heater lamp and the thermostat are connected parallel across CN204. The
heater lamp is controlled by D205. Each is turned on when the gate are triggered, respectively energizing
the appropriate heater lamp.

For details on the fuser function, refer to on page .

Power Circuit Distribution

86

6. Electrical Circuit Description

6.6 Logic controller system

The main logic controller has the overall specifications as tabled on next page. A simplified block diagram is
shown on page 88. The logic controller system does the following:

• Communicates with the host computer to receive data at one of the printer’s interface

• Analyzes and translates the print data to be the dot data in the raster memory

• Communicates with the engine system t o discern readiness for printing

• Stores fonts and macro information
The main logic controller has specifications as shown in the following section. A simplified diagram is illus-

trated on page 88.

Main Logic Controller Specifications

Item Specification

CPU PowerPC740/200 MHz
Co-processor Peerless QP-1800
Gate array Fujitsu MB87D129
System ROM size 8 MB (4 MB × 2 slots); flash DIMM
RAM size Standard 48 MB (onboard 16 MB (2 MB × 8) + SIMM slot 32 MB)

Option 4, 8, 16, or 32 MB × 2
Status ROM 128 kB flash ROM
Fonts Resident 4 MB (2 M × 16 bits)

Custom 45 Type 1, 80 PCL bitmap, TrueType rasterizer
Application program interface 512 kB (256 k × 16 bits) × 1
PC card 1 slot, JEIDA4.2/PCMCIA2.1, max. 32 MB
Interface Parallel High-speed bi-directional [IEEE 1284]

Serial RS-232C (8-pin DIN); barcode reader support

Option Network interface [Kuio]
Harddisk (option) Onboard, 2GB [HD-2C]
Engine comm u nication Se ri al int e rface
Front panel communication Serial interface
Other features Smoothing None

Toner saver EcoPrint [On/Off]

Enlarge/reduc-

tion

None

Compatibility KPDLII (PostScript compatible), PCL5C, Prescribe IIC
Colour correction KC Colour Correction

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FS-5900C Service Manual

Controller block diagram

YC1

HDD

Data Bus(16D 16bit)

U8

U11

API

FONT ROM

YC5

IC Card

DIMM 4MBx2Slot

YS1,YS2 System ROM

Address Bus(BA 32bit)

U9,U10,U12,U13

Buffer 74x244

Address Bus(MPCA 32bit)

U5,U7

Data Bus(DH32bit)

33MCLKO

Buffer 74x245

U4,U6

Buffer 74x244

U3

G/A

MB87D129

U27

Status ROM

Video Data(Serial)

AD Bus (BAD 32bit)

U2

Divider

YC2

KUIO

Front Panel I/F

Video Data (4bit)

Divider

Vclk16

QVCLK

Engine Command/Status

QP1800

X3

DRAM Address Bus(DA 11bit)

YC7

32MH

DRAM Data Bus(DD32bit)

KME Printer

YS3,YS4

Option RAM SIMM 2

Standard RAM

U14,U15,U16,U17

88

U1

MPU

MPC603e

(Int 100Mhz)

X1

66MH

Y1 14.7456MHz

YC3 Serial I/F

YC6 Parallel I/F

6. Electrical Circuit Description

6.6.1 Printing data processing

The printer communicates with the host computer for receiving the print data at one of the printer’s inter­faces and temporarily store them in the interface buffer. The main logic controller analyzes the data for
translating them into the dot data according to the original print image. The resultant dot data are depicted
in the raster memory (DRAM’s).

While data processing is in course, on the other hand, the main logic controller CPU talks to the engine
CPU via the engine interface, to discern the readiness of the printer’s engine for printing.

If the engine is ready to start printing, the main controlle r issues print signal towards the engin e controller
which request the paper feed. In synchronization with the procession of the paper within the printer, U2
releases video data in the raster memory. Thus the video data are transferred to the laser scanner together
with the horizontal synchronization signal a n d the video clock.

On reception of the video data, the laser diode turns on and off to constitutes the print image over the drum.
The image on the drum, referred to as the static latent image, is applied with toner, transferred onto the
paper, and finally fused permanently on the paper by means of heat and pressure.

6.7 Main logic component

CPU (U1)

A PowerPC740/200 MHz is used. This 64-bit processor is operated at 32-bit width. The external clock of 33
MHz is sextupled to 200 MHz by the internal PLL circuitry.

Co-processor (U3)

The Peerless QP01800 is used. This ASIC includes the following circuitries:

• Processor interface

• Interrupt controller

•ROM interface

• I/O interface

• Engine interface controller

• DRAM controller

• P1284 controller

• Serial communication controller

• Graphics execution unit

• Print engine video controller

ASIC (U4)

This ASIC implements the following functionalities by use of signals provided QP-1800:

• System DIMM control

• Memory card control

• Font ROM control

• Front panel interface control

• Harddisk interface control

• Simulated DMA access for KUIO

• Character check for parallel interface

• Vide o data triggering
For data buses of 16 bit wide for such as memory card and fonts, 32-bit conversion for CPU is implemented

within this ASIC.

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FS-5900C Service Manual

System DIMM (YS1/YS2)

Two 72-pin DIMM with 4MB capacity are used for the system. The firmware can be up-versioned by down­loading a new firmware data.

Main RAM (U14 through U24)

Eight 16Mbit DRAM’s are used in EDO mode, constituting 16 MB of base memory and a 32 MB SIMM in
YS3 as the default (48 MB in total). The main RAM is expandable up to 112 MB using two open sockets on
the main logic board. SIMM to be used should comply with the following specifications:

No. of SIMM sockets 2
Socket code YS4 , YS5
No. of pins 72
Size 8, 16, or 32 MB
Access speed <70ns

Memory card interface (YC5)

The printer supports PCM CI A 2.1- or JEI DA4.2 -comp ati ble, Type I SRAM or flash type memory cards. The
maximum size is 32 MB. For SRAM cards, the printer recognizes the battery voltage and write-protection
switch.

KUIO interface (YC1)

This is the interface for a slot-in option device conforming to the KUIO interface specifications. For model
FS-5900C, this accepts a network interface card.

The pin assignment for the connector is given below.

Pin No. Termina l Signal Pin No. Terminal Signal

A1 VCC (+5V) VCC A16 CTLRDY CTLRDY
B1 VCC (+5V) VCC B16 OP2DREQ OP2DREQ
A2 VCC (+5V) VCC A17 GND GND
B2 NC NC B17 OP2DACKN OP2DACKN
A3 GND GND A18 IOR* LIORN
B3 NC NC B18 IOW* LIOWN
A4 NC NC A19 RESET* RESETN3
B4 A16 IOA16 B19 NC NC
A5 GND GND A20 D15 LD15
B5 A15 IOA15 B20 D14 LD14
A6 A14 IOA14 A21 GND GND
B6 A13 IOA13 B21 D13 LD13
A7 A12 IOA12 A22 D12 LD12
B7 A11 IOA11 B22 D11 LD11
A8 A10 IOA10 A23 D10 LD10
B8 A9 IOA9 B23 D9 LD9
A9 GND GND A24 D8 LD8

B9 A8 IOA8 B24 D7 LD7
A10 A7 IOA7 A25 GND GND
B19 A6 IOA6 B25 D6 LD6
A11 A5 IOA5 A26 D5 LD5
B11 A4 IOA4 B26 D4 LD4

90

6. Electrical Circuit Description

Pin No. Terminal Signal Pin No. Terminal Signal

A12 A3 IOA3 A27 D3 LD3
B12 A2 IOA2 B27 D2 LD2
A13 GND GND A28 D1 LD1
B13 NC NC B28 D0 LD0
A14 OP2CS OP2CSN A29 GND GND
B14 OP2ACK OP2ACKN B29 VCC (+5V) VCC
A15 OP2IRN OP2IRN A30 VCC (+5V) VCC
B15 NC NC B30 VCC (+5V) VCC

Parallel interface

The printer has a port for the parallel interface that is compatible with the current line-up of the Ecosys
series printers. The parallel interface supports the protocols defined by the IEEE 1284 standards. To gain
conformity to these standards, the prin ter supports the ECP and nibble modes.

Details on the signals on the parallel interface are described in the appropriate appendix in this manual.

Serial interface

The printer incorporates a port for the serial interface. The serial interface controller is included within the
gate array and supports RS-232C protocol. Since the RS-232C support is designed to be compatible with
SNMP (Simple Network Management Protocol ), CTS and DSR signals are included.

A 8-pin mini DIN connector is used for the serial port. (See Appendix A for the interface later in this manual
for details.) A conversion cable kit is available for connecting the printer’s serial interface to a D-SUB con­nector of the serial interface of the computer.

The serial interface has the following features:

Connector type 8-pin mini DIN
Baud rates/sec. 300/600/1200/2400/4800/9600/19200/38400/57600/115200
Protocol RS-232C

Engine interface

The interface to the engine system is b ased on the serial interface, not the parallel interface that was used
with the previous line-up of the Ecosys printers. For communication interface, the QP-1800’s interface is
used.

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FS-5900C Service Manual

Engine interface connector assignment

Pin No. Signal Pin No. Signal Pin No. Signal

A1 GND A11 GND A21 GND

B1 VCC B11 NCCLK B21 VDAT2

A2 GND A12 GND A22 GND

B2 VCC B12 STSC B22 VDAT3

A3 GND A13 SBSY A23 FPGND

B3 VCC B13 CMDC B23 FPGND

A4 GND A14 MCPRDY A24 No connection

B4 VCC B14 CBSY B24 No connection

A5 GND A15 PURG E A25 No connection

B5 VCC B15 NPPRDY B25 FPDATC

A6 GND A16 GND A26 No connection

B6 VCC B16 NVSZC B26 No connection

A7 GND A17 GND A27 No connection

B7 VCC B17 NHSZC B27 FPDIRC

A8 GND A18 GND A28 No connection

B8 VCC B18 VCLK16C B28 VCC

A9 VCC A19 GND A29 FPGND

B9 VCC B19 VDAT0 B29 VCC
A10 GND A20 GND A30 FPGND
B10 No connection B20 VDAT1 B30 FPCLKC

6.8 Print engine (video) interface

This section defines the interface between the printer engine and the raster image processor (RIP). The
terms video and raster refer to the method of image data transfer. The data is synchronized to the vertical
and horizontal beam scanning while printing.

The engine modulates the laser beam to print an image. The image data and printing control is through the
video interference connection. General control and status information is communicated through a serial
interface in the same connector.

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6. Electrical Circuit Description

6.8.1 Physical Characteristics

The printer/image processor interface consists of image data and control data signal lines. Signal names
with N as the first character are asserted (true) with low levels. The diagram below is a simplified block dia­gram for the RIP and the engine portions of the printer.

1. Printing video interface lines

VD0 through VD3 image data
VCLK: video clock
NVSZ: Vertical size
NHSZ: horizontal size

2. Printing control lines

NCPRDY: Controller power ready

RASTER IMAGE
PROCESSOR
(RIP)

Front panel
Interfaces

[Centronics,
RS-232C]

Explanation to the above diagram

1. Printing video interference
signal lin es

These lines are for image data transfer in bit-parallel fashion.

PURGE: Purge media
NPRDY: Print engine power ready

3. Serial control lines

CMD: Command serial data
CBSY: Command busy
NCCLK: Communication clock

STS: Status serial data
SBSY: Status busy

4. Power lines

+5V and ground

ENGINE
CONTROL CPU

LASER
SCANNER
UNIT

2. Printing control lines Printing enable lines and control options. These lines exchange status and control
information.

3. Serial control lines These lines consist of command signals employed to control the printer by the
image processor. Status signals return information about the printer status. Com­mands and status responses are transmitted and received as clocked serial signals.

4. Power lin es

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FS-5900C Service Manual

6.9 Interface Signals

6.9.1 Signal functions

Throughout the following table, the signal names that begin with N mean that the signal is asserted (true)
with low level, and not asserted (false) with high level.

Signal name Function Source

NPRDY Printer power ready. Valid and asserted true with 1.8 sec. after power on. Engine
NCPRDY Controller power ready RIP
NVSZ Vertical size signal (vertical sync or enable). When asserted, data transfer on lines

VD0-3 is in the vertical printable area.

NHSZ Horizontal size signal (horizontal sync or enable). When asserted, data transfer on

lines VD0-3 is in the horizontal printable area.
Runs anytime LSU spinning, including: Before NVSZ true, After NVSZ false,
Between color planes.

Engine

Engine

VCLK Video data clock signal. Image data transfer on lines VD0-4 is synchronized to this

clock signal. Frequency is 18.07625 MHz. Runs all the time (even when not print­ing), IP must gate with NHSZ and NVSZ.

VD0-3 Video data lines (4-bit parallel). Each byte transfer represents one of 2 possible lev-

els for each color pixel.
If VD0-3=0 (all lines low), no dot is printed. Where VDn=1, a pixel dot is printed in
each of the positions.
VD must be transmitted from the image processor with each nibble transfer syn­chronized with the VCLK signal. VD is transmitted only while the NHSZ and NVSZ
lines asserted.
NHSZ and NVSZ signals identify the print scan timing and are adjusted with the
top and left calibration serial port commands.

PURGE Purge signal. Asserted while paper or transparency is b eing ejected out of the

printer into the output tray. PURGE is asserted for 500 msec., beginning when the
leading edge of the media is detected b y the fuser exit sensor.

Engine

Engine

Engine

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6. Electrical Circuit Description

6.9.2 Serial control lines

Signal Function Source

STS Status and data serial line. Synchronous serial line used to transmit print engine

status information to the im ag e pr ocessor. Status bytes are return ed in r espo ns e to
command and status requests from the CMD se rial line. If a command is received
by the engine that requires numeric information, the digital data is returned on the
STS line. The numeric information is returned as a sequence of ASCII digits (0-9).
For a 5 digit status the first digit is ten-thousands, digit 3 is hundreds, digit 4 is
tens, and digit 5 is ones.

Protocol Half duplex, synchronous signal.
Baud rate 500 kHz
Data length 7 bits
Parity bit Odd (bit 0 or LSB)
DTR None

Transmission sequence is MSB first to LSB last (bits 7, 6, 5, 4, 3, 2, 1, 0).
SBSY line is asserted during the transmission of data over the STS line.
Engine does not respond with STS and SBSY asserted if CBSY from RIP is
asserted.

SBSY Status busy signal. Asserted whe n status or numeric infor m at io n is be ing tr ans mi t -

ted from the engine to the RIP over the STS line.
Following the reception of a command byte from the CMD line, the CBSY line deas­sreted (low). The engine then assert s the SBSY within 5 msec. (50 msec. for diag­nostic mode) and returns serial information over the STS line. After the STS serial
transfer finishes, SBSY deasserts.
When CBSY is asserted, the engi ne cannot activates SBSY, nor return information
over STS.

CMD Synchronous serial line used to transmi t c om mand a nd n ume ri c ar gum ent info rma -

tion to the print engine. The numeric information is transmitted as a sequence of
ASCII digits (0-9). For a 5-digit command the first digit is ten-thousands, digit 2 is
thousands, digit 3 is hundreds, digit 4 is tens, and digit 5 is ones.
The protocol and bit sequence is the same as for the STS line.
CBSY line is asserted during the transmission of data over the CMD line.
RIP must not transmit on the CM D line, nor assert CBSY when the eng in e asse r t s
the SBSY line.

Engine

Engine

RIP

CBSY Command busy signal. Asserted when command or numeric information is being

transmitted from the RIP to the engine over the CMD line.
Following the transmission of a comman d byte from the CMD line, the CBSY line
deasserts (low).
Following command trans missio ns, th e engi ne respo nds with a stat us by te over th e
STS line.
When SBSY is asserted, RIP cannot activate CBSY, not transmit command infor­mation over the CMD line.
There is no constraint on how long RIP may keep CBSY asserted.

NCCLK Communication clock signal. This clock provides a synchronous pulse while com-

mand or status bytes are being transferred between the engine and RIP.
Both the STS and CMD serial lines are synchronized with this clock signal.
Each CMD bi t i s s en t to en gine on th e f allin g edge of NCC LK and ea ch S TS d at a b it
is received from en gine on the rising edge of NCCLK.

RIP

RIP

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