Mitac 8965 Service Manual

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SERVICE MANUAL FOR

8965

89658965

8965

89658965

8965

89658965

BY: Sinty Zhang

Repair Technology Research Department /EDVD

Apr.2005 / R01

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Contents

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1. Hardware Engineering Specification ……………………………………………………………… ………

1.1 Introduction ………………………………………………………………………………………………………………..

1.2 System Hardware Parts …………………………………………………………………………………………………...

1.3 Other Functions ……………………………………………………………………………………………………………

1.4 Power Management ……………………………………………………………………………………………………….

1.5 Appendix 1 : VIA VT8235CE GPI/O Pins Definitions ……………………………………………………………….....

1.6 Appendix 2 : W83L950D KBC Pins Definitions ………………………………………………………………………...

2. System View and Disassembly ……… ……………………………………………………………………..

2.1 System View ……………………………………………………………………………………………………………….

2.2 Tools Introduction …………………………………………………………………………………………………………

2.3 System Disassembly ……………………………………………………………………………………………………….

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3. Definition & Location of Connectors / Switches …………………………………………………………..

3.1 Mother Board ……………………………………………………………………………………………………………...

3.2 Modem Board ……………………………………………………………………………………………………………...

4. Definition & Location of Major Comp onents ……………………………………………………………..

4.1 Mother Board ……………………………………………………………………………………………………………...

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5. Pin Description of Major Componen ts ….…………………………………………………………………

5.1 Intel Pentium M Processor CPU …………………………………………………………………………………………

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5.2 PN800 North Bridge ………………………………………………………………………………………………………

5.3 VT8235CE South Bridge ….……………………………………………………………………………………………...

6. System Block Diagram ……………………………………………………………………………………..

7. Maintenance Diagnostics …………… ……………………………………………………………………..

7.1 Introduction ……………………………………………………………………………………………………………….

7.2 Error Codes ……………………………………………………………………………………………………………….

7.3 Debug Tool …………………………………………………………………………………………………………………

8. Trouble Shooting ……………………………………………………………………………………………

8.1 No Power …………………………………………………………………………………………………………………..

8.2 Battery Can not Be Charged …………………………………………………………………………………..…………

8.3 No Display …………………………………………………………………………………………………………………

8.4 LCD No Display or Picture Abnormal …………………………………………………………………………………..

8.5 External Monitor No Display or Color Abnormal ………………………………………………………………………

8.6 Memory Test Error ……………………………………………………………………………………………………….

8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………………..

8.8 Hard Disk Drive Test Error ………………………………………………………………………………………………

8.9 USB Port Test Error ……………………………………………………………………………………………………...

8.10 Mini-PCI Socket Test Error …………………………………………………………………………………………...

8.11 Audio Test Error …………………………………………………………………………………………………………

8.12 LAN Test Error ………….……………………………………………………………………………………………….

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9. Spare Parts List ……………………………………………………………………………………………..

10. System Exploded Views …………… ………………………………………………………………………

11. Circuit Diagram ……………………………………………………………………………………………

12. Reference Material ……………………………………… ………………………………………………..

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1. Hardware Engineering Specification

1.1 Introduction

1.1.1 General Description

This document describes the brief introduction for MITAC 8965 portable notebook computer system.

1.1.2 System Overview

The MITAC 8965 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It can support Banias 1.5G ~ 1.9GHz.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such as Wireless Lan indicator, Power indicator, Battery status indicator, HDD, Num Lock, Caps Lock, Scroll Lock. It also equipped with LAN, 4 USB ports, and audio line out, external microphone function.

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The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC3200 DDR400 SDRAM.

The VIA PN800 Mobile North Bridge integrates a high performance CPU interface for Intel Pentium 4 / Pentium-M processor, a full featured AGP port controller, integrated Graphics with 2D/ 3D/ Video Controllers, a advanced high- performance DDR400 SDRAM controller, and high bandwidth Ultra V-Link host controller connecting with VIA

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VT8235CE South Bridge.

The VIA VT8235CE integrates Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Inter- operable with VIA Host-to-V-Link Host Controller.

The VIA VT6103L is a Fast Ethernet 10 / 100 1-port PHY / Transceiver with MII interface, and meet all applicable IEEE 802.3, 10Base-T and 100Base-Tx standards.

The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high performance systems can be implemented easily.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering

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IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Parts

CPU

Core logic VGA Control

System BIOS Memory

Video Memory Clock Generator

LVDS LAN PHY

Audio System

Mobile Pentium-M Processor 1.3G ~ 1.9GHz Thermal spec 35W TDP

VIA PN800 + VIA VT8235CE chipset

North Bridge Integrated

SST49LF040

DDR RAM : DDR333 Nanya NT512D64S8HBAFM-6K DDR400 Micron, MT8VDDT3264HD

Share memory

ICS 950902

VIA VT1634AL

VIA VT6103L

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AC97 CODEC: Advance Logic, Inc, ALC655 Power Amplifier: TI TPA0212

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1.2.1 Intel Banias Processors in Micro-FCPGA Package

Intel Banias Processors with 593 pins Micro-FCBGA package.

It has the Intel NetBurst micro-architecture which features include hyper-pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock.

Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes.

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1.2.2 Clock Generator

The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory. The ICS950902 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.

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Recommended Application

 VIA P4X/P4M/KT/KN266/333 style chipsets

Output Features

 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ 1 - Pair of differential open drain CPU clocks (K7)

 1 - Pair of differential push pull CPU_CS clocks @ 2.5V

 3 - AGP @ 3.3V

 7 - PCI @ 3.3V (1 - Free running)

 1 - 48MHz @ 3.3V fixed

 1 - 24_48MHz @ 3.3V (Default 48MHz I2C select only)

 2 - REF @ 3.3V, 14.318MHz

 12 - SDRAM (6 pair - DDR) selectable

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Features/Benefits

 Programmable output frequency

 Programmable output divider ratios

 Programmable output rise/fall time

 Programmable output skew

 Programmable spread percentage for EMI control

 DDR output buffer supports up to 200MHz

 Watchdog timer technology to reset system if system malfunctions

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 Programmable watch dog safe frequency

 Support I2C Index read/write and block read/write operations

 Uses external 14.318MHz crystal

1.2.3 PN800 Mobile North Bridge

The PN800 is a high performance, cost-effective and energy efficient UMA North Bridge with integrated UniChrome Pro graphics / video controllers used for the implementation of mobile personal computer systems based on 800 / 533 / 400 MHz FSB Intel Pentium 4 and Pentium M super-scalar processors. The complete mobile chipset consists of the PN800 North Bridge (829 pin HSBGA) and the VT8235-CE V-Link South Bridge (539-pin BGA). The PN800 integrates VIA’s PT800 system controller with high-performance UniChrome Pro 3D/2D graphics accelerator plus flat panel, DVI monitor and TV out interfaces. The PN800 provides superior performance between the CPU, DRAM, V-Link bus and internal AGP 8x graphics controller bus with pipelined, burst, and concurrent operation. The VT8235-CE is a highly integrated peripheral controller which includes V-Link-to-PCI /

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V-Link-to-LPC controllers, Ultra DMA IDE controller,USB2.0 host controller, 10/100Mb networking MAC, AC97, and system power management controllers.

Host CPU Interface

The PN800 supports 800 / 533 / 400 MHz FSB Intel Pentium 4 and Pentium M super-scalar processors. It implements a twelve level In-Order-Queue and supports Intel Hyper-Threading Technology to maximize system performance for multi-threaded software applications. DBI and Pentium M bus protocol, as well as Intel SpeedStep Technology, are supported which effectively reduce overall system power consumption.

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AGP Interface

The PN800 AGP controller is AGP 3.0 compliant with up to 2.1 GB / second data transfer rate capability. It supports asynchronous AGP and CPU interfaces for flexible system configuration. Deep read (1024 byte) and write (512 byte) FIFOs are integrated for optimal bus utilization and minimum data transfer latency.

Memory Controller

The PN800 SDRAM Controller supports two sets of 64-bit memory data, address and control signals to minimize signal loading and up to 4 double-sided DDR400 / 333 / 266 DIMMs for 8 GB maximum physical memory. The DDR DRAM interface allows zero wait-state data transfer bursting between the DRAM and the memory controller’s data buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 / 256 / 512 / 1024Mb DRAMs in x8 and x16 configurations. The DRAM controller can run either synchronous or pseudo- synchronous with the host CPU bus. The PN800 North Bridge is pin compatible with the PN880 North Bridge which connects to the memory modules in exactly the same manner while supporting true 128-bit operation

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(simultaneous memory access on both sets of 64-bit memory data / address / control signals).

Ultra V-Link

The PN800 North Bridge interfaces to the South Bridge through a high speed (up to 1 GB/sec) 8x, 66 MHz Data Transfer interconnect bus called “Ultra V-Link”. Deep pre-fetch and post-write buffers are included to allow for concurrent CPU and Vlink operation. The combined PN800 North Bridge and VT8235-CE South Bridge system supports enhanced PCI bus commands such as “Memory-Read-Line”, “Memory-Read-Multiple” and “Memory- Write-Invalid” commands to minimize snoop overhead. In addition, advanced features are supported such as CPU write-back forward to PCI master, and CPU write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for

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further improvement of overall system performance.

System Power Management

For sophisticated power management, the PN800 supports dynamic CKE control to minimize DDR SDRAM power consumption during normal system state (S0). A separate suspend power plane is implemented for the memory control logic for Suspend-to-DRAM state. Enhanced Intel SpeedStep™ Technology enables minimization of CPU power consumption while sustaining processing power. The PN800 graphics accelerator implements dynamic clock gating for inactive functions to achieve maximum power savings. The system can also be switched to standby or suspend states to further reduce power consumption when idle.Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down are supported.Coupled with the VT8235-CE South Bridge chip, a complete power conscious PC main board can be implemented with no external glue logic.

3D Graphics Engine

Featuring an integrated 128-bit 3D graphics engine, the PN800 North Bridge utilizes a highly pipelined architecture that provides high performance along with superior image quality. Several new features enhance the 3D architecture, including two pixel rendering pipes, single-pass multitexturing, bump and cubic mapping, texture compression, edge anti-aliasing, vertex fog and fog table, hardware back-face culling, specular lighting, anisotropic filtering and an 8-bit stencil buffer. The chip also offers the industry’s only simultaneous usage of single-pass multitexturing and single-cycle trilinear filtering – enabling stunning image quality without performance loss. Image quality is further enhanced with true 32-bit color rendering throughout the 3D pipeline to produce more vivid and realistic images. The advanced triangle setup engine provides industry leading 3D performance for a realistic user experience in games and other interactive 3D applications. The 3D engine is optimized for AGP texturing from system memory.

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128-bit 2D Graphics Engine

The PN800 North Bridge's advanced 128-bit 2D graphics engine delivers high-speed 2D acceleration for productivity applications. The enhanced 2D architecture with direct access frame buffer capability optimizes UMA performance and provides acceleration of all color depths.

MPEG Playback

The PN800 North Bridge provides the ideal architecture for high quality MPEG-2 based video applications. For MPEG video playback, the integrated video engine offloads the CPU by performing planar-to-packed format conversion and motion video compensation tasks, while its enhanced scaling algorithm delivers incredible full-screen video playback.

Video Capture

The PN800 North Bridge implements an optional Video Capture Port which supports various video capture standards, including ITU-R BT656, VIP 1.1 and VIP 2.0 and is compliant with the most common video capture formats: 16 / 32- bit RGB and YUV422. With the integrated video capture feature, the PN800 can provide high performance video effects for video capturing and playback.

LCD, DVI Monitor and TV Output Display Support

The PN800 provides three “Digital Video Port” interfaces: FPDP, GDVP1 and DVP0. The Flat Panel Display Port (FPDP) implements a 24-bit / dual 12-bit interface which is designed to drive a Flat Panel Display via an external LVDS transmitter chip (such as the VIA VT1631, NSC DS90C387R or Chrontel CH7017). The PN800 can be connected to the external LVDS transmitter chip in either 24-bit or dual-12-bit modes. A wide variety of LCD panels are supported including VGA, SVGA, XGA, SXGA+ and up to UXGA-resolution TFT color panels, in either SDR (1

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pixel / clock) or DDR (2 pixels / clock) modes. UXGA and higher resolutions require dual-edge data transfer (DDR) mode which is supported by the VIA VT1631 LVDS transmitter chip Digital Video Port 0 (DVP0) is normally used for interfacing to a TV encoder (such as the VIA VT1622A or VT1622AM using 3.3V signal levels), however if DVP0 is used for video capture, Digital Video Port 1 (GDVP1) may be configured for support of an external TV encoder (VIA VT1623 or VT1623M using low-voltage 1.5V signal levels). If GDVP1 is not being used for TV out, it can optionally be used to drive a DVI monitor via an external TMDS transmitter chip (such as the VIA VT1632) The flexible display configurations of the PN800 allow support of a flat panel (LVDS interface) or flat panel monitor (TMDS / DVI interface), TV display and CRT display at the same time. Internally the PN800 North Bridge provides two separate display engines, so if two display devices are connected, each can display completely different information at different resolutions, pixel depths and refresh rates. If more than two display devices are connected, the additional displays must have the same resolution, pixel depth and refresh rate as one of the first two. The maximum display resolutions supported for one display device are listed in the table below. If more than one display is implemented (i.e., if both display engines are functioning at the same time), then available memory bandwidth may limit the display resolutions supported on one or both displays. This will be dependent on many factors including primarily clock rates and memory speeds (contact VIA for additional information).

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1.2.4 VT8235CE Highly Integrated South Bridge

The VT8235 Version CE South Bridge is a high integration, high performance, power-efficient and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001-compliant PCI/LPC system. The VT8235 Version CE includes standard intelligent peripheral controllers. a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external

PHY ceiver.

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b) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel

commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8235 Version CE also supports the Ultra DMA-133, 100, 66 and 33 standards to allow reliable data transfer at rates up to 133 MB/sec. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

c) Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The VT8235

Version CE includes three root hubs with six function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.

d) Keyboard controller with PS2 mouse support.

e) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the

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integrated RTC also includes the date alarm, century field and other enhancements for compatibility with the ACPI standard.

f) Notebook-class power management functionality compliant with ACPI and legacy APM requirements.

Multiple sleep states (power-on suspend, suspend-to-DRAM and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.

g) Full System Management Bus (SMBus) interface.

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h) Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.

I) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA

channels to any interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of onboard peripherals for Windows family compliance.

The VT8235 Version CE also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8235 Version CE supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (double words) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.

1.2.5 AC’97 Audio System: Advance Logic, Inc, ALC655

The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meetperformance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions toprovide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655 also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk

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devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs can be detected.

 Meets performance requirements for audio on PC99/2001 systems

 Meets Microsoft WHQL/WLP 2.0 audio requirements

 16-bit Stereo full-duplex CODEC with 48KHz sampling rate

 Compliant with AC’97 2.3 specifications

- 14.318MHz- 24.576MHz PLL to save crystal

- 12.288MHz BITCLK input can be consumed

- Integrated PCBEEP generator to save buzzer

- Interrupt capability

 Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX

 High quality differential CD input

 Two analog line-level mono input: PCBEEP, PHONE-IN

 Two software selectable MIC inputs applications (software selectable)

 Boost preamplifier for MIC input

 50mW/20 amplifier

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 External Amplifier Power Down (EAPD) capability

 Power management and enhanced power saving features

 Stereo MIC record for AEC/BF application

 Supports Power Off CD function

 Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback

 Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification

 Power support: Digital: 3.3V; Analog: 3.3V/5V

1.2.6 System Flash Memory (BIOS)

 Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets

 Flexible Erase Capability

- Uniform 4 KByte Sectors

- Uniform 16 KByte overlay blocks for SST49LF002A

- Uniform 64 KByte overlay blocks for SST49LF004A

- Top boot block protection

- 16 KByte for SST49LF002A

- 64 KByte for SST49LF004A

- Chip-Erase for PP Mode

 Single 3.0-3.6V Read and Write Operations

 Superior Reliability

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 Firmware Hub Hardware Interface Mode

- 5-signal communication interface supporting byte Read and Write

- 33 MHz clock frequency operation

- WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

- Block Locking Register for all blocks

- Standard SDP Command Set

- Data# Polling and Toggle Bit for End-of-Write detection

- 5 GPI pins for system design flexibility

- 4 ID pins for multi-chip selection

1.2.7 Memory System

1.2.7.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs

 JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

 Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components

 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg

x 64 [HD])

 VDD= VDDQ= +2.5V ±0.2V

 VDDSPD = +2.2V to +5.5V

 2.5V I/O (SSTL_2 compatible)

 Commands entered on each positive CK edge

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 DQS edge-aligned with data for READs; center-aligned with data for WRITEs

 Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle

 Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture

 Differential clock inputs (CK and CK# can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

 Four internal device banks for concurrent operation

 Selectable burst lengths: 2, 4 or 8

 Auto precharge option

 Auto Refresh and Self Refresh Modes

 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,

MT8VDDT6464HD) maximum average periodic refresh interval

 Serial Presence Detect (SPD) with EEPROM

 Fast data transfer rates PC2100 or PC1600

 Selectable READ CAS latency for maximum compatibility

 Gold-plated edge contacts

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1.2.8 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Receiver is a

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Low-power, Physical-layer Device (PHY)

The VT6103L is a Physical Layer device for Ethernet 10Base-T and 100Base-TX using category 5 Unshielded and Type 1 Shielded cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s Fast Ethernet LANs. It interfaces to a MAC through an MII interface ensuring interoperability between products from different vendors.

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Product Features

 Single Chip 100Base-TX / 10Base-T Physical Layer Solution

 Dual Speed – 100 / 10 Mbps

 Half and Full Duplex

 MII Interface to Ethernet Controller

 MII Interface to Configuration & Status

 Auto Power Saving Mode

 Auto Negotiation: 10 / 100, Full / Half Duplex

 Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards

 On Chip Wave Shaping – No External Filters Required

 Adaptive Equalizer

 Baseline Wander Correction

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 LED Outputs

- Link Status

- Duplex status

- Speed Status

- Collision

 48 Pin LQFP Package

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1.2.9 Keyboard System: Winbond W83L950D

The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP-ROM that is divided into four banks, two SMBus interface for master and slave, support 4 PWM channels, 2 D-A and 8 A-D converters.

 8051 uC based

 Keyboard Controller Embedded Controller

 Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB

 Support 4 Timer (8 bit) signal with 3 prescalers

 Support 2 PWM channels, 2 D-A and 8 A-D converters

 Reduce Firmware burden by Hardware PS/2 decoding

 Support 72 useful GPIOs totally

 Support Flash utility for on board re-flash

 Support ACPI

 Hardware fast Gate A20 with software programmable

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1.3 Other Functi ons

1.3.1 Hot Key Function (TBD)

Keys Combination Meaning

Fn + F3

Fn + F4 Volume Increase

Fn + E5 Toggle Among LCD, External CRT

Fn + F6 LCD Brightness Decrease

Fn + F7 LCD Brightness Increase

Fn + F8 Disable Touchpad

Fn + F10 Mute

Fn + F11 Toggle Between LCD ON and OFF

Volume Decrease

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Fn + F12 Activate Suspend-to-Disk or Suspend-to-RAM

Fn + F1 Enable/Disable WLAN

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1.3.2 Power on/off/Suspend/Resume Button

APM mode

At APM mode, Power button is on/off system power.

ACPI mode

At ACPI mode. Windows power management control panel set power button behavior. You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power button function.

Continue pushing power button over 4 seconds will force system off at ACPI mode.

1.3.3 Cover Switch

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover.

At ACPI mode there are four functions to be chosen at windows power management control panel.

1. None

2. Standby

3. Off

4. Hibernate (must enable hibernate function in power management)

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1.3.4 LED Indicators

1.3.4.1 Three LED Indicators

There are 2 sets of 3 LED indicators on panel housing and above keyboard separately.

From left to right that indicate WIRELESS LAN, POWER, BATTERY STATUS

Wireless LAN

This LED lights green when operated in wireless LAN mode, otherwise it turns off.

Power

This LED lights green when the notebook was powered by AC power line or Battery, Flashes (on 1 second, off 1 second) when entered suspend to RAM state. The LED is off when the notebook is in power off state.

Battery Status

During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged.

1.3.4.2 Five LED Indicators

System has 4 status LED indicators at front side which to display system activity. From left to right that indicate HARD DISK, NUM LOCK, CAPS LOCK, SCROLL LOCK.

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1.3.5 Battery Status

1.3.5.1 Battery Warning

System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store data before battery dead. This function also protects system from mal-function while battery capacity is low.

Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.

System will Suspend to HDD after 2 Minutes to protect users data.

1.3.5.2 Battery Low State

After Battery Warning State and battery capacity is below 5%, system will generate beep sound for twice per second.

1.3.5.3 Battery Dead State

When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend the battery packs' life.

1.3.6 Fan Power on/off Management

FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.

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1.3.7 CMOS Battery

CR2032 3V 220mAh lithium battery

When AC in or system main battery inside, CMOS battery will consume no power

AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years

1.3.8 I/O Port

One Power Supply Jack.

One External CRT Connector For CRT Display

Supports four USB port for all USB devices

One RJ-45 for LAN

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Headphone Out Jack

Microphone Input Jack

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1.3.9 Battery Current Limit and Learning

Implanted H/W current limit and battery learning circuit to enhance protection of battery

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1.4 Power Management

The 8965 system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.

1.4.1 System Management Mode

Full on Mode

In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.

Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability.

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The CPU power consumption and temperature is lower in this mode.

Standby Mode

For more power saving, it turns off the peripheral components. In this mode, the following is the status of each

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device:

- CPU: stop grant

- LCD: backlight off

- HDD: spin down

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Suspend to DRAM and HDD

The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device

 Suspend to DRAM

- CPU: off

- Intel 855GME: partial off

- VGA: suspend

- PCMCIA: suspend

- Audio: off

- SDRAM: self refresh

 Suspend to HDD

- All devices are stopped clock and power-down

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- System status is saved in HDD

- All system status will be restored when powered on again

1.4.2 Other Power Management Functions

HDD & Video Access

System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending

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on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.

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1.5 Appendix 1: VIA VT8235CE GPI/O Pin Definitions (1)

Pin name MUX Function GPIO Function Power plane

GPI0

GPO0

GPI1 SCI# GPI

GPO1 SUSA# GPO

GPI2

GPO2 SUSB# GPO

GPI3 WAKE_UP# GPI

GPO3 SUSST# GPO

GPI4 LIDSW# GPI4

GPO4 SPK_OFF GPO

GPI5 CARD_RI# GPI

GPO5 CPU_STP# GPO

GPI6 AGPBUSY# GPI

GPO6 PCI_STP# GPO

GPI7 PCI_REQ5# GPI

/CB# GPI

IRELESS_PD# GPO

XTSMI# GPI

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GPO7

CI_GNT5# GPO

GPIO12

CI_INTE# GPIO

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1.5 Appendix 1: VIA VT8235CE GPI/O Pin Define (2)

Continue to the previous page

Pin name MUX Function GPIO Function Power plane

GPIO13

GPIO14 CRT_IN# GPIO

GPIO15 ENABKL_SB GPIO

GPI16 X GPI

GPI17 X GPI

GPI18 SB_THRM# GPI

GPIO20 X GPIO

GPIO21 X GPIO

GPIO22 MINIPCI_ACT# GPIO

GPIO23 HDPSLP# GPIO

GPIO26 SMBDATA2 GPIO

GPIO27 SMBCLK2 GPIO

GPIO28 X GPIO

GPIO29 DPRSLPVR GPIO

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BD_US/JP# GPIO

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1.6 Appendix 2: W83L950D KBC Pins Definitions (1)

Port pin Function Implement

P0 0-7 KO[0..7] P1 0-7 KO[8..15] P3 0-7 P2

0 LPC enable H8_THRM# 1 GPIO x1 H8_WAKE_UP# 2 BATT_G# 3 4 EXTSMI# 5 CAP# 6 NUM# 7 0 H8_ENABKL 1 2 LEARING 3 4 KBRST H8_HRCIN# 5 H8_SCI 6 0 GPIO x1 SW_VDD3 1 H8_LIDSW# 2 BATT_DEAD# 3 4 BATT_LED# 5

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6 BLADJ 7

Scan matrix

SMBUS1 or UART

GPIO x4

Xcin/cout or PWM 2,3

GPIO x2 (INT1)

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GPIO x3 (INT20,30,40)

GPIO x2

KBC_PWRON_VDD3S

D/A, PWM 2,3

KI[0..7]

BATT_R#

SCROLL#

CHARGING

H8_SUSB

H8_PWRON

H8_ADEN#

H8_I_CTR

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1.6 Appendix 2: W83L950D KBC Pins Definitions (2)

Continue to the previous page

Port pin Function Implement

0 PWRBTN# 1 KBC_RI# 2 AC_ POWER# 3 BATT_V 4 BATT_T 5 H8_I_LIMIT 6 H8_PROCHOT# 7 0 T_DATA 1 H8_RSMRST 2 ICH_PWRBTN 3 T_CLK 4 H8_PWRON_SUSB# 5 6 BAT_DATA 7 0 PCICLK_KBC 1 SERIRQ 2 LAD3 3 LAD2 4 LAD1 5 LAD0 6 KBC_PCIRST# 7

A/D (INT5-12)

+BC_CPUCORE

PS/2 port x3

SUSC#

SMBUS

BAT_CLK

LPC interface

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LFRAME#

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2. System View and Disassembly

2.1 System View

2.1.1 Front View

Top Cover Latch



2.1.2 Left-side View

AC Power Connector



USB Ports *2



Line Out Connector



MIC In Connector



RJ-45 Connector



USB Ports *2



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











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2.1.3 Right-side View

RJ-11 Connector



Ventilation Openings



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2.1.4 Rear View

Lock



Battery Pack



VGA Port







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





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2.1.5 Bottom View

Hard Disk Drive



DDR-SDRAM



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

CPU



Battery Park



2.1.6 Top-open View

LCD Screen



Stereo Speaker Set



Power Button



Keyboard



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Device LED Indicators



Touch Pad



Battery Charge Indicator





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



















AC Power Indicator



Wireless Indicator







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2.2 Tools Introduction

1. Minus screw driver with bit size 2mm for notebook assembly & disassembly.

2. Auto screw driver for notebook assembly & disassembly.

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2mm

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Screw Size Tooling Tor. Bit Size

1. M2.0 Auto-Screw driver 2.0-2.5 kg/cm2 #0

Bit Size

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2.3 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations.Use the chart below to determine the disassembly sequence for removing components from the notebook.

NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power.

2.3.1 Battery Pack

2.3.2 Keyboard

NOTEBOOK

Modular Components

2.3.3 CPU

2.3.4 HDD Module

2.3.5 DDR-SDRAM

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2.3.6 LCD Assembly

LCD Assembly Components

2.3.7 LCD Panel

2.3.8 Inverter Board

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2.3.9 Modem Card

2.3.10 System Board

Base Unit Components

2.3.11 Modem Board

2.3.12 Touch Pad

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2.3.1 Battery Pack

Disassembly

1. Carefully put the notebook upside down.

2. Slide the two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of the compartment (). (Figure 2-1)





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Figure 2-1 Remove the battery pack

Reassembly

1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound.

2. Slide the release lever to the “lock” ( ) position.

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2.3.2 Keyboard

Disassembly

1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)

2. Push the keyboard cover to loose the locks from the battery compartment. (Figure 2-2)

3. Lift the keyboard cover up. (Figure 2-3)

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Figure 2-2 Push the keyboard cover Figure 2-3 Lift the keyboard cover

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4. Slightly lift up the keyboard. (Figure 2-4)

5. Disconnect the cable from the system board, then separate the keyboard. (Figure 2-5)

Figure 2-4 Lift the keyboard Figure 2-5 Disconnect the cable

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Reassembly

1. Reconnect the keyboard cable and fit the keyboard back into place.

2. Replace the keyboard cover.

3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

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2.3.3 CPU

Disassembly

1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)

2. Remove the four screws fastening the CPU cover. (Figure 2-6)

3. Remove the four spring screws and two screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from the system board. (Figure 2-7)

Figure 2-6 Remove the four screws

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Figure 2-7 Free the heatsink

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4. To remove the existing CPU, loosen the screw by a flat screw driver, upraise the CPU socket to unlock the CPU. (Figure 2-8)

Figure 2-8 Remove the CPU

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Reassembly

1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU.

2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU, then secure with four spring screws and two screws.

3. Replace the CPU cover and secure with four screws.

4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

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2.3.4 HDD Module

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)

2. Remove the two screws fastening the HDD compartment cover. (Figure 2-9)

3. Remove the one screw and slide the HDD module out of the compartment. (Figure 2-10)

cover

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Figure 2-10 Remove HDD moduleFigure 2-9 Remove the HDD compartment

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4. Remove the four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-11)

Figure 2-11 Remove hard disk drive

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Reassembly

1. Attach the bracket to hard disk drive and secure with four screws.

2. Slide the HDD module into the compartment and secure with one screw.

3. Place the HDD compartment cover and secure with two screws.

4. Replace the battery pack. (Refer to section 2.3.1 Reassembly)

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2.3.5 DDR-SDRAM

Disassembly

1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly)

2. Remove the three screws fastening the DDR cover. (Figure 2-12)

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Figure 2-13 Remove the SO-DIMMFigure 2-12 Remove the three screws

3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-13)

Reassembly

1. To install the DDR, match the DDR's notched part with the socket's projected part and firmly insert the SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR into position.

2. Replace the DDR cover and secure with three screws.

3. Replace the battery pack. (See section 2.3.1 Reassembly)

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2.3.6 LCD ASSY

Disassembly

1. Remove the battery pack and keyboard. (See sections 2.3.1 and 2.3.2 Disassembly)

2. Remove the CPU cover. (Refer to the step 2 of section 2.3.3 Disassembly)

3. Remove the DDR cover. (Refer to the step 2 of section 2.3.5 Disassembly)

4. Separate the antenna from the system board. And disconnect the inverter board’s cable from the system board. (Figure 2-14)

5. Remove the two hinge covers. (Figure 2-15)

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Figure 2-14 Separate the antenna and

disconnect the cable

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Figure 2-15 Remove the two hinge covers

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6. Disconnect the cable from the system board, then separate the inverter board’s cable and the antenna from the housing. (Figure 2-16)

7. Remove the four screws, then free the LCD assembly. (Figure 2-17)

Figure 2-16 Free the cables Figure 2-17 Free the LCD assembly

Reassembly

1. Attach the LCD assembly to the base unit and secure with four screws.

2. Replace the antenna back into Mini PCI compartment.

3. Reconnect the two cables to the system board.

4. Replace the two hinge covers.

5. Replace the DDR cover. (Refer to the step 2 of section 2.3.5 Reassembly)

6. Replace the CPU cover. (Refer to the step 3 of section 2.3.3 Reassembly)

7. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)

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2.3.7 LCD Panel

Disassembly

1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.6 Disassembly)

2. Remove the two rubber pads and two screws on the corners of the panel. (Figure 2-18)

3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process until the cover is completely separated from the housing.

4. Remove the eight screws and disconnect the cable. (Figure 2-19)

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Figure 2-18 Remove LCD cover

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Figure 2-19 Remove the eight screws and

disconnect the cable

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5. Remove the four screws that secure the LCD brackets. (Figure 2-20)

6. Disconnect the cable to free the LCD panel. (Figure 2-21)

Figure 2-20 Remove the four screws

Figure 2-21 Free the LCD panel

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Reassembly

1. Replace the cable to the LCD panel.

2. Attach the LCD panel’s brackets back to LCD panel and secure with four screws.

3. Replace the LCD panel into LCD housing and secure with eight screws.

4. Reconnect one cable to inverter board.

5. Fit the LCD cover and secure with two screws and rubber pads.

6. Replace the LCD assembly, keyboard and battery pack. (See sections 2.3.6, 2.3.2 and 2.3.1 Reassembly)

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2.3.8 Inverter Board

Disassembly

1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.6 Disassembly)

2. Remove the LCD cover. (Refer to the steps 1-3 of section 2.3.7 Disassembly )

3. Remove the two screws fastening the inverter board and disconnect the cable, then free the inverter board. (Figure 2-22)

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Figure 2-22 Free the inverter board

Reassembly

1. Reconnect the cable. Fit the inverter board back into place and secure with two screws.

2. Replace the LCD cover. (Refer to section 2.3.7 Reassembly)

3. Replace the LCD assembly. (Refer to section 2.3.6 Reassembly)

4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)

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2.3.9 Modem Card

Disassembly

1. Remove the battery, keyboard, CPU, hard disk drive, DDR and LCD assembly. (Refer to sections 2.3.1, 2.3.2,

2.3.3, 2.3.4, 2.3.5 and 2.3.6 Disassembly)

2. Remove the three screws fastening the housing. (Figure 2-23)

3. Disconnect the (L&R) speakers’ cables from the system board and remove the twenty-two screws fastening the housing, then free the housing. (Figure 2-24)

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Figure 2-23 Remove the three screws

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Figure 2-24 Free the housing

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4. Disconnect the modem card’s cable, then remove the two screws and free the modem card. (Figure 2-25)

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Figure 2-25 Free the modem card

Reassembly

1. Replace the modem card into the system board and secure with two screws.

2. Reconnect the modem card’s cable into the modem board.

3. Replace the housing and secure with twenty-five screws.

4. Reconnect the (L&R) speakers’ cables into the system board.

5. Replace the LCD assembly, DDR, hard disk drive, CPU, keyboard and battery pack. (Refer to previous section reassembly)

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2.3.10 System Board

Disassembly

1. Remove the battery, keyboard, CPU, hard disk drive, DDR, LCD assembly and modem card. (Refer to sections

2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.9 Disassembly)

2. Disconnect the touch pad’s cable from the system board. (Figure 2-26)

3. Remove the four screws fastening the system board and free the system board. (Figure 2-27)

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Figure 2-26 Disconnect the cable

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Figure 2-27 Free the system board

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Reassembly

1. Replace the system board into the top cover and secure with four screws.

2. Turn over the base unit, then reconnect the touch pad’s cable.

3. Replace modem card, LCD assembly, DDR, DDR, hard disk drive, CPU, keyboard and battery pack. (Refer to previous section reassembly)

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2.3.11 Modem Board

Disassembly

1. Remove the battery, keyboard, CPU, hard disk drive, DDR, LCD assembly and modem card. (Refer to sections

2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6 and 2.3.9 Disassembly)

2. Remove the two screws fastening the modem board and free the modem board. (Figure 2-28)

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Figure 2-28 Free the modem board

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Reassembly

1. Replace the modem board into the top cover and secure with two screws.

2. Replace the modem card, LCD assembly, DDR, DDR, hard disk drive, CPU, keyboard and battery pack. (Refer to previous section reassembly)

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2.3.12 Touch Pad

Disassembly

1. Remove the battery pack, keyboard, CPU, hard disk drive, DDR, LCD assembly, modem card and the system board. (See sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.9 and 2.3.10 Disassembly)

2. Remove the four screws and lift the shielding, then free the touch pad. (Figure 2-29)

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Figure 2-29 Free the touch pad

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Reassembly

1. Replace the touch pad, then fit the shielding and secure with four screws.

2. Replace the battery pack, keyboard, CPU, hard disk drive, DDR, LCD assembly, modem card and the system board. (See sections previous section reassembly)

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3. Definition & Location of Connectors / Switches

3.1 Mother Board (Side A) - 1

J718

PJ701 : Power Jack

J1003

J1004

J701 : External VGA Connector J703,J1002 : USB Port J704 : Line Out Jack J705 : Battery Connector J706 : MIC In Jack J715 : RJ45 Connector J718 : HDD Connector J1003,J1004 : USB Port

J715

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J706

J704 J703

J1002

J705

J701

PJ701

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3. Definition & Location of Connectors / Switches

3.1 Mother Board (Side A) - 2

J1006 J1001

J719

J717

J716

J710 J711

J709

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J712

J1001 : Inverter Board Connector J1006 : MDC Jump Wire Connector J709 : Internal Left Speaker Connector J710 : Internal Right Speaker Connector J711 : CPU Fan Connector J712 : RTC Battery Connector J716,J719 : DDR_SODIMM Socket J717 : Mini PCI Socket

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3. Definition & Location of Connectors / Switches

3.1 Mother Board (Side B )

J2 : Internal Keyboard Connector J3 : Touch-Pad Connector

SW1

SW2

SW4

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J2J3

J4 : LCD Connector

SW1 : Touch-Pad Left Button SW2 : Touch-Pad Right Button SW4 : Power Button

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3. Definition & Location of Connectors / Switches

3.2 Modem Board (Si de A)

J1 : RJ11 Connector J2 : MDC Board Connector

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4. Definition & Location of Major Components

4.1 Mother Board (Side A)

U713

U709

U711

U702 : ALC655 Audio Codec U704 : CPU (Pentium-M/Celeron-M) Socket U709 : NB VIA PN800

U704

U711 : SB VIA VT8235CE U713 : ICS950902 Clock Generator

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U702

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4. Definition & Location of Major Components

4.1 Mother Board (Side B )

U16 : System BIOS

U17

U16

U17 : KBC (W83L950D)

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5. Pin Descriptions of Major Components

5.1 Intel Pentium M Processor CPU - 1

CPU Pin Description

`Signal Name Type Description

A[31:3]#

A20M#

ADS#

ADSTB[1:0]#

BCLK[1:0]

BNR#

BPM[2:0]# BPM[3]

I/O A[31:3]# (Address) define a 2 32 -byte physical memory address space.

In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of both agents on the Intel Pentium M synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted.

I If A20M# (Address-20 Mask) is asserted, the processor masks physical

address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

I/O ADS# (Address Strobe) is asserted to indicate the validity of the

transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.

I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising

and falling edges. Strobes are associated with signals as shown below.

Signals Associated Strobe

REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]#

I The differential pair BCLK (Bus Clock) determines the system bus

frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs.

I/O BNR# (Block Next Request) is used to assert a bus stall by any bus agent

that is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance

I/O

monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents. This includes debug or performance monitoring tools.

rocessor system bus. A[31:3]# are source

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CPU Pin Description (Cont inued)

Signal Name Type Description

BPRI#

BR0#

COMPP3:0]

D[63:0]#

I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the

I/O BR0# is used by the processor to request the bus. The arbitration is done

Analog COMP[3:0] must be terminated on the system board using precision

I/O D[63:0]# (Data) are the data signals. These signals provide a 64-

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DBR#

O DBR# (Data Bus Reset) is used only in processor systems where no

processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.

between the Intel Pentium M processor (Symmetric Agent) and the MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM chipset.

(1% tolerance) resistors. Refer to the platform design guides for more implementation details.

it data path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#.

Quad-Pumped Signal Groups

Data Group DSTBN#/DSTBP# DINV#

D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2

D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high.

debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal.

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CPU Pin Description (Cont inued)

Signal Name Type Description

DBSY#

DEFER#

DINV[3:0]#

DPSLP#

DRDY#

DSTBN[3:0]#

DSTBP[3:0]#

I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for driving

data on the processor system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal must connect the appropriate pins on both processor system bus agents.

I DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both processor system bus agents.

I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate

the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.

DINV[3:0]# Assignment To Data Bus

Bus Signal Data Bus Signals

DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]#

I DPSLP# when asserted on the platform causes the processor to

transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset.

I/O DRDY# (Data Ready) is asserted by the data driver on each data

transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both processor system bus agents.

I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBN[0]# D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]#

I/O Data strobe used to latch in D[63:0]#.

Signals Associated Strobe

D[15:0]#, DINV[0]# DSTBP[0]# D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]#

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CPU Pin Description (Cont inued)

Signal Name T ype Description

DPWR#

FERR#/PBE#

GTLREF

HIT# HITM#

I DPWR# is a control signal from the Intel 855PM and Intel 855GM

O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a

I GTLREF determines the signal reference level for AGTL+ input pins.

I/O I/O

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IERR#

IGNNE#

REQ[4:0]#

O IERR# (Internal Error) is asserted by a processor as the result of an

I IGNNE# (Ignore Numeric Error) is asserted to force the processor to

I/O REQ[4:0]# (Request Command) must connect the appropriate pins of

chipsets used to reduce power on the Intel Pentium M data bus input buffers.

multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 80387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event.

VCCP

GTLREF should be set at 2/3 receivers to determine if a signal is a logical 0 or logical 1. HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.

internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.

ignore a numeric error and continue to execute noncontrol floating- instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction.

both processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[0]#.

. GTLREF is used by the AGTL+

oint

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CPU Pin Description (Cont inued)

Signal Name Type Description

INIT#

LINT[1:0]

LOCK#

PRDY#

PREQ#

PROCHOT#

PSI#

I INIT# (Initialization), when asserted, resets integer registers inside the

processor without affecting its internal caches or floating- The processor then begins execution at the power on Reset vector configured during power on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST)

I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of

all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration.

I/O LOCK# indicates to the system that a transaction must occur atomically.

This signal must connect the appropriate pins of both processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock.

O Probe Ready signal used by debug tools to determine processor debug

readiness.

I Probe Request signal used by debug tools to request debug operation of

the processor.

O PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal may require voltage translation on the motherboard.

O Processor Power Status Indicator signal. This signal is asserted when the

processor is in a lower state (Deep Sleep and Deeper Sleep).

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CPU Pin Description (Cont inued)

Signal Name Type Description

oint registers.

PWRGOOD

ITP_CLK[1:0]

RESET#

I PWRGOOD (Power Good) is a processor input. The processor requires

I ITP_CLK[1:0] are copies of BCLK that are used only in processor

I Asserting the RESET# signal resets the processor to a known state and

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RS[2:0]#

RSVD

SLP#

I RS[2:0]# (Response Status) are driven by the response agent (the agent

- These pins are RESERVED and must be left unconnected on the board.

I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to

this signal as a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation.

systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects. These are not processor signals.

invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both system bus agents will deassert their outputs within two clocks. All processor straps must be valid within the specified setup time before RESET# is deasserted.

responsible for completion of the current transaction), and must connect the appropriate pins of both processor system bus agents.

However, it is recommended that routing channels to these pins on the board be kept open for possible future use. Please refer to the platform design guides for more details.

enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state.

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CPU Pin Description (Cont inued)

Signal Name Type Description

SMI#

STPCLK#

TCK

TDI

TDO

TEST1, TEST2, TEST3 THERMDA THERMDC THERMTRIP#

TMS

TRDY#

TRST#

I SMI# (System Management Interrupt) is asserted asynchronously by

system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs.

I STPCLK# (Stop Clock), when asserted, causes the processor to enter a

low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input.

I TCK (Test Clock) provides the clock input for the processor Test Bus

(also known as the Test Access Port).

I TDI (Test Data In) transfers serial test data into the processor. TDI

provides the serial input needed for JTAG specification support.

O TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

I TEST1, TEST2, and TEST3 must be left unconnected but should have a

stuffing option connection to V SS separately using 1-k, pull-down resisitors.

Other Thermal Diode Anode. Other Thermal Diode Cathode.

O The processor protects itself from catastrophic overheating by use of an

internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.

I TMS (Test Mode Select) is a JTAG specification support signal used by

debug tools.

I TRDY# (Target Ready) is asserted by the target to indicate that it is

ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents.

I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#

must be driven low during power on Reset.

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CPU Pin Description (Cont inued)

Signal Name Type Description

VCC VCCA[3:0] VCCP VCCQ[1:0]

VCCSENSE

VID[5:0]

VSSSENSE

I Processor core power supply. I VCCA provides isolated power for the internal processor core PLL’s. I Processor I/O Power Supply. I Quiet power supply for on die COMP circuitry. These pins should be

O VCCSENSE is an isolated low impedance connection to processor core

O VID[5:0] (Voltage ID) pins are used to support automatic selection of

O VSSSENSE is an isolated low impedance connection to processor core

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connected to VCCP on the motherboard. However, these connections should enable addition of decoupling on the VCCQ lines if necessary.

power (VCC ). It can be used to sense or measure power near the silicon with little noise.

power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Pentium M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations.

VSS. It can be used to sense or measure ground near the silicon with little noise.

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CPU Interface

Signal Name Pin # I/O Signal Description

HA[35:3]#

HADSTB [1:0]#

HD[63:0]#

HDBI[3:0]#

HDSTBP [3:0]# HDSTBN [3:0]#

ADS#

DBSY#

DRDY# HIT#

HITM#

(see pin

lists)

C26, A22 IO Host CPU Address Strobe. Source synchronous strobes used

(see pin

lists)

A5, J3,

B13, A6

D1, H3, E13, F8 E1, H2,

D13, D8

A19 IO Address Strobe. The CPU asserts ADS# in T1 of the CPU bus

B19 IO Data Bus Busy. Used by the data bus owner to hold the data

C19 IO Data Ready. Asserted for each cycle that data is transferred. C17 IO Hit. Indicates that a caching agent holds an unmodified version

F16 I Hit Modified. Asserted by the CPU to indicate that the address

IO Host CPU Address Bus. Connect to the address bus of the host

CPU. Inputs during CPU cycles and driven by the North Bridge during cache snooping operations. Address signals up through HA[35]# allow future support of a 64 Gbyte memory space (the current design supports up to HA[33]# for support of 16 GB)..

to transfer HA[31:3]# and HREQ[4:0]# at a 2x transfer rate. HASTB1# is the strobe for HA[31:17]# and HASTB0# is the strobe for HA[16:3] and HREQ[4:0]#.

IO Host CPU Da ta. These signals are connected to the CPU data

bus.

IO Host CPU Dy nami c Bus Inversion. Driven along with

HD[63:0]# to indicate if the associated signals are inverted or not. Used to limit the number of simultaneously switching signals to 8 for the associated 16-bit data pin group (HDBI3# for HD[63:48]#, HDBI2# for HD[47:32]#, HDBI1# for HD[31:16]#, and HDBI0# for HD[15:0]#). HDBIn# is asserted such that the number of data bits driven low for the corresponding group does not exceed 8.

IO Host CPU Di fferential Data Strobes. Source synchronous

strobes used to transfer HD[63:0]# and HDBI[3:0]# at a 4x transfer rate. HDSTBP3# / HDSTBN3# are the strobes for HD[63:48]# & HDBI3#; HDSTBP2# / HDSTBN2# are the strobes for HD[47:32]# & HDBI2#; HDSTBP1# / HDSTBN1# are the strobes for HD[31:16]# & HDBI1#; and HDSTBP0# / HDSTBN0# are the strobes for HD[15:0]# & HDBI0#.

cycle.

bus for transfers requiring more than one cycle.

of the requested line. Also driven in conjunction with HITM# by the target to extend the snoop window.

is modified in the L1 cache and needs to be written back.

CPU Interface (Continued)

Signal Name Pin # I/O Signal Description

HLOCK#

HREQ[4:0]#

HTRDY#

RS[2:0]#

DPWR#

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BREQ0# BPRI#

BNR#

DEFER#

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CPURST#

Note: Clocking of the CPU interface is performed with HCLK+ and HCLK– (see clock pin description group).

F18 I Host Lock. All CPU cycles sampled with the assertion of

F19, E19,

D20, C20,

D19

G18 IO Host Target Ready. Indicates that the target of the processor

B17, D18,

B18

G15 O Data Bus Power Reduction. Request to reduce power on the

E18 O Bus Request 0. Bus request output to CPU. C16 IO Priority Agent Bus Request. The owner of this signal will

C18 IO Block Next Request. Used to block the current request bus

E17 IO Defer. The PN800 uses a dynamic deferring policy to optimize

K6 O CPU Reset. Reset output to CPU. External pullup and filter

HLOCK# and ADS# until the negation of HLOCK# must be atomic.

IO Request Command. Asserted during both clocks of the request

phase. In the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type.

transaction is able to enter the data transfer phase.

IO Response Signals. Indicates the type of response per the table

below:

RS[2:0]# Response type RS[2 :0]# Response type

000 Idle State 100 Hard Failure 001 Retry Response 101 Normal Without Data 010 Defer Response 110 Implicit Writeback 011 Reserved 111 Normal With Data

mobile CPU data bus input buffer. Connect to mobile CPU if used.

always be the next bus owner. This signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the HLOCK# signal is asserted. The PN800 drives this signal to gain control of the processor bus.

owner from issuing new requests. This signal is used to dynamically control the processor bus pipeline depth.

system performance. The PN800 also uses the DEFER# signal to indicate a processor retry response.

capacitor to ground should be provided per CPU manufacturer’s recommendations.

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DDR SDRAM Interface – “A” Data

Signal Name Pin # I/O Signal Description

MDA[63:0]

DQMA[7:0]

DQSA[7:0]# AR16,

CSA[3:0]#

CKEA[3:0]

(see pin

lists)

AT16, AP20,

AP24, AN32, AD35,

V34, L33,

D36

AN20,

AT24,

AT33, AD34,

U34, L31,

D35 AP25, AP29,

AR25,

AT25 L34, R35, M35, T33

IO Memory Data. These signals are connected to the DRAM data

bus. Output drive strength may be set by Device 0 Function 3 RxE2.

O Data Mask. Data mask of each byte lane. Output drive strength

may be set by Device 0 Function 3 RxE2.

IO DDR Data Strobe. Data strobe of each byte lane. Output drive

strength may be set by Device 0 Function 3 RxE0.

O Chip Select. Chip select of each bank. Output drive strength

may be set by Device 0 Function 3 RxE4.

O Clock Enables. Clock enables for each DRAM bank for

powering down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in high-speed memory systems.

DDR SDRAM Interface – “B” Data

Signal Name Pin # I/O Signal De scription

MDB[63:0]

DQMB[7:0]

DQSB[7:0]# AP18,

CSB[3:0]#

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CKEB[3:0]

(see pin

lists)

AN18, AP22, AR28, AG32,

Y33, N35,

H36, A34

AR22, AT28, AG33,

Y34, N34,

H34, A33

AP28, AR29, AT29,

AT30

J35, K31,

J33, K32

IO Memory Data. These signals are connected to the DRAM data

bus. Output drive strength may be set by Device 0 Function 3 RxE2.

O Data Mask. Data mask of each byte lane. Output drive strength

may be set by Device 0 Function 3 RxE2.

IO DDR Data Strobe. Data strobe of each byte lane. Output drive

strength may be set by Device 0 Function 3 RxE0.

O Chip Select. Chip select of each bank. Output drive strength

may be set by Device 0 Function 3 RxE4.

O Clock Enables. Clock enables for each DRAM bank for

powering down the SDRAM or clock control for reducing power usage and for reducing heat / temperature in high-speed memory systems.

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AGP 8x / 4x Bus Interface

Signal Name Pin # I/O Signal Description

GADSTB1F

(GADSTB1 for 4x), GADSTB1S (GADSTB1# for 4x)

GFRAME

(GFRAME# for 4x)

GDEVSEL

(GDEVSEL# for 4x)

GIRDY

(GIRDY# for 4x)

GTRDY

(GTRDY# for 4x)

AGP8XDET#

AG3

AG1

AL4 IO Frame. Assertion indicates the address phase of a PCI transfer.

AK1 IO Device Select (PCI transactions only). Driven by the North

AL5 IO Initiator Ready. (Interpreted as active low for PCI/AGP4x and

AK3 IO Target Ready. (Interpreted as active low for PCI/AGP4x and

AB1 I AGP 8x Transfer Mode D et ect. Low indicates that the external

IO Bus Strobe 1. Source synchronous strobes for GD[31:16] (i.e.,

the agent that is providing the data drives these signals). For 8x transfer mode, GADSTB1 is interpreted as GADSTB1F (“First” strobe) and GADSTB1# as GADSTB1S (“Second” strobe). GADSTB1 and GADSTB1# provide timing for 4x transfer mode.

Negation indicates that one more data transfer is desired by the cycle initiator. Interpreted as active high for 8x.

Bridge when a PCI initiator is attempting to access main memory. Input when the chip is acting as PCI initiator. Not used for AGP cycles. Interpreted as active high for AGP 8x.

high for AGP 8x). For AGP write cycles, the assertion of this pin indicates that the master is ready to provide all write data for the current transaction. Once this pin is asserted, the master is not allowed to insert wait states. For AGP read cycles, the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data. The master is never allowed to insert a wait state during the initial block of a read transaction. However, it may insert wait states after each block transfers. For PCI cycles, asserted when initiator is ready for data transfer.

high for AGP 8x). For AGP cycles, indicates that the target is ready to provide read data for the entire transaction (when the transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data when the transfer requires more than four clocks to complete. The target is allowed to insert wait states after each block transfer for both read and write transactions. For PCI cycles, asserted when target is ready for data transfer.

graphics card can support 8x transfer mode. Readable in Device 0 Function 0 Rx84[3].

AGP 8x / 4x Bus Interface (Continued)

Signal Name Pin # I/O Signal Descripti on

GD[31:0]

GC#BE[3:0]

(GCBE#[3:0] for 4x mode)

GPAR

GDBIH /

GDBIL

GPIPE#

(see pin

list)

AK5, AK2,

AL3, AN4

AN3 IO

AF4 AG4 IO Dynamic Bus Inversion High / Low. AGP 8x transfer mode

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Confidential Document

GADSTB0F

(GADSTB0 for

GADSTB0S

4x), (GADSTB0# for 4x)

AT3

AR3

Address / Data Bus. Address is driven with GADSTB assertion

for AGP-style transfers and with GFRAME# assertion for PCI-style transfers.

Command / Byte Enable. (Interpreted as C/BE# for AGP 4x

and C#/BE for 8x). For AGP cycles these pins provide command information (different commands than for PCI) driven by the master (graphics controller) when requests are being enqueued using GPIPE# (4x only as GPIPE# isn’t used in 8x mode). These pins provide valid byte information during AGP write transactions and are driven by the master. The target (this chip) drives these lines to “0000” during the return of AGP read data. For PCI cycles, commands are driven with GFRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks.

AGP Parity. A single parity bit is provided over GD[31:0] and

GC#BE[3:0].

only. Driven by the source to indicate whether the corresponding data bit group (GDBIH for GD[31:16] and GDBIL for GD[15:0]) needs to be inverted on the receiving end (1 on GDBIx indicates that the corresponding data bit group should be inverted). Used to limit the number of simultaneously switching outputs to 8 for each 16-pin group.

Pipelined Request. Not used by AGP 8x. Asserted by the

master (external graphics controller) to indicate that a full-width request is to be enqueued by the target (North Bridge). The master enqueues one request each rising edge of GCLK while GPIPE# is asserted. When GPIPE# is deasserted no new requests are enqueued across the AD bus.

Note: See RxAE[1] for GPIPE# / GDBIH pin function

selection.

Bus Strobe 0. Source synchronous strobes for GD[15:0] (the

agent that is providing the data drives these signals). For 8x transfer mode, GADSTB0 is interpreted as GADSTB0F (“First” strobe) and GADSTB0# as GADSTB0S (“Second” strobe). GADSTB0 and GADSTB0# provide timing for 4x mode.

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AGP 8x / 4x Bus Interface (Continued)

Signal Name Pin # I/O Signal Description

GSBA[7:0]#

(GSBA[7:0] for 4x)

GSBSTBF

(GSBSTB for 4x), GSBSTBS (GSBSTB# for 4x)

GST[2:0]

AE1, AE4, AE3, AE2,

AD2,

AC3, AC4,

AC1 AD3

AD1

AE6, AE5,

AD6

I Side Band Address. Provides an additional bus to pass address

and command information from the master (graphics controller) to the target (North Bridge). These pins are ignored until enabled.

I Side Band Strobe. Driven by the master to provide timing for

GSBA[7:0]. 8x mode uses GSBSTBF (“First” strobe) and GSBSTBS (“Second” strobe). These signals are interpreted as GSBSTB & GSBSTB# for AGP4x.

O Status (AGP only). Provides information from the arbiter to a

master to indicate what it may do. Only valid while GGNT# is asserted. 000 Indicates that previously requested low priority read or flush data is being returned to the master (graphics controller). 001 Indicates that previously requested high priority read data is being returned to the master. 010 Indicates that the master is to provide low priority write data for a previously enqueued write command. 011 Indicates that the master is to provide high priority write data for a previously enqueued write command. 100 Reserved. (arbiter must not issue, may be defined in the future). 101 Reserved. (arbiter must not issue, may be defined in the future). 110 Reserved. (arbiter must not issue, may be defined in the future). 111 Indicates that the master (graphics controller) has been given permission to start a bus transaction. The master may enqueue AGP requests by asserting GPIPE# or start a PCI transaction by asserting GFRAME#. GST[2:0] are always outputs from the target (North Bridge) and inputs to the master (graphics controller).

AGP 8x / 4x Bus Interface (Continued)

Signal Name Pin # I/O Signal Description

GWBF (GWBF# for 4x) GRBF (GRBF# for 4x)

GREQ (GREQ# for 4x) GGNT (GGNT# for 4x) GSERR

(GSERR# for 4x)

GSTOP

(GSTOP# for 4x) Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are referenced to AGPVREF. Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices. For simplification of the AGP pin description tables above and on the next page, that multiplexing is not shown here (see “Additional I2C

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Interfaces” and “Digital Display” pin description tables later in this document for more information). Note: I/O pads for all pins on this page are powered by VCC15AGP. Input voltage levels are referenced to AGPVREF. Note: The AGP interface pins can be optionally configured as additional interfaces for connecting to external display devices. For simplification of the AGP pin description tables above and on the next page, that multiplexing is not shown here (see “Additional I2C Interfaces” and “Digital Display” pin description tables later in this document for more information). Note: Separate system interrupts are not provided for AGP. The AGP connector provides interrupts via PCI bus INTA-B#. Note: A separate reset is not required for the AGP bus (RESET# resets both PCI and AGP buses) Note: Two mechanisms are provided by the AGP bus to enqueue master requests: GPIPE# (to send addresses multiplexed on the AD lines) and the GSBA port (to send addresses unmultiplexed). AGP masters implement one or the other or select one at initialization time (they are not allowed to change during runtime). Only one of the two will be used; the signals associated with the other will not be used. GRBF# has an internal pullup to maintain it in the de-asserted state in case it is not implemented on the master device. AGP 8x mode allows only GSBA (GPIPE# isn’t used in 8x mode). Note: AGP 8x signal levels are 0V and 0.8V. AGP 8x mode maintains most signals at a low level when inactive resulting in no current flow.

AB2 I

AE7 I Read Buffer Full. Indicates if the master (graphics controller)

AD4 I Request. Master (graphics controller) request for use of the

AD5 O Grant. Permission is given to the master (graphics controller) to

AN1 IO

AM3 IO Stop. Asserted by the target to request the master to stop the

Write Buffer Full.

is ready to accept previously requested low priority read data. When GRBF# is asserted, the North Bridge will not return low priority read data to the graphics controller.

AGP bus.

use the AGP bus.

System Error.

current transaction. Interpreted as active high for AGP 8x.

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CRT Interface

Signal Name Pin # I/O Signal Description

AR AG AB HSYNC VSYNC RSET

I/O pads for the pins in the above table are powered by VCC33GFX (i.e., 3.3V I/O).

Digital Power / Ground

Signal Name Pin # I/O Signal Description

VTT

VCC25MEM

VCC15VL

VCC15AGP

VCC33GFX

VCC15 VSUS15 GND

R1 AO Analog Red. Analog red output to the CRT monitor. R2 AO Analog Green. Analog green output to the CRT monitor.

R3 AO Analog Blue. Analog blue output to the CRT monitor. U4 O Horizontal Sync. Output to CRT. U3 O Vertical Sync. Output to CRT. V7 AI Reference Resistor. Tie to GNDDAC through an external 82 Ω

1%%resistor to control the RAMDAC full-scale current value. See Design Guide for details.

(see pin list

AD16-17 P Power for V-Link I/O Interface Logic (2 Pins).

(see pin list

V13, W13,

Y13

(see pin list

AT14 P Suspend Power (1 Pin). 1.5V ±5%

(see pin list

P Power for CPU I/O Interface Logic (15 Pins).

Typical 1.65V (CPU dependent)

P Power for Memory I/O Interface Logic (25

Pins). 2.5V ±5%.

1.5V ±5%

P Power for AGP Bus I/O Interface Logic (6

Pins). 1.5V ±5%

Power for Graphics Display I/O Logic (3 Pins).

3.3V ±5%

P Power for Internal Logic (51 Pins). 1.5V ±5%

P Digital Ground (161 Pins). Connect to main

ground plane.

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Ultra V-Link Interface

Signal Name Pin # I/O Signal Description

V-Link Data Bus. During system initialization, VD[7:0] are

VD15, VD14, VD13, VD12, VD11, VD10, VD9, VD8, VD7, VD6, VD5, VD4, VD3, VD2, VD1, VD0 VPAR

VBE# UPCMD

UPSTB+ UPSTB– DNCMD

DNSTB+ DNSTB–

Note: I/O pads for the pins in the above table are powered by VCC15VL. Input voltage levels are referenced to VLVREF.

AP13 AN13

AR6 AT6

AM12

AP12

AN6

AM7

AP11

AM11

AP7

AR7 AR11 AN10

AR8

AP8

AT7 IO

AN7 IO AN12 I

AM10 I

AM9 I

AP10 O

AN9 O

AP9 O

used to transmit strap information from the South Bridge (the

straps are not on the VD pins but are on the indicated pins of the

South Bridge chip). Check the strap pin table for details.

IO IO IO IO IO IO IO IO IO IO IO IO IO

V-Link Parity. V-Link Byte Enable. V-Link Command from Client (South Bridge) to Host

(North Bridge). V-Link Strobe from Client to Host.

V-Link Complement Strobe from Client to Host. V-Link Command from Host (North Bridge) to Client

(South Bridge). V-Link Strobe from Host to Client.

V-Link Complement Strobe from Host to Client.

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Dedicated Digital Video Port 0 (DVP0)

Signal Name Pin # I/O Signal Description

TVD11 / DVP0D11 /

CAPD11, TVD10 / DVP0D10 / CAPD10 / strap, TVD9 / DVP0D9 / CAPD9 / strap, TVD8 / DVP0D8 / CAPD8 / strap, TVD7 / DVP0D7 / CAPD7 / strap, TVD6 / DVP0D6 / CAPD6 / strap, TVD5 / DVP0D5 / CAPD5 / strap, TVD4 / DVP0D4 / CAPD4 / strap, TVD3 / DVP0D3 / CAPD3 / strap, TVD2 / DVP0D2 / CAPD2 / strap, TVD1 / DVP0D1 / CAPD1 / strap, TVD0 / DVP0D0 / CAPD0 / strap

TVHS / DVP0HS / CAPHS W4 O TV Encoder 0 Horizontal Sync. Internally pulled

TVVS / DVP0VS / CAPVS V1 O TV Encoder 0 Vertical Sync. Internally pulled

TVDE / DVP0DE W3 O TV Encoder 0 Display Enable. Internally pulled

TVCLKIN / DVP0DET /

CAPBCLK TVCLK / DVP0CLK / CAPACLK The above pins may be connected to an external TV Encoder chip such as a VIA VT1622A or VT1622AM for driving a TV set. I/O pads for the pins on this page are powered by VCC33GFX (3.3V I/O).

AA6

AB6

AB5

AA4

AA5

V2 I TV Encoder 0 Clock In. Feedback from TV

Y4 O TV Encoder 0 Clock Out. Output to TV encoder.

TV Encoder 0 Data.

To configure DVP0 as a TV Out interface port, pins DVP0D[6:5] must be strapped high.

Note: One TV Encoder interface is supported through either DVP0 or GDVP1.

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down.

encoder. Internally pulled down.

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Internally pulled down.

SMB / I2C Interfa ce

Signal Name AGP Name P in # I /O Signal Desc riptio n

SBPLCLK

SBPLDAT

SBDDCCLK

SBDDCDAT

SPCLK2 SPCLK1 /

CAPD12

SPDAT2, SPDAT1 /

CAPD13

I/O pads for SPCLK[2:1] / SPDAT[2:1] above are powered by VCC33GFX (i.e., 3.3V I/O). All other pins in the above table are powered by VCC15AGP (i.e., 1.5V I/O)

GIRDY AL5 IO

GC#BE1 AL3 IO

GREQ AD4 IO

GGNT AD5 IO

n/a n/a

T3 V3

T4 V4

I2C Serial Bus C lock for Panel (M u xed on AGP Bus Pins). I2C Serial Bus Dat a for Panel (Muxed on AGP Bus Pins). I2C Serial Bus Clock for CRT DDC (Muxed on AGP Bus Pins). I2C Serial Bus Data for CRT DDC (Muxed on AGP Bus Pins).

IO Serial Port (SMB/I2C) Clock and Data. The

SPCLKn pins are the clocks for serial data transfer. The SPDATn pins are the data signals used for serial data transfer. SPxxx1 is typically used for DVI monitor communications and SPxxx2 is typically used for DDC for CRT monitor communications. These pins are programmed via “Sequencer” graphics registers (port 3C5) in the “Extended” VGA register space (see the UniChrome-II Graphics Registers document for additional details). The SPxxx1 registers are programmed via 3C5.31 (“IIC Serial Port Control 1”) and the SPxxx2 registers are programmed via 3C5.26 (“IIC Serial Port Control 0”). In both registers, the clock out state is programmed via bit-5 and the data out state via bit-4, clock in status may be read in bit-3 and data in status in bit-2, and the port may be enabled via bit-0.

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CCIR601 / CCIR656 / VIP1.1 / VIP2.0 Video Capture Port (VCP)

Signal Name Pin # I/O Signal Description

I Video Capture Data. To configure DVP0 as a

CAPD15 / GPO0 CAPD14 / GPOUT CAPD13 / SPDAT1 CAPD12 / SPCLK1, CAPD11 / DVP0D11 /

TVD11, CAPD10 / DVP0D10 / TVD10 / strap, CAPD9 / DVP0D9 / TVD9 / strap, CAPD8 / DVP0D8 / TVD8 / strap, CAPD7 / DVP0D7 / TVD7 / strap, CAPD6 / DVP0D6 / TVD6 / strap, CAPD5 / DVP0D5 / TVD5 / strap, CAPD4 / DVP0D4 / TVD4 / strap, CAPD3 / DVP0D3 / TVD3 / strap, CAPD2 / DVP0D2 / TVD2 / strap, CAPD1 / DVP0D1 / TVD1 / strap, CAPD0 / DVP0D0 / TVD0 / strap

CAPHS / DVP0HS / TVHS W4 I Video Capture Horizontal Sync. For capture port

CAPVS / DVP0VS / TVVS V1 I Video Capture Vertical Sy nc. For capture port

V4 V3

AA6

AB6

AB5

AA4

AA5

video capture port, pin DVP0D6 must be strapped low. Pin Function: 8-Bit Mode 16-Bit Mode CAPBD7 CAPAD15 CAPBD6 CAPAD14 CAPBD5 CAPAD13 CAPBD4 CAPAD12 CAPBD3 CAPAD11

CAPBD2 CAPAD10

CAPBD1 CAPAD9

CAPBD0 CAPAD8

CAPAD7 CAPAD7

CAPAD6 CAPAD6

CAPAD5 CAPAD5

CAPAD4 CAPAD4

CAPAD3 CAPAD3

CAPAD2 CAPAD2

CAPAD1 CAPAD1

CAPAD0 CAPAD0

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“A” (16-bit and 8-bit mode). Internally pulled down.

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CCIR601 / CCIR656 / VIP1.1 / VIP2.0 Video Capture Port (VCP) (Continued)

Signal Name Pin # I/O Signal Description

CAPAFLD / BISTIN V6 I

CAPBCLK / DVP0DET /

TVCLKIN

CAPACLK / DVP0CLK / TVCLK

Note: I/O pads for the pins on this page are powered by VCC33GFX (3.3V I/O)

V2 I Vide o Capture Clock B. Port “B” (8-bit mode)

Y4 I Vide o Capture Clock A. Port “A” (16-bit and

Video Capture “A”-Channel TV Field Indicator. For capture port “A” (16-bit and 8-bit

mode).

input clock from external video decoder. Internally pulled down. Not used in 16-bit mode.

8-bit mode) input clock from external video decoder. Internally pulled down.

DDR SDRAM Interface – Address

Signal Name Pin # I/O Signal Description

MAA[13:0], MAB[13:0]

BAA[1:0], BAB[1:0]

SRASA#, SCASA#, SWEA#, SRASB#, SCASB#, SWEB#

Note: I/O pads for all SDRAM pins are powered by VCC25MEM. MD / DQS input voltage levels are referenced to MEMVREF.

(see pin

lists)

AT35, AT31, AF36,

AJ36 AP26, AN25, AR26, AL29, AN28,

AN31

O Memory Address A and B. Two sets for additional drive.

Output drive strength may be set by Device 0 Function 3 RxE8 (MAA) and EA (MAB).

O Bank Address A and B. Two sets for additional drive.

Output drive strength may be set by Device 0 Function 3 RxE8 (BA) and EA (BB).

Row Address, Column Address and Write Enable Command Indicators A and B. Two sets for additional drive.

Output drive strength may be set by Device 0 Function 3 Rx E8 (ScmdA) and EA (ScmdB).

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AGP-Multiplexed Digital Video Port 1 (GDVP1) – TV Encoder

Signal Name AGP Name Pin # I/O Signal Description

GTVD11 / GDVP1D11, GTVD10 / GDVP1D10, GTVD9 / GDVP1D9, GTVD8 / GDVP1D8, GTVD7 / GDVP1D7, GTVD6 / GDVP1D6, GTVD5 / GDVP1D5, GTVD4 / GDVP1D4, GTVD3 / GDVP1D3, GTVD2 / GDVP1D2, GTVD1 / GDVP1D1, GTVD0 / GDVP1D0 GTVHS / GDVP1HS GTVVS / GDVP1VS GTVDE / GDVP1DE GTVCLKIN / FPDET GTVCLK / GDVP1CLK GTVCLK# / GDVP1CLK# The above pins may be connected to an external TV Encoder chip such as a VIA VT1623 or VT1623M for driving a TV set. I/O pads for the pins on this page are powered by VCC15AGP (1.5V I/O). Note: If the FPD port is enabled and TV-out capability is required at the same time, the dedicated TV-out port (DVP0) must be used because pin AG1 will be dedicated to the FPDET function.

GC#BE3

GD26

GD24

GD30

GD28

GD29

GSBA4#

GD27

GSBA5#

GSBSTBS

GSBSTBF

GSBA2#

GSBA3# AD2 O Horizontal Sync. Internally pulled down.

GSBA0# AC1 O Vertical Sync. Internally pulled down.

GSBA1# AC4 O Display Enable. Internally pulled down.

GADSTB1S AG1 I Clock In. Input from TV encoder. Internally

GSBA6# AE4 O Clock Out. Output to TV encoder. Internally

GSBA7# AE1 O Clock Out Complement. Output to TV encoder.

AK5

AH5

AG5

AG6

AH4

AF3

AE2

AG2

AE3

AD1

AD3

AC3

Data.

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pulled down.

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pulled down.

Internally pulled down.

AGP-Multiplexed Digital Video Port 1 (GDVP1) – DVI Interface

Signal Name AGP Name Pin # I/O Signal Description

GDVP1D11 / GTVD11, GDVP1D10 / GTVD10, GDVP1D9 / GTVD9, GDVP1D8 / GTVD8, GDVP1D7 / GTVD7, GDVP1D6 / GTVD6, GDVP1D5 / GTVD5, GDVP1D4 / GTVD4, GDVP1D3 / GTVD3, GDVP1D2 / GTVD2, GDVP1D1 / GTVD1, GDVP1D0 / GTVD0, GDVP1HS / GTVHS GDVP1VS / GTVVS GDVP1DE / GTVDE

GDVP1DET

GDVP1CLK /

GTVCLK GDVP1CLK# / GTVCLK#

GC#BE3

GD26

GD24

GD30

GD28

GD29

GSBA4#

GD27

GSBA5#

GSBSTBS

GSBSTBF

GSBA2#

GSBA3# AD2 O

GSBA0# AC1 O

GSBA1# AC4 O

GD31 AF1 I Display Detect. If VGA register 3C5.3E[0] = 1,

GSBA6# AE4 O

GSBA7# AE1 O

AK5

AH5

AG5

AG6

AH4

AF3

AE2

AG2

AE3

AD1

AD3

AC3

Data.

Horizontal Sync .

Vertical Sync.

Data Enable.

3C5.1A[4] will read 1 if a display is connected. Tie to GND if not used.

Clock.

Clock Complement.

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24-Bit / Dual 12-Bit Flat Panel Display Interface

Signal Name AGP Name Pin # I/O Signal Description

O Flat Panel Data. For 24-bit or dual 12-bit flat

FPD23 / FPD0D11, FPD22 / FPD0D10, FPD21 / FPD0D09, FPD20 / FPD0D08, FPD19 / FPD0D07, FPD18 / FPD0D06, FPD17 / FPD0D05, FPD16 / FPD0D04, FPD15 / FPD0D03, FPD14 / FPD0D02, FPD13 / FPD0D01, FPD12 / FPD0D00, FPD11 / FPD1D11, FPD10 / FPD1D10, FPD09 / FPD1D09, FPD08 / FPD1D08, FPD07 / FPD1D07, FPD06 / FPD1D06, FPD05 / FPD1D05,

GD11

GD13

GD14

GD15

GC#BE2

GD16

GD17

GD18

GD23

GD20

GD22

GADSTB1F

GD1

GD0

GD3

GD4

GD5

GD6

GD7

AM4

AN2

AL1

AP1

AK2

AJ3

AJ1

AJ4

AH3

AH1

AK4

AG3

AP2

AT2

AT5

AR4

AT1

AN5

AT4

panel display modes. Two FPD interface modes, 24-bit and dual 12-bit, are supported. Strapping pin DVP0D4 is used to select the interface mode to theLVDS transmitter chip: Strap High (3C5.12[4]=1): 24-bit Strap Low (3C5.12[4]=0): Dual 12-bit In “24-bit” mode, only one set of control pins is required. However, in dual 12-bit mode, the PN800 provides two sets of control signals that are required for certain LVDS transmitter chips. In 24-bit mode, two operating modes are supported: 3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=0 Double data rate: each rising & falling clock edge transmits a complete 24-bit pixel 3C5.12[4]=1 & 3x5.88[2]=0 & 3x5.88[4]=1 Single data rate: each clock rising edge transmits a complete 24-bit pixel In dual 12-bit mode, 3C5.12[4]=0 & 3x5.88[2] = 1 Double data rate: each rising and falling clock edge transmits half (12 bits) of two 24-bit pixels

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24-Bit / Dual 12-Bit Flat Panel Display Interface (Continued)

Signal Name AGP Name Pin # I/O Signal Description

FPD04 / FPD1D04, FPD03 / FPD1D03, FPD02 / FPD1D02, FPD01 / FPD1D01, FPD00 / FPD1D00 FPHS

FPVS

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FPDE

FPDET

FPCLK

FPCLK# GWBF AB2 O Flat Panel Clock Complement. 24-bit mode or

FP1HS

FP1VS

FP1DE

FP1DET /

GTVCLKIN

FP1CLK FP1CLK#

GADSTB0F

GC#BE0

GADSTB0S

GD10

GD12

GFRAME AL4 O Flat Panel Hor izontal Sync. 24-bit mode or port

GDEVSEL AK1 O Flat Panel Vertical Sync. 24-

GD19 AK6 O Flat Panel Data Enable. 24-bit mode or port 0 in

GADSTB1S AG1 I Flat Panel Detect. 24-bit mode or port 0 in dual

GD21 AH2 O Flat Panel Clock. 24-bit mode or port 0 in dual

GD9 AP3 O Flat Panel Horizontal Sync. For port 1 in dual

GPAR AN3 O Flat Panel Vertical Sync. For port 1 in dual 12-

GSERR AN1 O Flat Panel Data Enable. For port 1 in dual 12-bit

GD8 AM1 I Flat Panel Detect. For port 1 in dual 12-bit mode.

GD2 AP4 O Flat Panel Clock. For port 1 in dual 12-bit mode.

GSTOP AM3 O Flat Panel Clock Complement. For port 1 in dual

AT3

AN4

AR3

AR1

AL2

0 in dual 12-bit mode.

it mode or port 0 in

dual 12-bit mode.

dual 12-bit mode

12-bit mode

port 0 in dual 12-bit mode. For double-data-rate data transfers.

12-bit mode.

mode.

12-bit mode. For double-data-rate data transfers.

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Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test

Signal Name Pin # I/O Signal Description Power Plane

HCLK+

HCLK–

MCLKOA

MCLKIA

MCLKOB

DISPCLKI

DISPCLKO

GCLK XIN

RESET#

PWROK

SUSST#

M5 I Host Clock. This pin receives the host CPU

M6 I Host Clock Complement. Used for Quad Data

B31 O Memory (SDRAM) Clock A. Output from

A32 I Memory (SDRAM) Clock Feedback. Input

A31 O Memory (SDRAM) Clock B. Output from

N3 I Dot Clock (Pixel Clock) In. Used for external

N4 O Dot Clock (Pixel Clock) Out. Used for

N7 I AGP Clock. Clock for AGP logic. N5 I Reference Frequency Input. External

AM13 I Reset. Input from the South Bridge chip. When

AP14 I Power OK. Connect to South Bridge and

AN14 I Suspend Status. For implementation of the

clock (100 / 133 / 166 / 200 / 266 MHz). This clock is used by all PN800 logic that is in the host CPU domain.

Transfer on host CPU bus.

internal clock generator to external memory interface clock buffer (if required for fanout)

from MCLKOA.

internal clock generator to external memory interface clock buffer (if required for fanout)

EMI reduction circuit if used. Connect to GND if external EMI reduction circuit not implemented.

external EMI reduction circuit if used. NC if external EMI reduction circuit not implemented.

14.31818 MHz clock source. All internal graphics controller clocks are synthesized on chip using this frequency as a reference.

asserted, this signal resets the PN800 and sets all register bits to the default value. The rising edge of this signal is used to sample all power-up strap options

Power Good circuitry.

Suspend-to-DRAM feature. Connect to an external pull-up to disable.

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MiTac Secret

VTT

VCC25MEM

VCC33GFX

VCC15AGP VCC33GFX

VSUS15

Clocks, Resets, Power Control, General Purpose I/O, Interrupts and Test (Continued)

Signal Name Pin # I/O S i gnal Description Power P l ane

AGPBUSY# / NMI

GPOUT

CAPD14

GPO0

INTA#

TCLK

TESTIN#

DFTIN#

BISTIN

CAPAFLD

/ CAPD15 V5 O

U2 O

W6 I

C31 I

AL14 O

W5 O

D32 I

V6 I

AGP Interface Busy.

Bridge GPIO pin for monitoring the status of the internal AGP bus. See Design Guide for details. Pin function selectable with Device 0 Function 0 RxBE[7] (default = NMI).

General Purpose Output.

state of SRD[0].

General Output Port.

cleared, this pin reflects the state of CR5C[0].

Interrupt.

interrupt controller in the South Bridge)

Test Clock.

must be connected to GND through a 1K-4.7K ohm resistor for all board designs.

Test In.

be connected to VTT through a 1K-4.7K ohm resistor for all board designs.

DFT In.

be connected to VTT through a 1K-4.7K ohm resistor for all board designs.

BIST In.

be tied to GND with a 1K-4.7K ohm resistor on all board designs.

PCI interrupt output (handled by the

This pin is used for testing and must

Connect to a South

This pin reflects the

When SR1A[4] is

This pin is used for testing and

VCC25MEM

VCC33GFX

VCC25MEM

VCC33GFX

Flat Panel Power Control (Muxed with AGP)

Signal Name AGP Name Pin # I/O Signal Descriptio n

ENAVDD ENAVEE ENABLT

Note: I/O pads for all pins on this page are powered by VCC15AGP (i.e., 1.5V I/O).

ST1 AE5 IO ST0 AD6 IO ST2 AE6 IO

Enable Panel VDD P ower. Enable Panel VEE Power. Enable Panel Back Light.

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Compensation

Signal Name Pin # I/O Signal Description Power Plane

HRCOMP

VLCOMPP

AGPCOMPN

AGPCOMPP

F15 AI Host CPU Compensation. Connect 20.5 §Ù

1% resistor to ground. Used for Host CPU interface I/O buffer calibration.

AM6 AI V-Link Compensation. Connect a 360Ω 1%

resistor to ground.

AB3 AI AGP N Compensation. Connect a 60.4Ω1%

resistor to VCC15AGP.

AC6 AI AGP P Compensation. Connect a 60.4Ω1%

resistor to ground.

VTT

VCC15VL

VCC15AGP

Reference Voltages

Signal Name Pin # I/O Signal Description Power Plane

GTLVREF

HDVREF[0:3]

HAVREF[0:1]

HCOMPVREF

MEMVREF [0:5]

VLVREF

AGPVREF[0:1]

H17 P

H11,

H14, K7,

H19, G22 P Host CPU Address Voltage Reference. 2/3

G14 P

J29, R29, W29, AE29,

AK22,

AK17

AL7 P V-Link Voltage Reference. 0.625V ±2%

AF7,

AD7

Host CPU Interface AGTL+ Voltage Reference. 2/3 VTT ±2% typically derived

using a resistive voltage divider. See Design Guide.

P Host CPU Data Voltage Reference. 2/3 VTT

±2% typically using a resistive voltage divider. See Design Guide.

VTT ±2% typically derived using a resistive voltage divider. See Design Guide.

Host CPU Compensation Voltage Reference.

1/3 VTT ±2% typically derived using a resistive voltage divider. See Design Guide.

P Memory V oltage Referen ce. 0.5 VCC25MEM

±2% typically derived using a resistive voltage divider. See Design Guide.

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derived using a resistive voltage divider. See Design Guide.

P AGP Voltage Reference. ½ VCC15AGP

(0.75V) for AGP 2.0 (4x transfer mode) and

0.23 VCC15AGP (0.35V) for AGP 3.0 (8x transfer mode). See the Design Guide for additional information and circuit implementation details.

VTT

VCC25MEM

VCC15VL

VCC15AGP

Analog Power / Ground

Signal Name Pin # I/O Signal Description

VCCA33HCK1

GNDAHCK1

VCCA33HCK2

GNDAHCK2

VCCA33MCK GNDAMCK

VCCA33GCK GNDAGCK

VCCA15PLL1

GNDAPLL1

VCCA15PLL2

GNDAPLL2

VCCA15PLL3

GNDAPLL3

VCCA33DAC[1:2] GNDADAC[1:3]

M4 P Power for Host CPU Clock PLL 1 (3.3V ±5%).

M3 P Ground for Host CPU Clock PLL 1. Connect to

L1 P Power for Host CPU Clock PLL 2 (3.3V ±5%).

L2 P Ground for Host CPU Cl ock PLL 2. Connect to

D31 P Power for Memory Clock PLL (3.3V ±5%) E31 P Ground for Memory Clock PLL. Connect to

M1 P Power for AGP Clock PLL (3.3V ±5%) M2 P Ground for AGP Clock PLL. Connect to main

P3 P Power for Graphics Controller PLL 1 (1.5V

P2 P

P6 P Power for Graphics Controller PLL 2 (1.5V

N6 P

N1 P Power for Graphics Controller PLL 3 (1.5V

N2 P

T5, P4 P Power for DAC. (3.3V ±5%)

T6, P5, R4 P Ground for DAC. Connect to main ground plane

Host CPU Clock PLL 1 generates 400 MHz for CPU / DRAM frequencies of multiples of 100, 133, and 200 MHz.

main ground plane through a ferrite bead.

Host CPU Clock PLL 2 generates 500 MHz for CPU / DRAM frequencies of multiples of 166 MHz.

main ground plane through a ferrite bead.

ground plane through a ferrite bead.

±5%).

Ground for Graphic s Controller PLL 1 .

Connect to main ground plane through a ferrite bead.

±5%).

Ground for Graphic s Controller PLL 2 .

Connect to main ground plane through a ferrite bead.

±5%).

Ground for Graphic s Controller PLL 3 .

Connect to main ground plane through a ferrite bead.

through a ferrite bead.

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V-Link Interface

Signal Name Pin # I/O Signal Description

(see pin

VD[7:0]

VPAR F24 IO Parity. If the VPAR function is implemented in a compatible

VBE# VCLK UPCMD DNCMD UPSTB UPSTB# DNSTB DNSTB#

IO Data Bus. These pins are also used to send strap information to

list)

G24 IO L22 I K23 O K25 I J26 O J24 O K26 I H24 I

the chipset north bridge. At power up, VD7 reflects the state of a strap on SDCS3#, VD[6:4] reflect the state of straps on pins SDA[2:0], and VD[3:0] reflect the state of straps on pins Strap_VD3-0. The specific interpretation of these straps is north bridge chip design dependent.

manner on the north bridge, this pin should be connected to the north bridge VPAR pin (P4X333, P4X400, P4X800, KT400). If VPAR is not implemented in the north bridge chip or is incompatible with the 8235CE (4x V-Link north bridges) connect this pin to an

8.2K pullup to 2.5V (Pro266, Pro266T, KT266, KT266A, KT333, P4X266, PN266, KN266, KM266, P4M266, P4N266). See app note AN222 for details.

Byte Enable. V-Link Clock. Command from Client-to-Host. Command from Host-to-Client. Strobe from Client-to-Host. Complement Strobe from Client-to-Host. Strobe from Host-to-Client. Complement Strobe from Host-to-Clie nt.

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CPU Interface Signal Name Pin # I/O Signal Description

A20M#

FERR# U24 I Numerical Coprocessor Error. This signal is tied to the

IGNNE#

INIT#

INTR

NMI

SLP# SMI#

STPCLK#

Note: Connect each of the above signals to 150 §Ù pullup resistors to VCC_CMOS (see Design Guide).

U26 OD A20 Mask. Connect to A20 mask input of the CPU to control

address bit-20 generation. Logical combination of the A20GATE input (from internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).

coprocessor error signal on the CPU. Internally generates interrupt 13 if active. Output voltage swing is programmable tot

1.5V or 2.5V by Device 17 Function 0 Rx67[2].

T24 OD Ignore Numeric Error. This pin is connected to the CPU

iPignore errorlr pin.

R26 OD Initialization. The VT8235 Version CE asserts INIT# if it

detects a shut-down special cycle on the PCI bus or if a soft reset is initiated by the register

T25 OD CPU Interrupt. INTR is driven by the VT8235 Version CE to

signal the CPU that an interrupt request is pending and needs service.

T26 OD Non-Maskable Interrupt. NMI is used to force a

non-maskable interrupt to the CPU. The VT8235 Version CE generates an NMI when PCI bus SERR# is asserted.

V26 OD Sleep. Used to put the CPU to sleep. U25 OD System Management Interrupt. SMI# is asserted by the

VT8235 Version CE to the CPU in response to different Power-Management events.

R24 OD Stop Clock. STPCLK# is asserted by the VT8235 Version CE

to the CPU to throttle the processor clock.

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Advanced Programmable Interrupt Controller (APIC) Interface Signal Name Pin # I/O Signal Description

APICD1 APICD0 R25 O Internal APIC Data 0. Function 0 Rx58[6] = 1 APICCLK

T23 O Internal APIC Data 1. Function 0 Rx58[6] = 1

U23 I

APIC Clock.

CPU Speed Control Interface Signal Name Pin # I/O Signal Description

VRDSLP /

GPI29/ GPO29

GHI# / GPI22/

GPO22

DPSLP# /

GPI23/ GPO23 CPUMISS / GPI17

AGPBZ# / GPI6 AD10 I AGP Busy. Low indicates that an AGP master cycle is in

AB9 OD Voltage Regulator Deep Sleep. Connected to the CPU voltage

R22 OD CPU Speed Select. Connected to the CPU voltage regulator,

P21 OD CPU Deep Sleep. This pin performs the DPSLP# function if

Y1 I CPU Missing. Used to detect the physical presence of the CPU

regulator. High selectsthe proper voltage for deep sleep mode. This pin performs the VRDPSLP function if Function 0 RxE5[3] = 0.

used to select high speed (L) or low speed (H). This pin performs the GHI# function if Function 0 RxE5[3] = 0.

Device 17 Function 0RxE5[3]=0.

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chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time.

progress (CPU speed transitions will be postponed if this input is asserted low). Connected to the AGP Bus AGPBZ# pin.

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PCI Bus Interface Signal Name Pin # I/O Signal Description

(see

AD[31:0]

CBE[3:0]# M3, L4,

DEVSEL#

FRAME#

IRDY#

TRDY#

STOP#

SERR#

PERR#

PAR

IO Address / Data Bus. Multiplexed address and data. The address

pinlist)

IO Command / Byte Enable. The command is driven with

C1, E2

H2 IO Device Select. The VT8235 Version CE asserts this signal to

J1 IO Frame. Assertion indicates the address phase of a PCI transfer.

J2 IO Initiator Ready. Asserted when the initiator is ready for data

H1 IO Target Ready. Asserted when the target is ready for data

K4 IO Stop. Asserted by the target to request the master to stop the

C2 I System Error. SERR# can be pulsed active by any PCI device

C3 _ Parity Error. PERR#, sustained tri-state, is only for the

F4 IO Parity. A single parity bit is provided over AD[31:0] and

is driven with FRAME#assertion and data is driven or received in following cycles.

FRAME# assertion. Byteenables corresponding to supplied or requested data are driven on following clocks.

claim PCI transactions through positive or subtractive decoding. As an input, DEVSEL# indicates the response to a VT8235 Version CE-initiated transaction and is also sampled when decoding whether to subtractively decode the cycle.

Negation indicates that one more data transfer is desired by the cycle initiator.

transfer.

current transaction.

that detects a system error condition. Upon sampling SERR# active, the VT8235 Version CE can be programmed to generate an NMI to the CPU.

reporting of data parity errors during all PCI transactions except for a Special Cycle.

C/BE[3:0]#.

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PCI Bus Interface ( C ontinued) Signal Name Pin # I/O Signal Description

INTA# INTB# INTC# INTD# INTE# / GPI12, /

GPO12, INTF# / GPI13, / GPO13, INTG# / GPI14, / GPO14, INTH# / GPI15, / GPO15

REQ5# / GPI7, REQ4#, REQ3#, REQ2#, REQ1#, REQ0# GNT5# / GPO7, GNT4#, GNT3#, GNT2#, GNT1#, GNT0# PCIRST#

PCICLK

PCKRUN#

I PCI Interrupt Request. The INTA# through INTD# pins are

B4 B5 C4 D4

I PCI Request. These signals connect to the VT8235 Version CE

R3 P3 D5 C5 B6 A5 R2

O PCI Grant. These signals are driven by the VT8235 Version

R4 E5 C6 D6 A6 R1 O PCI Reset. This signal is used to reset devices attached to the

R23 I PCI Clock. This signal provides timing for all transactions on

AB7 IO PCI Bus Clock Run. This signal indicates whether the PCI

typically connected to thePCI bus INTA#-INTD# pins per the table below. INTE-H# are enabled by setting Device17, Function 0 Rx5B[1] = 1. BIOS settings must match the physical connection method.

PCI Slot 1 INTA# NTB# INTC# INTD# PCI Slot 2 INTB# INTC# INTD# INTE# PCI Slot 3 INTC# INTD# INTE# INTF# PCI Slot 4 INTD# INTE# INTF# INTG# PCI Slot 5 INTE# INTF# INTG# INTH# PCI Slot 6 INTF# INTG# INTH# INTA#

from each PCI slot (oreach PCI master) to request the PCI bus. To use pin R3 as REQ5#, Function 0 RxE4 mustbe set to 1 otherwise this pin will function as General Purpose Input 7.

CE to grant PCI access to aspecific PCI master. To use pin R2 as GNT5#, Function 0 RxE4 must be set to 1otherwise this pin will function as General Purpose Output 7.

PCI bus.

the PCI Bus.

clock is or will be stopped (high) or running (low). The VT8235 Version CE drives this signal low when the PCI clock is running (default on reset) and releases it when it stops the PCI clock. External devices may assert this signal low to request that the PCI clock be restarted or prevent it from stopping. Connect this pin to ground using a 100 §Ù resistor if the function is not used. Refer to the ihPCI Mobile Design Guidelo and applicable VIA North Bridge Design Guide (KT400A, CLE266, or P4X400) for more details.

INTA# INTB# INTC# INTD#

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LAN Controller - Media Independent Interface ( MII)

Signal Name Pin # I/O PU Signal Description

MCOL MCRS

MDCK

MDIO

MRXCLK

MRXD[3-0]

MRXDV MRXERR

MTXCLK

B11 I A11 I

A7 O

B7 IO

C9 I

C7, A8, B8, C8

D8 I D10 I

C10 I

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MTXD[3-0]

MTXENA

MIIVCC

MIIVCC25

RAMVCC RAMGND

A9, B9, B10, A10 C11 O

D9, E9, E10, E11 D12, E12 E7

Power

Power Power

MII Collision Detect. From the external PHY.

MII Carrier Sense. Asserted by the external PHY when

the media is active. MII Management Data Clock. Sent to the external PHY

as a timing reference for MDIO MII Management Data I/O. Read from the MDI bit or

written to the MDO bit. MII Receive Clock. 2.5 or 25 MHz clock recovered by the

PHY. MII Receive Data. Parallel receive data lines driven by the

external PHY synchronous with MRXCLK. MII Receive Data Valid.

MII Receive Error. Asserted by the PHY when it detects a

data decoding error. MII Transmit Clock. Always active 2.5 or 25 MHz clock

supplied by the PHY. MII Transmit Data. Parallel transmit data lines

synchronized to MTXCLK. MII Transmit Enable. Signals that transmit is active from

the MII port to the PHY.

MII Interface Power. 3.3V ±5%.

MII Suspend Power. 2.5V ±5%.

Power For Internal LAN RAM. 2.5V ±5%. Ground For Internal LAN RAM.

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Serial EEPROM Interface Signal Name Pin # I/O PU Signal Description

EECS# D11 O EECK C12 O EEDO B12 I

EEDI A12 O

Serial EEPROM Chip Select. Serial EEPROM Clock. Serial EEPROM Data Output. Connect to EEPROM Data

Out pin. Serial EEPROM Data Input. Connect to EEPROM Data

In pin.

Low Pin Count (LPC) Interf ace

Signal Name Pin # I/O PU Signal Description

LFRM# AF6 IO LREQ# AE6 IO LAD[3-0] AD7,

AE7, AF7,

AD8

Note: Connect the LPC interface LPCRST# (LPC Reset) signal to PCIRST#

IO PU

LPC Frame. LPC DMA / Bus Master Request. LPC Address / Data.

System Management Bus (SMB) Interface (I 2 C Bus) Signal Name

SMBCK1 SMBCK2 /

GPI27 / GPO27 SMBDT1

SMBDT2 / GPI26 / GPO26 SMBALRT#

Pin # I/O Signal Description

AC4 IO AC3 IO SMB / I 2 C Channel 2 Clock. Rx95[2] = 0

AB2 IO AD1 IO SMB / I 2 C Channel 2 Data. Rx95[2] = 0

AB1 I SMB Alert. (enabled by System Management Bus I/O space

SMB / I 2 C Channel 1 Clock.

SMB / I 2 C Channel 1 Da ta.

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Rx08[3] =

1) When the chip is enabled to allow it, assertion generates an IRQ or SMI interrupt or a power management resume event. Connect to a 10K ohm pullup to VSUS33 if not used.

Universal Serial Bus 2.0 Interface Signal Name Pin # I/O Signal Description

USBP0+

USBP0Œ D20 IO USBP1+ A20 IO USBP1Œ B20 IO USBP2+ E18 IO USBP2Œ D18 IO USBP3+ A18 IO USBP3Œ B18 IO USBP4+ D16 IO USBP4Œ E16 IO USBP5+ A16 IO USBP5Œ B16 IO USBCLK E23 I USB 2.0 Clock. 48MHz clock input for the USB interface USBOC0# C26 I USB 2.0 Port 0 Over Current Detect. Port 0 is disabled if low. USBOC1# D24 I USB 2.0 Port 1 Over Current Detect. Port 1 is disabled if low. USBOC2# B26 I USB 2.0 Port 2 Over Current Detect. Port 2 is disabled if low.

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USBOC3# C25 I USB 2.0 Port 3 Over Current Detect. Port 3 is disabled if low. USBOC4# B24 I USB 2.0 Port 4 Over Current Detect. Port 4 is disabled if low. USBOC5# A24 I USB 2.0 Port 5 Over Current Detect. Port 5 is disabled if low. USBVCC (see pin

USBGND (see pin

VSUSUSB C24

VCCUPLL A23,

GNDUPLL C23,

E20 IO

list)

B23

D23

USB 2.0 Port 0 Data + USB 2.0 Port 0 Data Œ USB 2.0 Port 1 Data + USB 2.0 Port 1 Data Œ USB 2.0 Port 2 Data + USB 2.0 Port 2 Data Œ USB 2.0 Port 3 Data + USB 2.0 Port 3 Data Œ USB 2.0 Port 4 Data + USB 2.0 Port 4 Data Œ USB 2.0 Port 5 Data + USB 2.0 Port 5 Data Œ

USB 2.0 Port Differential Output Interface Logic Voltage. 3.3V

Pow er Pow

USB 2.0 Port Differential Output Interface Logic Ground.

USB 2.0 Suspend Power. 2.5V ±5%.

Pow er

USB 2.0 PLL Analog Voltage. 2.5V ±5%.

Pow er Pow

USB 2.0 PLL Analog Ground.

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UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface Signal Name

PDRDY

/PDDMARDY /PDSTROBE

SDRDY

/SDDMARDY /SDSTROBE

PDIOR#

/PHDMARDY /PHSTROBE

SDIOR#

/SHDMARDY /SHSTROBE

PDIOW# /PSTOP

SDIOW# /SSTOP

PDDRQ SDDRQ

Pin # I/O Signal Description

Y22 I EIDE Mode: Primary I/O Channel Ready. Device ready

AF17 I EIDE Mode: Secondary I/O Channel Ready. Device ready

W26 O EIDE Mode: Primary Device I/O Read. Device read strobe

AF23 O EIDE Mode: Seconda ry Device I/O Read. Device read strobe

Y25 O EIDE Mode: Primary Device I/O Write. Device write strobe

AE23 O EIDE Mode: Secondary Device I/O Write. Device write strobe

Y23 I Primary Device DMA Request. Primary channel DMA request AD17 I Secondary Device DMA Request. Secondary channel DMA

indicator UltraDMA Mode: Primary Device DMA Ready. Output flow control. The device mayassert DDMARDY to pause output transfers Primary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers

indicator UltraDMA Mode: Secondary Device DMA Ready. Output flow control. The devicemay assert DDMARDY to pause output transfers Secondary Device Strobe. Input data strobe (both edges). The device may stop DSTROBE to pause input data transfers

UltraDMA Mode: Primary Host DMA Ready. Primary channel input flow control. Thehost may assert HDMARDY to pause input transfers Primary Host Strobe. Output data strobe (both edges). The host may stop HSTROBE to pause output data transfers

UltraDMA Mode: Secondary Host DMA Ready. Input flow control. The host mayassert HDMARDY to pause input transfers Host Strobe B. Output strobe (both edges). The host may stop HSTROBE to pause output data transfers

UltraDMA Mode: Primary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

UltraDMA Mode: Secondary Stop. Stop transfer: Asserted by the host prior to initiation of an UltraDMA burst; negated by the host before data is transferred in an UltraDMA burst. Assertion of STOP by the host during or after data transfer in UltraDMA mode signals the termination of the burst.

request

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UltraDMA-133 / 100 / 66 / 33 Enhanced IDE Interface (Continued) Signal Name Pin # I/O Signal Description

PDDACK#

SDDACK#

IRQ14 IRQ15 PDCS1#

PDCS3#

SDCS1# / strap AF25 O Secondary Master Chip Select. This signal corresponds to

SDCS3# / strap AF26 O Secondary Slave Chip Select. This signal corresponds to CS37X#

PDA[2-0]

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SDA[2-0] / strap AE24,

PDD[15-0]

SDD[15-0]

Y24 O Primary Device DMA Acknowledge. Primary channel DMA

AD23 O Secondary Device DMA Acknowledge. Secondary channel DMA

AD24 I AE26 I V22 O Primary Master Chip Select. This signal corresponds to CS1FX#

V23 O Primary Slave Chip Select. This signal corresponds to CS3FX# on

W24, V25, W23

AC22, AF24

(see pin list) (see pin list)

Serial IRQ Signal Name Pin # I/O Signal Description

SERIRQ

AD9 I Serial IRQ. This pin has an internal pull-up resistor.

acknowledge

Primary Channel Interrupt Reque st. Secondary Channel Interrupt Request.

on the primary IDE connector.

the primary IDE connector.

CS17X# on the secondary IDE connector. Strap low (resistor to ground) to enable serial EEPROM interface via the MII bus (this disables the EExx pins). This pin has an internal pullup to default to serial EEPROM interface via the EExx pins.

on the secondary IDE connector. Strap information is communicated to the north bridge via VD[7].

O Primary Disk Address. PDA[2:0] are used to indicate which byte

in either the ATA command block or control block is being accessed.

O Secondary Disk Address. SDA[2:0] are used to indicate which

byte in either the ATA command block or control block is being accessed. Strap information is communicated to the north bridge via VD[6:4].

Primary Disk Data.

Secondary Disk Data.

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AC97 Audio / Modem Interface Signal Name

ACRST# ACBTCK ACSYNC ACSDO ACSDIN0

(VSUS33)ƒ ACSDIN1 (VSUS33)ƒ ACSDIN2 / GPIO20 / PCS0# ACSDIN3 /

GPIO21 / PCS1# / SLPBTN#

Pin # I/O Signal Description

T3 O T1 I T2 O U2 O U3 I

V2 I

U1 I AC97 Serial Data In 2. RxE4[6]=0,E5[1]=0, PMIO Rx4C[20]=1

V3 I AC97 Serial Data In 3. RxE4[6]=0,E5[2]=0, PMIO Rx4C[21]=1

AC97 Reset. AC97 Bit Clock. AC97 Sync. AC97 Serial Data Out. AC97 Serial Data In 0.

AC97 Serial Data In 1.

Resets, Clocks, and Power Status Signal Name Pin # I/O Signal Description

PWRGD AC5 I

PWROK# AF1 O PCIRST# R1 O

OSC AB8 I

RTCX1 AE4 I

RTCX2 AF3 O

TEST AE9 I Test. TPO AF9 O NC (see pin

list)

Power Good. Connected to the Power Good signal on the

Power Supply. Internal logic

PCI Reset. Active low reset signal for the PCI bus. The

VT8235 Version CE will assert this pin during power-up or from the control register. Oscillator. 14.31818 MHz clock signal used by the internal Timer. RTC Crystal Input: 32.768 KHz crystal or oscillator input. This input is used for the internal RTC and power-well power management logic and is powered by VBAT. RTC Crystal Output: 32.768 KHz crystal output. Internal logic powered by VBAT.

Test Pin Output. Output pin for test mode. No Connect. Do not connect.

–

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Internal Keyboard Controller

Signal Name Pin # I/O PU Signal Description

MSCK / IRQ1

MSDT / IRQ12

KBCK / KA20G

KBDT / KBRC

W1 IO / I PU

W2 IO / I PU

W3 IO / I PU

V1 IO / I PU

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KBCS# / strap Note: KBCK, KBDT, MSCK, and MSDT are powered by the VSUS33 suspend voltage plane.

Speaker Signal Name Pin # I/O PU Signal Description

SPKR / strap

AF10 O

AF8 O

MultiFunction Pin (Internal mouse controller enabled by

Rx51[1]) Rx51[2]=1 Mouse Clock. From internal mouse controller.

Rx51[2]=0 Interrupt Request 1. Interrupt input 1. MultiFunction Pin (Internal mouse controller enabled by

Rx51[1]) Rx51[2]=1 Mouse Data. From internal mouse controller. Rx51[2]=0 Interrupt Request 12. Interrupt input 12. MultiFunction Pin (Internal keyboard controller enabled by Rx51[0]) Rx51[0]=1 Keyboard Clock. From internal keyboard controller Rx51[0]=0 Gate A20. Input from external keyboard controller. MultiFunction Pin (Internal keyboard controller enabled by Rx51[0]) Rx51[0]=1 Keyboard Data. From internal keyboard controller. Rx51[0]=0 Keyboard Reset. From external keyboard controller (KBC) for CPURST# generation Keyboard Chip Select (Rx51[0]=0). To external keyboard controller chip. Strap high to enable LPC BIOS ROM.

Speaker. Strap low to enable (high to disable) CPU frequency

strapping.

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General Purpose Inputs Signal Name Pin # I/O Signal De script ion

GPI0 (VBAT) AE2 I GPI1 (VSUS33) AC2 I GPI2 / EXTSMI#

(VSUS33)

GPI3 / RING#

(VSUS33)

GPI4 / LID#

(VSUS33)

GPI5 /

BATLOW#

(VSUS33)

GPI6 / AGPBZ#

GPI7 / REQ5#

GPI12 / GPO12 /

INTE#

GPI13 / GPO13 /

INTF#

GPI14 / GPO14 /

INTG#

GPI15 / GPO15 /

INTH#

GPI16 /

INTRUDER#

(VBAT)

GPI17 /

CPUMISS

GPI18 / THRM#

/ AOLGPI

GPI20 / GPO20 /

ACSDIN2 /

PCS0#

GPI21 / GPO21 /

ACSDIN3 /

PCS1# /

SLPBTN#

GPI22 / GPO22 /

GHI#

GPI23 / GPO23 /

DPSLP#

AA1 I

Y2 I

AC1 I

V4 I

AD10 I

R3 I D4 I

E4 I

A3 I

B3 I

AE1 I

Y1 I

Y4 I

U1 I

V3 I

R22 I

P21 I

General Purpose Input 0. Status on PMIO Rx20[0] General Purpose Input 1. Status on PMIO Rx20[1] General Purpose Input 2. Status on PMIO Rx20[4]

General Purpose Input 3. Status on PMIO Rx20[8]

General Purpose Input 4. Status on PMIO Rx20[11]

General Purpose Input 5. Status on PMIO Rx20[12]

General Purpose Input 6. Status on PMIO Rx20[5] General Purpose Input 7. RxE4[2] = 0 General Purpose Input 12. RxE 4[4] = 0, 5B[1]=0

General Purpose Input 13. RxE 4[4] = 0, 5B[1]=0

General Purpose Input 14. RxE 4[4] = 0, 5B[1]=0

General Purpose Input 15. RxE 4[4] = 0, 5B[1]=0

General Purpose Input 16. Status on PMIO Rx20[6]

General Purpose Input 17. Status on PMIO Rx20[5]

General Purpose Input 18. Rx8C[3] = 0

General Purpose Input 20. RxE4[6]=1, E5[1]=0, PMIO 4C[20] = 1

General Purpose Input 21. RxE4[6]=1, E5[2]=0 PMIO 4C[21] = 1

General Purpose Input 22. RxE5[3] = 1, PMIO 4C[22] = 1 General Purpose Input 23. RxE5[3] = 1, PMIO 4C[23] = 1

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General Purpose Inputs (Continued) Signal Name Pin # I/O Signal Description

GPI26 / GPO26 /

SMBDT2

(VSUS33)

GPI27 / GPO27 /

SMBCK2

(VSUS33)

GPI28 / GPO28

GPI29 / GPO29 /

VRDSLP

Note: Register references above are Device 17 Function 0 unless indicated otherwise. Note: Default pin function is underlined in the signal name column above. Note: Input pin status for the above GPI pins 31-0 is also available on PMIO Rx4B-48[31-0] Note: See also Power Management I/O register Rx50 for input pin change status for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx52 for SCI/SMI select for GPI16-19 and 24-27 Note: See also Power Management I/O register Rx4C. General purpose input pins 20-31 are shared with OD (open drain) general

AD1 I

AC3 I

AC8 I

AB9 I

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Programmable Chip Selects Signal Name Pin # I/O Signa l Description

PCS0# / GPIO20 / ACSDIN2 PCS1# / GPIO21

/ ACSDIN3 / SLPBTN#

U1 O

V3 O

General Purpose Input 26. Rx95[2] = 1, 95[3] = 0

General Purpose Input 27. Rx95[2] = 1, 95[3] = 0

General Purpose Input 28. RxE5[3] = 1, PMIO 4C[28] = 1 General Purpose Input 29. RxE5[3] = 1, PMIO 4C[29] =

Programmable Chip Select 0. RxE4[6]=1, E5[1]=1

Programmable Chip Select 1. RxE4[6]=1, E5[2]=1

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General Purpose Outputs

Signal Name Pin # I/O Signal Description

GPO0 (VSUS33) AA3 O

GPO1 / SUSA#

(VSUS33)

GPO2 / SUSB#

(VSUS33)

GPO3 /

SUSST1#

(VSUS33)

GPO4 / SUSCLK

(VSUS33)

GPO5 /

CPUSTP#

GPO6 / PCISTP#

GPO7 / GNT5#

GPO12 / GPI12 /

INTE#

GPO13 / GPI13 /

INTF#

GPO14 / GPI14 /

INTG#

GPO15 / GPI15 /

INTH#

GPO20 / GPI20 /

ACSDIN2 /

PCS0#

GPO21 / GPI21 /

ACSDIN3 /

PCS1#

/SLPBTN#

GPO22 / GPI22 /

GHI#

GPO23 / GPI23 /

DPSLP#

GPO26 / GPI26 /

SMBDT2

(VSUS33ƒ)

GPO27 / GPI27 /

SMBCK2

(VSUS33ƒ)

AA2 O

AD3 O

Y3 O

AB3 O

AC7 O

AD6 O

R2 O D4 O

E4 O

A3 O

B3 O

U1 OD

V3 OD

R22 OD

P21 OD

AD1 OD

AC3 OD

General Purpose Output 0. General Purpose Output 1. Rx94[2] = 1

General Purpose Output 2. Rx94[3] = 1

General Purpose Output 3. Rx94[4] = 1

General Purpose Output 4. Rx95[1] = 1

General Purpose Output 5. RxE4[0] = 1

General Purpose Output 6. RxE4[1] = 1 General Purpose Output 7. RxE4[2] = 0 General Purpose Output 12. RxE4[4]=1, 5B[1]=0

General Purpose Output 13. RxE4[4]=1, 5B[1]=0

General Purpose Output 14. RxE4[4]=1, 5B[1]=0

General Purpose Output 15. RxE4[4]=1, 5B[1]=0

General Purpose Output 20. RxE4[6]=1, E5[1]=0

General Purpose Output 21. RxE4[6]=1, E5[2]=0

General Purpose Output 22. RxE5[3]=1, PMIO 4C[22]=1

General Purpose Output 23. RxE5[3]=1, PMIO 4C[23]=1

General Purpose Output 26. Rx95[2] = 1, 95[3] = 1

General Purpose Output 27. Rx95[2] = 1, 95[3] = 1

Confidential Document

General Purpose Outputs (Continued)

Signal Name Pin # I/O Signal Description

GPO28 / GPI28

GPO29 / GPI29 /

VRDSLP

Note: The output state for each of the above general purpose outputs is selectable via Power Management I/O registers Rx4C-48 Note: Default pin functions are underlined in the table above.

AC8 OD AB9 OD

Power Management and Event Detection Signal Name Pin # I/O Signal Description

PWRBTN# AD2 I

SLPBTN# /

GPIO21/ ACSDIN3 /

MiTac Secret

PCS1# RSMRST# AD4 I

EXTSMI# / GPI2

PME# W4 I

SMBALRT# AB1 I

V3 I

AA1 IOD

General Purpose Output 28. RxE5[3] = 1, PM I O 4C [ 28] = 1 General Purpose Output 29. RxE5[3] = 1, PM I O 4C [ 29] = 1

Power Button. Used by the Power Management subsystem to monitor an external

system on/off button or switch. Internal logic powered by VSUS33. Sleep Button. Used by the Power Management subsystem

to monitor an external sleepbutton or switch. RxE4[6] = 1, 80[6] = 1, E5[2] = 0 and PMIO Rx4C[21] = 1

Resume Reset. Resets the internal logic connected to the VSUS33 power plane and also resets portions of the internal RTC logic. Internal logic powered by VBAT. External System Management Interrupt. When enabled to allow it, a falling edge on this input causes an SMI# to be generated to the CPU to enter SMI mode. (10K PU to VSUS33 if not used) (3.3V only) Power Management Event. (10K PU to VSUS33 if not used) SMB Alert. When programmed to allow it (SMB I/O Rx8[3]=1), assertion generates an IRQ, SMI, or power management event. (10K PU to VSUS33 if not used)

Page 88

8965 N/B Maintenance

5.3 VT8235CE South Bridge - 9

Power Manage ment and Event Detection (Continued) Signal Name Pin # I/O Signal Description

LID# / GPI4

INTRUDER# / GPI16

THRM# / GPI18/

AOLGPI

RING# / GPI3

BATLOW# / GPI5 CPUSTP# / GPO5

PCISTP# / GPO6

SUSA# / GPO1

SUSB# / GPO2

SUSC# AF2 O

AC1 I No te book Computer Display Lid Open / Closed

AE1 I

Y4 I

Y2 I

V4 I

AC7 O

AD6 O

AA2 O

AD3 O

Monitor. Used by the Power Management subsystem to

monitor the opening and closing of the display lid of notebook computers. Can be used to detect either low-to-high or high-to-low transitions to generate an SMI#. (10K PU to VSUS33 if not used) Intrusion Indicator. The value of this bit may be read at PMIO Rx20[6] Thermal Alarm Monitor. Rx8C[3] = 1. Rising or falling edges (selectable by PMIORx2C[6]) may be detected to set status at PMIO Rx20[10]. Setting of this status bit may then be used to generate an SCI or SMI. THRM# may also be used to enable duty cycle control of stop-clock (STPCLK#) to automatically limit maximum temperature (see Device 17 Function 0 Rx8C[7-4]). Ring Indicator. May be connected to external modem circuitry to allow the system to be re-activated by a received phone call. (10K PU to VSUS33 if not used) Battery Low Indicator. (10K PU to VSUS33 if not used) (3.3V only) CPU Clock Stop (RxE4[0] = 0). Signals the system clock generator to disable the CPU clock outputs. Not connected if not used. PCI Clock Stop (RxE4[1] = 0). Signals the system clock generator to disable the PCI clock outputs. Not connected if not used. Suspend Plane A Control (Rx94[2]=0). Asserted during power management POS, STR, and STD suspend states. Used to control the primary power plane. (10K PU to VSUS33 if not used) Suspend Plane B Control (Rx94[3]=0). Asserted during power management STR and STD suspend states. Used to control the secondary power plane. (10K PU to VSUS33 if not used) Suspend Plane C Control. Asserted during power management STD suspend state. Used to control the tertiary power plane. Also connected to ATX power-on circuitry. (10K PU to VSUS33 if not used)

Confidential Document

Power Management and Event Detection (Continued) Signal Name Pin # I/O Signal Description

SUSST1# / GPO3

SUSCLK AB3 O

CPUMISS / GPI17

AOLGPI /

GPI18/ THRM#

Y3 O

Y1 I

Y4 I

MiTac Secret

Strap Pins for VT8235 Version CE Configuration Signal Name Pin # Function Description Note

Strap_AUTO

SPKR

KBCS#

SDCS1#

AE10 Auto

AF8 CPU

AF10 Internal

AF25

Reboot

Frequency

Strapping

Keyboard

Controller Eliminate External LAN EEPROM

Suspend Status 1 (Rx94[4] = 0). Typically connected to the North Bridge to provide information on host clock status. Asserted when the system may stop the host clock, such as Stop Clock or during POS, STR, or STD suspend states. Connect 10K PU to VSUS33. Suspend Clock. 32.768 KHz output clock for use by the North Bridge (e.g., KT400A, CLE266, or P4X400) for DRAM refresh purposes. Stopped during Suspend-to-Disk and Soft-Off modes. Connect 10K PU to VSUS33. CPU Missing. Used to detect the physical presence of the CPU chip in its socket. High indicates no CPU present. Connect to the CPUMISS pin of the CPU socket. The state of this pin may be read in the SMBus 2 registers. This pin may be used as CPUMISS and GPI17 at the same time. Alert On LAN. The state of this pin may be read in the SMBus 2 registers. This pinmay be used as AOLGPI, GPI18 and THRM# all at the same time.

L: Enable Auto Reboot

H: Disable Auto Rebo ot

(Default)

L: Enable CPU Frequency Strapping H: Disable CPU Frequency Strapping (Default) L: Disable internal KBC H: Enable internal KBC (Default) L: Enable. Use external EEPROM (Default) H: Disable. Do not use external EEPROM

Page 89

8965 N/B Maintenance

5.3 VT8235CE South Bridge - 10

Power and Ground Signal Name Pin # I/O Signal Description

VSUS33 AA4,

AB4-6

VSUS25 T4, U4 P VSUSUSB C24 P VBAT AF4 P

VLVREF H22 P

VLCOMP J22 AI V-Link Compensation. VCCVK (see pin

list)

MIIVCC D9,

E9-11

MIIVCC25 D12.

E12

LANVCC E7 P

LANGND E6 P USBVCC (see pin

list)

USBGND (see pin

list)

VCCUPLL A23,

B23

GNDUPLL C23,

D23

PLLVCC T22 P

PLLGND U22 P

Suspend Power. 3.3V ±5%. Always available unless the

mechanical switch of the power supply is turned off. If the ihsoft-offlÉD state is not implemented, then this pin can be connected to VCC33. Signals powered by or referenced to this plane are: PWRGD, RSMRST#, PWRBTN#, SMBCK1/2, SMBDT1/2, GPO0, SUSA# / GPO1, SUSB# / GPO2, SUSC#, SUSST1# / GPO3, SUSCLK / GPO4, GPI1, GPI2 / EXTSMI#, GPI3 / RING#, GPI4 / LID, GPI5 / BATLOW#, GPI6 / PME#, SMBALRT#

Suspend Power. 2.5V ±5%. USB Suspend Power. 2.5V ±5%. RTC Battery. Battery input for internal RTC (RTCX1,

RTCX2) V-Link Voltage Reference. 0.9V ±5% for 4x transfers and

0.625V ±5% for 8x transfers.

V-Link Compensation Circuit Voltage. 2.5V ±5%

LAN MII Power. 3.3V ±5%.Power for LAN Media

Independent Interface (interface to external PHY). Connect to VCC33 through a ferrite bead.

LAN MII Suspend Power. 2.5V ±5%.

LAN Power. 2.5V ±5%. Power for LAN. Connect to VCC through a ferrite bead. LAN Ground. Connect to GND through a ferrite bead.

USB 2.0 Differential Output Power. 3.3V ±5%. Power

for USB differential outputs (USBP0+, P0Œ, P1+, P1Œ, P2+, P2Œ, P3+, P3Œ, P4+, P4Œ, P5+, P5Œ). Connect to VSUS33 through a ferrite bead.

USB 2.0 Differential Output Ground. Connect to GND

through a ferrite bead. USB 2.0 PLL Analog Voltage. 2.5V ±5%. Connect to

VCC through a ferrite bead. USB 2.0 PLL Analog Ground. Connect to GND through a

ferrite bead. PLL Analog Power. 2.5V ±5%. Connect to VCC through a ferrite bead. PLL Analog Ground. Connect to GND through a ferrite bead.

Confidential Document

Power and Ground (Continued) Signal Name Pin # I/O Signal Description

VCC33 (see pin

VCC (see pin

GND (see pin

list)

Strap Pins for North Bridge Config ura tion Signal Name Pin # Function Description Note

SDCS3#

SDA2

MiTac Secret

SDA1

SDA0

Strap_VD3

Strap_VD2

Strap_VD1

Strap_VD0

Note: Internal Pullups are present on pins KBCK, KBDT, MSCK, MSDT, SERIRQ, LAD[3:0] Internal Pulldowns are present on all LAN pins

AF26

AE24

AC22

AF24

AC6

AD5

AE5

AF5

I/O Power. 3.3V ±5%

P P Core Power. 2.5V ±5%. This supply is turned on

only when the mechanical switch on

supply is turned on and the PWRON signal is conditioned high. Ground. Connect to primary motherboard ground plane.

NB Configuratio n NB Configuratio n NB Configuratio n NB Configuratio n NB Configuratio n NB Configuratio n NB Configuratio n NB Configuratio n

SDCS3# signal state is reflected on signal pinVD[7] during power up for North Bridgeconfiguration. SDA2 signal state is reflected on signal pinVD[6] during power up for North Bridgeconfiguration. SDA1 signal state is reflected on signal pinVD[5] during power up for North Bridgeconfiguration. SDA0 signal states is reflected on signal pinsVD[4] during power up for North Bridgeconfiguration. Strap_VD3 signal state is reflected on signal pinVD[3] during power up for North Bridgeconfiguration. Strap_VD2 signal state is reflected on signal pinVD[2] during power up for North Bridgeconfiguration. Strap_VD1 signal state is reflected on signal pin, VD[1] during power up for North Bridge configuration. Strap_VD0 signal state is reflected on signalpin, VD[0] during power up for North Bridgeconfiguration.

Check the NorthBridge DS fordetails Check the NorthBridge DS fordetails Check the NorthBridge DS fordetails Check the NorthBridge DS fordetails Check the NorthBridge DS fordetails Check the NorthBridge DS fordetails Check the North Bridge DS for details

Check the NorthBridge DS fordetails

the power

Page 90

8965 N/B Maintenance

6. System Block Diagram

U713

Clock Generator

ICS950902

U704

Intel CPU

Pentium-M/Celeron-M

Front-Side Bus

200 pin DDR SO-DIMM Socket * 2

J717

Mini-PCI socket

PCI Bus

CRT LCD Panel

USB2.0

5 Ports (1 Port internal option)

Primary IDE (HDD)

Confidential Document

Fan

Fan Controller

U709

North Bridge

VIA PN800

V-Link Interface

MiTac Secret

U711

South Bridge

VT 8235 CE

Primary IDE

LPC

U707

ADT7460

Touch Pad

Keyboard

U17

W83L950D

KBC

MII

AC97

LVDS Encoder

VT6103L

U16

System

BIOS

U703

VT1634AL

U15

LAN

M.D.C

Audio Codec

U702

ALC655

Amplifier TPA0212

RJ-45 Jack

RJ-11 Jack

MIC-IN

Headphone

Speaker

Page 91

8965 N/B Maintenance

7. Maintenance Diagnostics

7.1 Introduction

Each time the computer is turned on, the system bios runs a series of internal checks on the hardware. This power- on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer.

If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available.

The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test failed, the user can determine where the problem occurred by reading the last value written to port 378H by the Mini PCI debug

board.

MiTac Secret

Confidential Document

Page 92

8965 N/B Maintenance

7.2 Error Codes (1)

Following is a list of error codes in sequent display on the MINI PCI debug board.

POST Routine DescriptionCode

Signals that Reset occurred10h

Turn off FAST A20 for POST11h

Signal power on reset12h

Initialize the chipset13h

Search for ISA Bus VGA adapter14h

Reset counter / Timer 115h

User register config through CMOS16h

Size memory17h

Dispatch to RAM test18h

Check sum the ROM19h

Reset PIC’s1Ah

Initialize video adapter1Bh

MiTac Secret

POST Routine DescriptionCode

Test keyboard20h

Test keyboard controller21h

Check if CMOS RAM valid22h

Test battery fail & CMOS X-SUM23h

Test DMA controller24h

Initialize 8237A controller25h

Initialize int vectors26h

RAM quick sizing27h

Protected mode entered safely28h

RAM test completed29h

Protected mode exit successful2Ah

Setup shadow2Bh

Confidential Document

Initialize video1Ch

Going to initialize video2Ch

Initialize color adapter1Dh

Initialize monochrome adapter1Eh

Test 8237A page registers1Fh

Search for monochrome adapter2Dh

Search for color adapter2Eh

Sign-on messages displayed2Fh

Page 93

8965 N/B Maintenance

7.2 Error Codes (2)

Following is a list of error codes in sequent display on the MINI PCI debug board.

POST Routine DescriptionCode

OEM initialization of keyboard controller30h

Test if keyboard Present31h

Test keyboard Interrupt32h

Test keyboard command byte33h

Test, blank and count all RAM34h

Protected mode entered safely(2)35h

RAM test complete36h

Protected mode exit successful37h

Update keyboard controller output port38h

Setup cache controller39h

Test if 18.2Hz periodic working3Ah

Test for RTC ticking3Bh

MiTac Secret

POST Routine DescriptionCode

Configure the COMM and LPT ports40h

Initialize the floppies41h

Initialize the hard disk42h

Initialize option ROMs43h

OEM’s initialization of power management44h

Update NUMLOCK status45h

Test for coprocessor installed46h

OEM functions before boot47h

Dispatch to operate system boot48h

Jump into bootstrap code49h

Confidential Document

Initialize the hardware vectors3Ch

Search for and initialize the mouse3Dh

Update NUMLOCK status3Eh

OEM initialization of COM and LPT ports3Fh

Page 94

8965 N/B Maintenance

7.3 Debug Tool

7.3.1 Diagnostic Tool for Mini PCI Slot :

MiTac Secret

P/N:411906900001 Description: PWA-MPDOG;MINI PCI DOGKELLER CARD

Confidential Document

Note: Order it from MIC/TSSC

Page 95

8. Trouble Shooting

8965 N/B Maintenance

8.1 No Power (*1)

8.2 Battery Can not Be Charged

8.3 No Display (*2)

8.4 LCD No Display or Picture Abnormal

MiTac Secret

8.5 External Monitor No Display or Color Abnormal

8.6 Memory Test Error

Confidential Document

8.8 Hard Disk Drive Test Error

8.9 USB Port Test Error

8.10 Mini-PCI Socket Test Error

8.11 Audio Test Error

8.12 LAN Test Error

8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error

Page 96

8965 N/B Maintenance

*1: No Power Definition

Base on ACPI Spec. We define the no power as while we press the power button, the system can’t leave S5 status or none the PG signal send out from power supply.

Judge condition:

 Check whether there are any voltage feedback control to turn off the power.  Check whether no CPU power will cause system can’t leave S5 status.

If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending out the PG signal. If yes, we should add the effected analysis into no power chapter.

*2: No Display Definition

Base on the digital IC three basic working conditions: working power, reset, Clock. We define the no display as while system leave S5 status but can’t get into S0 status.

Judge condition:

 Check which power will cause no display  Check which reset signal will cause no display  Check which Clock signal will cause no display

Base on these three conditions to analyze the schematic and edit the no display chapter.

Confidential Document

MiTac Secret

Keyword:

 S5: Soft Off  S0: Working

For detail please refer the ACPI specification

Page 97

8.1 No Power (1)

When power button is pressed, nothing happens, power indicator does not light up.

8965 N/B Maintenance

PJ701

PF702,PL711 PL712,PD715 PR744

P31

+PWR_VDDIN

VDD3_AVREF

Main Voltage Map

Charge

PL704,PQ706 PL706,PL705,PD704

PQ712

PD711

P31

F2,U12

P24

P31

Q23,D16

NOTE :

P28

: Page 28 on M/B Board circuit diagram.

PF1

: Through by part PF1.

P24

VDD3

PD713

PD712

Discharge

L49,Q33

P30

BATT

PQ702 PQ703,PR52

PF703,PL716,PL717,PU714, PU711 PU713,PU712,PD702,PL701,PR703

PU707,PU710

PL713,PU4

PR755,PL715

P28

+VCC_CORE

P25

+5VS_P

R83,C510

JS708,JS710 JS712,JS714

Discharge

P31

DVMAINADINPPOWER IN

P24

VDD3S

D22

PU708,PL714,PR754

MiTac Secret

P15

PL3,PU2

+VCC_RTC

PU8,PL1 PR15,PC75

PU9,PU10 PL2,PR33

P26

+1.5V_P

P26

+2.5VS_DDR_P

+3VS_P

JS7,JS10,JS11

JS702

P25

JS704,JS706

P23

L53,L54,L56

+1.5V

JS3,JS8,JS9

Confidential Document

PU11

PL708,PU704 PU703,PL707

+1.05V_P

JS715,JS717

P27

JS719

P23

+VCCP

L47

P21

+KBC_CPUCORE

P23

U9,L44,L45

+5VS

P23

+3VS

VCCPLL[1..3]

P23

+2.5VS_DDR

P27

+1.25V_DDR_P

+VCCQ

L73

L66

L46,U8 L43

L63

L81

+5V

P24

P13

+3VS_USB

P14

+3VSUS

P24

+3V

P15

+3VS_MII

P17

+3VS_LAN

L59,U14

R342,R343

R344,R345

Q43,Q710 Q718,R928

L72

R273

L65

JS4,JS5,JS6

+1.25V_DDR

+5V_HDD

P19

AMPVDD

TP_VDD

L58

L55,L57

L50,L51 L52,L75

U10

P16

L32

P20

P22

L726

L702

F3,L69 R261

+1.5VS

+DDRVREF_1

P10

+DDRVREF_2

P24

+2.5V

P15

+2.5VS_MII

MVREF_NB

P14

+2.5VSUS

P23

P19

AVDD

VCC33GFX

VCCDAC[0,1]

AVDD[1..4]

P24

+1.8V

R731

R743

R34

L87

LVDSVCC

PLLVCC

DVDD

P11

+2.5V_GEN

Page 98

8.1 No Power (2)

When power button is pressed, nothing happens, power indicator does not light up.

No Power

8965 N/B Maintenance

Is the

notebook connected

to power (either AC adaptor

or battery)?

Yes

Try another known good

battery or AC adapter.

Power

OK?

Is the

M/B and charger

BD connected

properly?

Yes

Try another known

good charger BD.

Yes

Replace the faulty AC adaptor or Battery.

Connect AC adaptor or battery.

Confidential Document

Power

OK?

Replace the faulty Charger BD.

Yes

Board-level

Troubleshooting

Where from

power source problem

(first use AC to

power it)?

MiTac Secret

Replace

Motherboard

Battery

Power

Check following parts and signals:

Parts: Signals:

PJ701 PF702 PQ11 PQ712 PD711 PD712 PD713 PL711 PL712

Check following parts and signals:

Parts: Signals:

J705 PF701 PL703 PL702 PQ702 PQ703 PQ2 PR51 PR52

ADINP DVMAIN +PWR_VDDIN

BATT BATT_T BATT_V BATT_C BATT_D

Page 99

8.1 No Power (3)

When power button is pressed, nothing happens, power indicator does not light up.

PJ701

P31

PF702

TR/SFT-10A

120Z/100M

PC55

0.01U

PL711

PL712

PC56

8965 N/B Maintenance

+PWR_VDDIN

PD711

BAV70LT1

JO48

PR744

.01

PC57

0.01U

PD715

RLZ24D

PR34 470K

PQ712

AO4407

3 2 1

ADINP

8 7 6 5

PC51

0.01U

PC52

0.01U

PC53

1000P

PC54

1000P

PR747

4.7K

PR745

4.7K

PD712

BAV70LT1

PD713

SM840B

PC49

0.01U

DVMAIN

PC50

0.01U

JO49

SPARKGAP_6

J705

P29

PF701

TR/SFT-10A

1,2

Battery Connector

JO50

SPARKGAP_6

PC703

0.01U

PQ11

2N7002

PR35 100K

PJO1

PR36

BATT

PC58

0.01U

1,2

PR37

PC3

1000P

PC59

PC2

0.01U

I_LIMIT

R82

D702

RLS4148

ADEN#

P31

PU3

MiTac Secret

MAX4173FEUT-T

Confidential Document

PL702

120Z/100M

PL703

120Z/100M

PC1

0.01U

PR51 33K

LEARNING#

H8_I_LIMIT

H8_ADEN#

PR52 100K

PQ2

2N7002

DVMAIN

PQ703

AO4407

P21

U17

KBC

W83L950D

PQ702

231

678

AO4407

Page 100

8965 N/B Maintenance

8.2 Battery Can not Be Charged (1)

When the battery is installed but the battery status indicate LED display abnormal.

Battery Can not Be Charged

Is the

notebook connected

to power (AC adaptor)?

Yes

Connect AC adaptor.

Motherboard

Replace

Board-level

Troubleshooting

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement.2

1. Make sure that the battery is good.

2. Make sure that the battery is installed properly.

Battery charge

OK?

Yes

MiTac Secret

Confidential Document

Correct it.

Parts Signal

PU3 PL704 PQ706 PL706 PR712 PQ709 PQ710 PQ3 PQ707 PD707 PD706

PD704 RP702 PR818 PR713 PR821 PD1 PD2 PF701 PL702 PL703

ADINP VDD3_AVREF I_LIMIT I_CRT BATT BATT_V BATT_T BATT_C BATT_D