miscellaneous mitac 8965 Service Manual

SERVICE MANUAL FOR

8965

89658965

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89658965

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BY: Sinty Zhang

Repair Technology Research Department /EDVD

Apr.2005 / R01

Contents

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1. Hardware Engineering Specification ……………………………………………………………… ………

1.1 Introduction ………………………………………………………………………………………………………………..

1.2 System Hardware Parts …………………………………………………………………………………………………...

1.3 Other Functions ……………………………………………………………………………………………………………

1.4 Power Management ……………………………………………………………………………………………………….

1.5 Appendix 1 : VIA VT8235CE GPI/O Pins Definitions ……………………………………………………………….....

1.6 Appendix 2 : W83L950D KBC Pins Definitions ………………………………………………………………………...

2. System View and Disassembly ……… ……………………………………………………………………..

2.1 System View ……………………………………………………………………………………………………………….

2.2 Tools Introduction …………………………………………………………………………………………………………

2.3 System Disassembly ……………………………………………………………………………………………………….

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3. Definition & Location of Connectors / Switches …………………………………………………………..

3.1 Mother Board ……………………………………………………………………………………………………………...

3.2 Modem Board ……………………………………………………………………………………………………………...

4. Definition & Location of Major Comp onents ……………………………………………………………..

4.1 Mother Board ……………………………………………………………………………………………………………...

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5. Pin Description of Major Componen ts ….…………………………………………………………………

5.1 Intel Pentium M Processor CPU …………………………………………………………………………………………

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5.2 PN800 North Bridge ………………………………………………………………………………………………………

5.3 VT8235CE South Bridge ….……………………………………………………………………………………………...

6. System Block Diagram ……………………………………………………………………………………..

7. Maintenance Diagnostics …………… ……………………………………………………………………..

7.1 Introduction ……………………………………………………………………………………………………………….

7.2 Error Codes ……………………………………………………………………………………………………………….

7.3 Debug Tool …………………………………………………………………………………………………………………

8. Trouble Shooting ……………………………………………………………………………………………

8.1 No Power …………………………………………………………………………………………………………………..

8.2 Battery Can not Be Charged …………………………………………………………………………………..…………

8.3 No Display …………………………………………………………………………………………………………………

8.4 LCD No Display or Picture Abnormal …………………………………………………………………………………..

8.5 External Monitor No Display or Color Abnormal ………………………………………………………………………

8.6 Memory Test Error ……………………………………………………………………………………………………….

8.7 Keyboard (K/B) Touch-Pad (T/P) Test Error …………………………………………………………………………..

8.8 Hard Disk Drive Test Error ………………………………………………………………………………………………

8.9 USB Port Test Error ……………………………………………………………………………………………………...

8.10 Mini-PCI Socket Test Error …………………………………………………………………………………………...

8.11 Audio Test Error …………………………………………………………………………………………………………

8.12 LAN Test Error ………….……………………………………………………………………………………………….

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9. Spare Parts List ……………………………………………………………………………………………..

10. System Exploded Views …………… ………………………………………………………………………

11. Circuit Diagram ……………………………………………………………………………………………

12. Reference Material ……………………………………… ………………………………………………..

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1. Hardware Engineering Specification

1.1 Introduction

1.1.1 General Description

This document describes the brief introduction for MITAC 8965 portable notebook computer system.

1.1.2 System Overview

The MITAC 8965 model is designed for Intel Banias processor with 400MHz FSB with Micro-FCPGA package. It can support Banias 1.5G ~ 1.9GHz.

This system is based on PCI architecture and is fully compatible with IBM PC/AT specification, which has standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 2.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 key at system start up or warm reset. System also provides icon LEDs to display system status, such as Wireless Lan indicator, Power indicator, Battery status indicator, HDD, Num Lock, Caps Lock, Scroll Lock. It also equipped with LAN, 4 USB ports, and audio line out, external microphone function.

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The memory subsystem supports two expansion DDR SDRAM slot with unbuffered PC3200 DDR400 SDRAM.

The VIA PN800 Mobile North Bridge integrates a high performance CPU interface for Intel Pentium 4 / Pentium-M processor, a full featured AGP port controller, integrated Graphics with 2D/ 3D/ Video Controllers, a advanced high- performance DDR400 SDRAM controller, and high bandwidth Ultra V-Link host controller connecting with VIA

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VT8235CE South Bridge.

The VIA VT8235CE integrates Universal Serial Bus 2.0 Host Controllers Interface (UHCI), the Audio Controller with AC97 interface, the Ethernet includes a 32-bit PCI controller, the IDE Master/Slave controllers, and Inter- operable with VIA Host-to-V-Link Host Controller.

The VIA VT6103L is a Fast Ethernet 10 / 100 1-port PHY / Transceiver with MII interface, and meet all applicable IEEE 802.3, 10Base-T and 100Base-Tx standards.

The W83L950D is a high performance microcontroller on-chip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication interface, optional I²C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high performance systems can be implemented easily.

A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME, Windows 2000 and Windows XP to take full advantage of the hardware capabilities. Features such as bus mastering

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IDE, Plug and Play, Advanced Power Management (APM) with application restart, software-controlled power shutdown.

Following chapters will have more detail description for each individual sub-systems and functions.

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1.2 System Hardware Parts

CPU

Core logic VGA Control

System BIOS Memory

Video Memory Clock Generator

LVDS LAN PHY

Audio System

Mobile Pentium-M Processor 1.3G ~ 1.9GHz Thermal spec 35W TDP

VIA PN800 + VIA VT8235CE chipset

North Bridge Integrated

SST49LF040

DDR RAM : DDR333 Nanya NT512D64S8HBAFM-6K DDR400 Micron, MT8VDDT3264HD

Share memory

ICS 950902

VIA VT1634AL

VIA VT6103L

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AC97 CODEC: Advance Logic, Inc, ALC655 Power Amplifier: TI TPA0212

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1.2.1 Intel Banias Processors in Micro-FCPGA Package

Intel Banias Processors with 593 pins Micro-FCBGA package.

It has the Intel NetBurst micro-architecture which features include hyper-pipelined technology, a rapid execution engine, a 400MHz system, an execution trace cache, advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2).

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.

Use Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock.

Support Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes.

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1.2.2 Clock Generator

The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with PC133 or DDR memory. The ICS950902 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.

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Recommended Application

 VIA P4X/P4M/KT/KN266/333 style chipsets

Output Features

 1 - Pair of differential CPU clocks @ 3.3V (CK408)/ 1 - Pair of differential open drain CPU clocks (K7)

 1 - Pair of differential push pull CPU_CS clocks @ 2.5V

 3 - AGP @ 3.3V

 7 - PCI @ 3.3V (1 - Free running)

 1 - 48MHz @ 3.3V fixed

 1 - 24_48MHz @ 3.3V (Default 48MHz I2C select only)

 2 - REF @ 3.3V, 14.318MHz

 12 - SDRAM (6 pair - DDR) selectable

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Features/Benefits

 Programmable output frequency

 Programmable output divider ratios

 Programmable output rise/fall time

 Programmable output skew

 Programmable spread percentage for EMI control

 DDR output buffer supports up to 200MHz

 Watchdog timer technology to reset system if system malfunctions

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 Programmable watch dog safe frequency

 Support I2C Index read/write and block read/write operations

 Uses external 14.318MHz crystal

1.2.3 PN800 Mobile North Bridge

The PN800 is a high performance, cost-effective and energy efficient UMA North Bridge with integrated UniChrome Pro graphics / video controllers used for the implementation of mobile personal computer systems based on 800 / 533 / 400 MHz FSB Intel Pentium 4 and Pentium M super-scalar processors. The complete mobile chipset consists of the PN800 North Bridge (829 pin HSBGA) and the VT8235-CE V-Link South Bridge (539-pin BGA). The PN800 integrates VIA’s PT800 system controller with high-performance UniChrome Pro 3D/2D graphics accelerator plus flat panel, DVI monitor and TV out interfaces. The PN800 provides superior performance between the CPU, DRAM, V-Link bus and internal AGP 8x graphics controller bus with pipelined, burst, and concurrent operation. The VT8235-CE is a highly integrated peripheral controller which includes V-Link-to-PCI /

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V-Link-to-LPC controllers, Ultra DMA IDE controller,USB2.0 host controller, 10/100Mb networking MAC, AC97, and system power management controllers.

Host CPU Interface

The PN800 supports 800 / 533 / 400 MHz FSB Intel Pentium 4 and Pentium M super-scalar processors. It implements a twelve level In-Order-Queue and supports Intel Hyper-Threading Technology to maximize system performance for multi-threaded software applications. DBI and Pentium M bus protocol, as well as Intel SpeedStep Technology, are supported which effectively reduce overall system power consumption.

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AGP Interface

The PN800 AGP controller is AGP 3.0 compliant with up to 2.1 GB / second data transfer rate capability. It supports asynchronous AGP and CPU interfaces for flexible system configuration. Deep read (1024 byte) and write (512 byte) FIFOs are integrated for optimal bus utilization and minimum data transfer latency.

Memory Controller

The PN800 SDRAM Controller supports two sets of 64-bit memory data, address and control signals to minimize signal loading and up to 4 double-sided DDR400 / 333 / 266 DIMMs for 8 GB maximum physical memory. The DDR DRAM interface allows zero wait-state data transfer bursting between the DRAM and the memory controller’s data buffers. The different banks of DRAM can be composed of an arbitrary mixture of 64 / 128 / 256 / 512 / 1024Mb DRAMs in x8 and x16 configurations. The DRAM controller can run either synchronous or pseudo- synchronous with the host CPU bus. The PN800 North Bridge is pin compatible with the PN880 North Bridge which connects to the memory modules in exactly the same manner while supporting true 128-bit operation

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(simultaneous memory access on both sets of 64-bit memory data / address / control signals).

Ultra V-Link

The PN800 North Bridge interfaces to the South Bridge through a high speed (up to 1 GB/sec) 8x, 66 MHz Data Transfer interconnect bus called “Ultra V-Link”. Deep pre-fetch and post-write buffers are included to allow for concurrent CPU and Vlink operation. The combined PN800 North Bridge and VT8235-CE South Bridge system supports enhanced PCI bus commands such as “Memory-Read-Line”, “Memory-Read-Multiple” and “Memory- Write-Invalid” commands to minimize snoop overhead. In addition, advanced features are supported such as CPU write-back forward to PCI master, and CPU write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also implemented for

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further improvement of overall system performance.

System Power Management

For sophisticated power management, the PN800 supports dynamic CKE control to minimize DDR SDRAM power consumption during normal system state (S0). A separate suspend power plane is implemented for the memory control logic for Suspend-to-DRAM state. Enhanced Intel SpeedStep™ Technology enables minimization of CPU power consumption while sustaining processing power. The PN800 graphics accelerator implements dynamic clock gating for inactive functions to achieve maximum power savings. The system can also be switched to standby or suspend states to further reduce power consumption when idle.Automatic panel power sequencing and VESA DPMS (Display Power Management Signaling) CRT power-down are supported.Coupled with the VT8235-CE South Bridge chip, a complete power conscious PC main board can be implemented with no external glue logic.

3D Graphics Engine

Featuring an integrated 128-bit 3D graphics engine, the PN800 North Bridge utilizes a highly pipelined architecture that provides high performance along with superior image quality. Several new features enhance the 3D architecture, including two pixel rendering pipes, single-pass multitexturing, bump and cubic mapping, texture compression, edge anti-aliasing, vertex fog and fog table, hardware back-face culling, specular lighting, anisotropic filtering and an 8-bit stencil buffer. The chip also offers the industry’s only simultaneous usage of single-pass multitexturing and single-cycle trilinear filtering – enabling stunning image quality without performance loss. Image quality is further enhanced with true 32-bit color rendering throughout the 3D pipeline to produce more vivid and realistic images. The advanced triangle setup engine provides industry leading 3D performance for a realistic user experience in games and other interactive 3D applications. The 3D engine is optimized for AGP texturing from system memory.

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128-bit 2D Graphics Engine

The PN800 North Bridge's advanced 128-bit 2D graphics engine delivers high-speed 2D acceleration for productivity applications. The enhanced 2D architecture with direct access frame buffer capability optimizes UMA performance and provides acceleration of all color depths.

MPEG Playback

The PN800 North Bridge provides the ideal architecture for high quality MPEG-2 based video applications. For MPEG video playback, the integrated video engine offloads the CPU by performing planar-to-packed format conversion and motion video compensation tasks, while its enhanced scaling algorithm delivers incredible full-screen video playback.

Video Capture

The PN800 North Bridge implements an optional Video Capture Port which supports various video capture standards, including ITU-R BT656, VIP 1.1 and VIP 2.0 and is compliant with the most common video capture formats: 16 / 32- bit RGB and YUV422. With the integrated video capture feature, the PN800 can provide high performance video effects for video capturing and playback.

LCD, DVI Monitor and TV Output Display Support

The PN800 provides three “Digital Video Port” interfaces: FPDP, GDVP1 and DVP0. The Flat Panel Display Port (FPDP) implements a 24-bit / dual 12-bit interface which is designed to drive a Flat Panel Display via an external LVDS transmitter chip (such as the VIA VT1631, NSC DS90C387R or Chrontel CH7017). The PN800 can be connected to the external LVDS transmitter chip in either 24-bit or dual-12-bit modes. A wide variety of LCD panels are supported including VGA, SVGA, XGA, SXGA+ and up to UXGA-resolution TFT color panels, in either SDR (1

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pixel / clock) or DDR (2 pixels / clock) modes. UXGA and higher resolutions require dual-edge data transfer (DDR) mode which is supported by the VIA VT1631 LVDS transmitter chip Digital Video Port 0 (DVP0) is normally used for interfacing to a TV encoder (such as the VIA VT1622A or VT1622AM using 3.3V signal levels), however if DVP0 is used for video capture, Digital Video Port 1 (GDVP1) may be configured for support of an external TV encoder (VIA VT1623 or VT1623M using low-voltage 1.5V signal levels). If GDVP1 is not being used for TV out, it can optionally be used to drive a DVI monitor via an external TMDS transmitter chip (such as the VIA VT1632) The flexible display configurations of the PN800 allow support of a flat panel (LVDS interface) or flat panel monitor (TMDS / DVI interface), TV display and CRT display at the same time. Internally the PN800 North Bridge provides two separate display engines, so if two display devices are connected, each can display completely different information at different resolutions, pixel depths and refresh rates. If more than two display devices are connected, the additional displays must have the same resolution, pixel depth and refresh rate as one of the first two. The maximum display resolutions supported for one display device are listed in the table below. If more than one display is implemented (i.e., if both display engines are functioning at the same time), then available memory bandwidth may limit the display resolutions supported on one or both displays. This will be dependent on many factors including primarily clock rates and memory speeds (contact VIA for additional information).

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1.2.4 VT8235CE Highly Integrated South Bridge

The VT8235 Version CE South Bridge is a high integration, high performance, power-efficient and high compatibility device that supports Intel and non-Intel based processor to V-Link bus bridge functionality to make a complete Microsoft PC2001-compliant PCI/LPC system. The VT8235 Version CE includes standard intelligent peripheral controllers. a) IEEE 802.3 compliant 10 / 100 Mbps PCI bus master Ethernet MAC with standard MII interface to external

PHY ceiver.

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b) Master mode enhanced IDE controller with dual channel DMA engine and interlaced dual channel

commands. Dedicated FIFO coupled with scatter and gather master mode operation allows high performance transfers between PCI and IDE devices. In addition to standard PIO and DMA mode operation, the VT8235 Version CE also supports the Ultra DMA-133, 100, 66 and 33 standards to allow reliable data transfer at rates up to 133 MB/sec. The IDE controller is SFF-8038i v1.0 and Microsoft Windows-family compliant.

c) Universal Serial Bus controller that is USB v2.0 / 1.1 and Universal HCI v2.0 / 1.1 compliant. The VT8235

Version CE includes three root hubs with six function ports with integrated physical layer transceivers. The USB controller allows hot plug and play and isochronous peripherals to be inserted into the system with universal driver support. The controller also implements legacy keyboard and mouse support so that legacy software can run transparently in a non-USB-aware operating system environment.

d) Keyboard controller with PS2 mouse support.

e) Real Time Clock with 256 byte extended CMOS. In addition to the standard ISA RTC functionality, the

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integrated RTC also includes the date alarm, century field and other enhancements for compatibility with the ACPI standard.

f) Notebook-class power management functionality compliant with ACPI and legacy APM requirements.

Multiple sleep states (power-on suspend, suspend-to-DRAM and suspend-to-Disk) are supported with hardware automatic wake-up. Additional functionality includes event monitoring, CPU clock throttling and stop (Intel processor protocol), PCI bus clock stop control, modular power, clock and leakage control, hardware-based and software-based event handling, general purpose I/O, chip select and external SMI.

g) Full System Management Bus (SMBus) interface.

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h) Integrated bus-mastering dual full-duplex direct-sound AC97-link-compatible sound system.

I) Plug and Play controller that allows complete steerability of all PCI interrupts and internal interrupts / DMA

channels to any interrupt channel. One additional steerable interrupt channel is provided to allow plug and play and reconfigurability of onboard peripherals for Windows family compliance.

The VT8235 Version CE also enhances the functionality of the standard ISA peripherals. The integrated interrupt controller supports both edge and level triggered interrupts channel by channel. The integrated DMA controller supports type F DMA in addition to standard ISA DMA modes. Compliant with the PCI-2.2 specification, the VT8235 Version CE supports delayed transactions and remote power management so that slower ISA peripherals do not block the traffic of the PCI bus. Special circuitry is built in to allow concurrent operation without causing dead lock even in a PCI-to-PCI bridge environment. The chip also includes eight levels (double words) of line buffers from the PCI bus to the ISA bus to further enhance overall system performance.

1.2.5 AC’97 Audio System: Advance Logic, Inc, ALC655

The ALC655 is a 16-bit, full duplex AC'97 2.3 compatible six channels audio CODEC designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC655 incorporates proprietary converter technology to meetperformance requirements on PC99/2001 systems. The ALC655 CODEC provides three pairs of stereo outputs with 5-Bitvolume controls, a mono output and multiple stereo and mono inputs, along with flexible mixing, gain and mute functions toprovide a complete integrated audio solution for PCs. The digital interface circuitry of the ALC655 CODEC operates from a 3.3V power supply for use in notebook and PC applications. The ALC655 integrates 50mW/20ohm headset audio amplifiers at Front-Out and Surr-Out, built-in 14.318M 24.576MHz PLL and PCBEEP generator, those can save BOM costs. The ALC655 also supports the S/PDIF input and output function, which can offer easy connection of PCs to consumer electronic products, such as AC3 decoder/speaker and mini disk

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devices. ALC655 supports host/soft audio from Intel ICHx chipsets as well as audio controller based VIA/SIS/ALI/AMD/nVIDIA/ATI chipset. Bundled Windows series drivers (WinXP/ME/2000/98/NT), EAX/Direct Sound 3D/ I3DL2/ A3D compatible sound effect utilities (supporting Karaoke, 26-kind of environment sound emulation,10-band equalizer), HRTF 3D positional audio and Sensaura™ 3D (optional) provide an excellent entertainment package and game experience for PC users. Besides, ALC655 includes Realtek’s impedance sensing techniques that makes device load on outputs and inputs can be detected.

 Meets performance requirements for audio on PC99/2001 systems

 Meets Microsoft WHQL/WLP 2.0 audio requirements

 16-bit Stereo full-duplex CODEC with 48KHz sampling rate

 Compliant with AC’97 2.3 specifications

- 14.318MHz- 24.576MHz PLL to save crystal

- 12.288MHz BITCLK input can be consumed

- Integrated PCBEEP generator to save buzzer

- Interrupt capability

 Three analog line-level stereo inputs with 5-bit volume control: LINE_IN, CD, AUX

 High quality differential CD input

 Two analog line-level mono input: PCBEEP, PHONE-IN

 Two software selectable MIC inputs applications (software selectable)

 Boost preamplifier for MIC input

 50mW/20 amplifier

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 External Amplifier Power Down (EAPD) capability

 Power management and enhanced power saving features

 Stereo MIC record for AEC/BF application

 Supports Power Off CD function

 Adjustable VREFOUT control Supports double sampling rate (96KHz) of DVD audio playback

 Support 48KHz of S/PDIF output is compliant with AC’97 rev2.3 specification

 Power support: Digital: 3.3V; Analog: 3.3V/5V

1.2.6 System Flash Memory (BIOS)

 Firmware Hub for Intel® 810, 810E, 815, 815E,815EP, 820, 840, 850 Chipsets

 Flexible Erase Capability

- Uniform 4 KByte Sectors

- Uniform 16 KByte overlay blocks for SST49LF002A

- Uniform 64 KByte overlay blocks for SST49LF004A

- Top boot block protection

- 16 KByte for SST49LF002A

- 64 KByte for SST49LF004A

- Chip-Erase for PP Mode

 Single 3.0-3.6V Read and Write Operations

 Superior Reliability

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 Firmware Hub Hardware Interface Mode

- 5-signal communication interface supporting byte Read and Write

- 33 MHz clock frequency operation

- WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

- Block Locking Register for all blocks

- Standard SDP Command Set

- Data# Polling and Toggle Bit for End-of-Write detection

- 5 GPI pins for system design flexibility

- 4 ID pins for multi-chip selection

1.2.7 Memory System

1.2.7.1 64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs

 JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM)

 Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components

 64MB (8 Meg x 64 [H]); 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg

x 64 [HD])

 VDD= VDDQ= +2.5V ±0.2V

 VDDSPD = +2.2V to +5.5V

 2.5V I/O (SSTL_2 compatible)

 Commands entered on each positive CK edge

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 DQS edge-aligned with data for READs; center-aligned with data for WRITEs

 Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle

 Bidirectional data strobe (DQS) transmitted/received with data—i.e.,source-synchronous data capture

 Differential clock inputs (CK and CK# can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.)

 Four internal device banks for concurrent operation

 Selectable burst lengths: 2, 4 or 8

 Auto precharge option

 Auto Refresh and Self Refresh Modes

 15.6µs (MT4VDDT864H, MT8VDDT1664HD), 7.8125µs (MT4VDDT1664H, MT8VDDT3264HD,

MT8VDDT6464HD) maximum average periodic refresh interval

 Serial Presence Detect (SPD) with EEPROM

 Fast data transfer rates PC2100 or PC1600

 Selectable READ CAS latency for maximum compatibility

 Gold-plated edge contacts

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1.2.8 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHY Receiver is a

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Low-power, Physical-layer Device (PHY)

The VT6103L is a Physical Layer device for Ethernet 10Base-T and 100Base-TX using category 5 Unshielded and Type 1 Shielded cables. This VLSI device is designed for easy implementation of 10 / 100 Mb/s Fast Ethernet LANs. It interfaces to a MAC through an MII interface ensuring interoperability between products from different vendors.

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Product Features

 Single Chip 100Base-TX / 10Base-T Physical Layer Solution

 Dual Speed – 100 / 10 Mbps

 Half and Full Duplex

 MII Interface to Ethernet Controller

 MII Interface to Configuration & Status

 Auto Power Saving Mode

 Auto Negotiation: 10 / 100, Full / Half Duplex

 Meet All Applicable IEEE 802.3, 10Base-T and 100Base-Tx Standards

 On Chip Wave Shaping – No External Filters Required

 Adaptive Equalizer

 Baseline Wander Correction

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 LED Outputs

- Link Status

- Duplex status

- Speed Status

- Collision

 48 Pin LQFP Package

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1.2.9 Keyboard System: Winbond W83L950D

The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers, nine general purpose I/O port, 2k+256 bytes of RAM, four timer/counters, dual serial ports, 40K MTP-ROM that is divided into four banks, two SMBus interface for master and slave, support 4 PWM channels, 2 D-A and 8 A-D converters.

 8051 uC based

 Keyboard Controller Embedded Controller

 Supply embedded programmable flash memory (internal ROM size: 40KB) and RAM size is 2 KB

 Support 4 Timer (8 bit) signal with 3 prescalers

 Support 2 PWM channels, 2 D-A and 8 A-D converters

 Reduce Firmware burden by Hardware PS/2 decoding

 Support 72 useful GPIOs totally

 Support Flash utility for on board re-flash

 Support ACPI

 Hardware fast Gate A20 with software programmable

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1.3 Other Functi ons

1.3.1 Hot Key Function (TBD)

Keys Combination Meaning

Fn + F3

Fn + F4 Volume Increase

Fn + E5 Toggle Among LCD, External CRT

Fn + F6 LCD Brightness Decrease

Fn + F7 LCD Brightness Increase

Fn + F8 Disable Touchpad

Fn + F10 Mute

Fn + F11 Toggle Between LCD ON and OFF

Volume Decrease

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Fn + F12 Activate Suspend-to-Disk or Suspend-to-RAM

Fn + F1 Enable/Disable WLAN

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1.3.2 Power on/off/Suspend/Resume Button

APM mode

At APM mode, Power button is on/off system power.

ACPI mode

At ACPI mode. Windows power management control panel set power button behavior. You could set “standby”, “power off” or “hibernate”(must enable hibernate function in power Management) to power button function.

Continue pushing power button over 4 seconds will force system off at ACPI mode.

1.3.3 Cover Switch

System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover.

At ACPI mode there are four functions to be chosen at windows power management control panel.

1. None

2. Standby

3. Off

4. Hibernate (must enable hibernate function in power management)

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1.3.4 LED Indicators

1.3.4.1 Three LED Indicators

There are 2 sets of 3 LED indicators on panel housing and above keyboard separately.

From left to right that indicate WIRELESS LAN, POWER, BATTERY STATUS

Wireless LAN

This LED lights green when operated in wireless LAN mode, otherwise it turns off.

Power

This LED lights green when the notebook was powered by AC power line or Battery, Flashes (on 1 second, off 1 second) when entered suspend to RAM state. The LED is off when the notebook is in power off state.

Battery Status

During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged.

1.3.4.2 Five LED Indicators

System has 4 status LED indicators at front side which to display system activity. From left to right that indicate HARD DISK, NUM LOCK, CAPS LOCK, SCROLL LOCK.

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8965 N/B Maintenance

1.3.5 Battery Status

1.3.5.1 Battery Warning

System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store data before battery dead. This function also protects system from mal-function while battery capacity is low.

Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds.

System will Suspend to HDD after 2 Minutes to protect users data.

1.3.5.2 Battery Low State

After Battery Warning State and battery capacity is below 5%, system will generate beep sound for twice per second.

1.3.5.3 Battery Dead State

When the battery voltage level reaches 11.5 volts, system will shut down automatically in order to extend the battery packs' life.

1.3.6 Fan Power on/off Management

FAN is controlled by W83L950D embedded controller-using ADT7460 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.

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8965 N/B Maintenance

1.3.7 CMOS Battery

CR2032 3V 220mAh lithium battery

When AC in or system main battery inside, CMOS battery will consume no power

AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years

1.3.8 I/O Port

One Power Supply Jack.

One External CRT Connector For CRT Display

Supports four USB port for all USB devices

One RJ-45 for LAN

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Headphone Out Jack

Microphone Input Jack

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1.3.9 Battery Current Limit and Learning

Implanted H/W current limit and battery learning circuit to enhance protection of battery

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1.4 Power Management

The 8965 system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.

1.4.1 System Management Mode

Full on Mode

In this mode, each device is running with the maximal speed. CPU clock is up to its maximum.

Doze Mode

In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability.

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The CPU power consumption and temperature is lower in this mode.

Standby Mode

For more power saving, it turns off the peripheral components. In this mode, the following is the status of each

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device:

- CPU: stop grant

- LCD: backlight off

- HDD: spin down

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Suspend to DRAM and HDD

The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device

 Suspend to DRAM

- CPU: off

- Intel 855GME: partial off

- VGA: suspend

- PCMCIA: suspend

- Audio: off

- SDRAM: self refresh

 Suspend to HDD

- All devices are stopped clock and power-down

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- System status is saved in HDD

- All system status will be restored when powered on again

1.4.2 Other Power Management Functions

HDD & Video Access

System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending

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8965 N/B Maintenance

on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.

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+ 112 hidden pages

miscellaneous mitac 8965 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual