Mips Technologies R4000 User Manual
MIPS R4000 Microprocessor
User’s Manual
Second Edition
Joe Heinrich
1994 MIPS Technologies, Inc. All Rights Reserved.
RESTRICTED RIGHTS LEGEND
Use, duplication, or disclosure of the technical data contained in this
document by the Government is subject to restrictions as set forth in
subdivision (c) (1) (ii) of the Rights in Technical Data and Computer
Software clause at DFARS 52.227-7013 and/or in similar or successor
clauses in the FAR, or in the DOD or NASA FAR Supplement.
Unpublished rights reserved under the Copyright Laws of the United
States. Contractor/manufacturer is MIPS Technologies, Inc., 2011 N.
Shoreline Blvd., Mountain View, CA 94039-7311.
RISCompiler, RISC/os, R2000, R6000, R4000, and R4400 are trademarks of
MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of
MIPS Technologies, Inc.
IBM 370 is a registered trademark of International Business Machines.
VAX is a registered trademark of Digital Equipment Corporation.
iAPX is a registered trademark of Intel Corporation.
MC68000 is a registered trademark of Motorola Inc.
UNIX is a registered trademark in the United States and other countries,
licensed exclusively through X/Open Company, Ltd.
MIPS Technologies, Inc.
2011 North Shoreline
Mountain View, California 94039-7311
Acknowledgments for the First Edition
First of all, special thanks go to Duk Chun for his patient help in supplying and
verifying the content of this manual; that this manual is technically correct is, in a
very large part, directly attributable to him.
Thanks also to the following people for supplying portions of this book: Shabbir
Latif, for, among other things, the exception handler flow charts, the description
of the output buffer edge-control logic, and the interrupts; once again, Duk Chun,
for his paper on R4000 processor synchronization support; Paul Ries, for
confirming the accuracy of sections describing the memory management and the
caches; John Mashey, for verifying the R4000 processor actually does employ the
64-bit architecture; Dave Ditzel, for raising the issue in the first place; and Mike
Gupta, for substantiating various aspects of the errata. Finally, thanks to Ed
Reidenbach for supplying a large portion of the parity and ECC sections of this
manual, and Michael Ngo for checking their accuracy.
Thanks also to the following folks for their technical assistance: Andy Keane,
Keith Garrett, Viggy Mokkarala, Charles Price, Ali Moayedian, George Hsieh,
Peter Fu, Stephen Przybylski, Michael Woodacre, and Earl Killian. Also to be
thanked are the people at fvn@world.std.com: Bill Tuthill, Barry Shein, Bob
Devine, and Alan Marr, for helping place RISC in a pecuniary perspective. Also,
thanks to the following people at the mystery_train@swim2birds news group: toma,
dan_sears, jharris@garnet, tut@cairo (again), and elvis@dalkey(mateo_b). Their night-
for-day netversations, fueled by caffeine, concerning the viability of the
cyberpsykinetic compute-core model helped form an important basis of this book.
On the editorial front, thanks once again to Ms. Robin Cowan, of the Consortium
of Editorial Arts for her labors in editing this manual. Thanks to Evelyn Spire for
slaving over that bottomless black well we refer to as an “Index.” Thanks also,
once again, to Karen Gettman, and Lisa Iarkowski at Prentice-Hall for their help.
On the artistic side, thanks to Jeanne Simonian, of the Creative department here
at Silicon Graphics, for the book cover design; and thanks to Pam Flanders for
providing MarCom tactical support.
Have we missed anyone? If so, here is where we apologize for doing so.
Joe Heinrich
April 1, 1993
Mt. View, California
MIPS R4000 Microprocessor User's Manual iii
MIPS R4000 Microprocessor User's Manual iv
Acknowledgments for the Second Edition
Thanks go to Shabbir Latif, from whose errata the major part of this second
edition is derived. Thanks also to Charlie Price for, among other things, making
available his revision of the ISA.
On the production side, thanks to Kay Maitz, Beth Fraker, Molly Castor, Lynnea
Humphries, and Claudia Lohnes for their assistance at the center of the hurricane.
MIPS R4000 Microprocessor User's Manual v
Joe Heinrich
joeh@sgi.com
April 1, 1994
Mt. View, California
MIPS R4000 Microprocessor User's Manual vi
Preface
This book describes the MIPS R4000 and R4400 family of RISC
microprocessors (also referred to in this book as processor).
Overview of the Contents
Chapter 1 is a discussion (including the historical context) of RISC
development in general, and the R4000 microprocessor in particular.
Chapter 2 is an overview of the CPU instruction set.
Chapter 3 describes the operation of the R4000 instruction execution
pipeline, including the basic operation of the pipeline and
interruptions that are caused by interlocks and exceptions.
Chapter 4 describes the memory management system including
address mapping and address spaces, virtual memory, the translation
lookaside buffer (TLB), and the System Control Processor (CP0).
Chapter 5 describes the exception processing resources of R4000
processor. It includes an overview of the CPU exception handling
process and describes the format and use of each CPU exception
handling register.
MIPS R4000 Microprocessor User's Manual vii
Preface
Chapter 6 describes the Floating-Point Unit (FPU), a coprocessor for
the CPU that extends the CPU instruction set to perform floatingpoint arithmetic operations. This chapter lists the FPU registers and
instructions.
Chapter 7 describes the FPU exception processing.
Chapter 8 describes the signals that pass between the R4000 processor
and other components in a system. The signals discussed include the
System interface, the Clock/Control interface, the Secondary Cache
interface, the Interrupt interface, the Initialization interface, and the
JTAG interface.
Chapter 9 describes in more detail the Initialization interface, which
includes the boot modes for the processor, as well as system resets.
Chapter 10 describes the clocks used in the R4000 processor, as well as
the processor status reporting mechanism.
Chapter 11 discusses cache memory, including the operation of the
primary and secondary caches, and cache coherency in a
multiprocessor system.
Chapter 12 describes the System interface, which allows the processor
access to external resources such as memory and input/output (I/O).
It also allows an external agent access to the internal resources of the
processor, such as the secondary cache.
Chapter 13 describes the Secondary Cache interface, including read
and write cycle timing. This chapter also discusses the interface buses
and signals.
Chapter 14 describes the Joint Test Action Group (JTAG) interface.
The JTAG boundary scan mechanism tests the interconnections
between the R4000 processor, the printed circuit board to which it is
mounted, and other components on the board.
Chapter 15 describes the single nonmaskable processor interrupt,
along with the six hardware and two software processor interrupts.
Chapter 16 describes the error checking and correcting (ECC)
mechanisms of the R4000 processor.
viii MIPS R4000 Microprocessor User's Manual
A Note on Style
Preface
Appendix A describes the R4000 CPU instructions, in both 32- and 64bit modes. The instruction list is given in alphabetical order.
Appendix B describes the R4000 FPU instructions, listed
alphabetically.
Appendix C describes sub-block ordering, a nonsequential method of
retrieving data.
Appendix D describes the output buffer and the ∆i/∆t control
mechanism.
Appendix E describes the passive components that make up the
phase-locked loop (PLL).
Appendix F describes Coprocessor 0 hazards.
Appendix G describes the R4000 pinout.
A brief note on some of the stylistic conventions used in this book: bits,
fields, and registers of interest from a software perspective are
italicized (such as Config register); signal names of more importance
from a hardware point of view are rendered in bold (such as Reset*).
A range of bits uses a colon as a separator; for instance, (15:0)
represents the 16-bit range that runs from bit 0, inclusive, through bit
15. (In some places an ellipsis may used in place of the colon for
visibility: (15...0).)
MIPS R4000 Microprocessor User's Manual ix
Preface
x MIPS R4000 Microprocessor User's Manual
Preface to the Second Edition
Changes From the First Edition
The second edition of this book incorporates certain low-level changes
and technical additions, but retains a substantive identity with the
original version.
Changes from the first edition are indicated by left-margin vertical
rules.
Getting MIPS Documents On-Line
MIPS documents (including an electronic version of the errata) are
available on-line, through the file transport protocol (FTP). To
retrieve them, follow the steps below. The text you are to type is
shown in Courier Bold font; the computer’s responses are in
shown in Courier Regular font.
1. First, place yourself in the directory on your system within which
you want to store the retrieved files. Do this by typing:
cd <directory_you_want_file_to_be_in>
2. Access the MIPS document server, sgigate, through FTP by
typing:
ftp sgigate.sgi.com
3. The server tells you when you are connected for FTP by
responding:
Connected to sgigate.sgi.com.
MIPS R4000 Microprocessor User's Manual xi
Preface
4. Next (after some announcements) the server asks you to log in by
requesting a name and then a password.
Name (sgigate.sgi.com:<login_name>):
5. Login by typing anonymous for your name and your electronic
mail address for your password.
Name (sgigate.sgi.com:<login_name>): anonymous
331 Guest login ok, type your name as
password.
Password: your_email_address
6. The system indicates you have successfully logged in by
supplying an FTP prompt:
ftp>
7. Go to the pub/doc directory by typing:
ftp> cd pub/doc
8. You can take a look at the contents of the doc directory by listing
them:
ftp> ls
9. You will find several R4000-related subdirectories, such as R4200,
R4400, and R4600. When you find the subdirectory you want, cd
into that subdirectory and retrieve the file you want by typing:
get <filename>
This copies the file from sgigate back to your system.
10. When you have retrieved the files you want, exit from ftp by
typing:
ftp> quit
11. If the file was encoded for transmission, you must decode it, after
retrieval, by typing:
uudecode <filename>
12. If the file was compressed for transmission, you must uncompress
it, after retrieval, by typing:
uncompress <filename>
13. If you tarred the file, type:
tar xvof <filename>
xii MIPS R4000 Microprocessor User's Manual
Table of Contents
Preface
Overview of the Contents...................................................................................vii
A Note on Style ....................................................................................................ix
Preface to the Second Edition
Changes From the First Edition.........................................................................xi
Getting MIPS Documents On-Line.................................................................... xi
MIPS R4000 Microprocessor User's Manual xiii
Table of Contents
1
Introduction
Benefits of RISC Design...........................................................................................2
Shorter Design Cycle........................................................................................... 3
Effective Utilization of Chip Area ..................................................................... 3
User (Programmer) Benefits...............................................................................3
Advanced Semiconductor Technologies.......................................................... 3
Optimizing Compilers.........................................................................................4
MIPS RISCompiler Language Suite ..................................................................5
Compatibility............................................................................................................ 6
Processor General Features..................................................................................... 6
R4000 Processor Configurations ............................................................................7
R4400 Processor Enhancements............................................................................. 7
R4000 Processor........................................................................................................9
64-bit Architecture ............................................................................................... 9
Superpipeline Architecture ................................................................................11
System Interface................................................................................................... 11
CPU Register Overview......................................................................................12
CPU Instruction Set Overview...........................................................................14
Data Formats and Addressing........................................................................... 24
Coprocessors (CP0-CP2)..................................................................................... 27
System Control Coprocessor, CP0.................................................................27
Floating-Point Unit (FPU), CP1 ..................................................................... 30
Memory Management System (MMU).............................................................31
The Translation Lookaside Buffer (TLB)......................................................31
Operating Modes.............................................................................................32
Cache Memory Hierarchy.............................................................................. 32
Primary Caches................................................................................................33
Secondary Cache Interface............................................................................. 33
xiv MIPS R4000 Microprocessor User's Manual
2
CPU Instruction Set Summary
CPU Instruction Formats ........................................................................................36
Load and Store Instructions ...............................................................................37
Scheduling a Load Delay Slot........................................................................37
Defining Access Types....................................................................................37
Computational Instructions................................................................................39
64-bit Operations .............................................................................................39
Cycle Timing for Multiply and Divide Instructions................................... 40
Jump and Branch Instructions ...........................................................................41
Overview of Jump Instructions ..................................................................... 41
Overview of Branch Instructions ..................................................................41
Special Instructions..............................................................................................42
Exception Instructions......................................................................................... 42
Coprocessor Instructions ....................................................................................42
3
The CPU Pipeline
Table of Contents
CPU Pipeline Operation..........................................................................................44
CPU Pipeline Stages................................................................................................. 45
Branch Delay.............................................................................................................48
Load Delay ................................................................................................................48
Interlock and Exception Handling......................................................................... 49
Exception Conditions .......................................................................................... 52
Stall Conditions....................................................................................................53
Slip Conditions.....................................................................................................53
External Stalls ....................................................................................................... 53
Interlock and Exception Timing ........................................................................53
Backing Up the Pipeline .................................................................................54
Aborting an Instruction Subsequent to an Interlock..................................55
Pipelining the Exception Handling...................................................................56
Special Cases.........................................................................................................58
Performance Considerations.......................................................................... 58
Correctness Considerations............................................................................58
R4400 Processor Uncached Store Buffer ............................................................... 59
MIPS R4000 Microprocessor User's Manual xv
Table of Contents
4
Memory Management
Translation Lookaside Buffer (TLB) ......................................................................62
Hits and Misses .................................................................................................... 62
Multiple Matches .................................................................................................62
Address Spaces.........................................................................................................63
Virtual Address Space.........................................................................................63
Physical Address Space....................................................................................... 64
Virtual-to-Physical Address Translation..........................................................64
32-bit Mode Address Translation......................................................................65
64-bit Mode Address Translation......................................................................66
Operating Modes .................................................................................................67
User Mode Operations...................................................................................67
Supervisor Mode Operations........................................................................69
Kernel Mode Operations ............................................................................... 73
System Control Coprocessor ..................................................................................80
Format of a TLB Entry.........................................................................................81
CP0 Registers........................................................................................................84
Index Register (0).............................................................................................85
Random Register (1)........................................................................................86
EntryLo0 (2), and EntryLo1 (3) Registers.....................................................87
PageMask Register (5)..................................................................................... 87
Wired Register (6)............................................................................................88
EntryHi Register (CP0 Register 10)...............................................................89
Processor Revision Identifier (PRId) Register (15)......................................89
Config Register (16).........................................................................................90
Load Linked Address (LLAddr) Register (17) ............................................93
Cache Tag Registers [TagLo (28) and TagHi (29)]...................................... 93
Virtual-to-Physical Address Translation Process............................................ 95
TLB Misses............................................................................................................ 97
TLB Instructions...................................................................................................97
xvi MIPS R4000 Microprocessor User's Manual
5
CPU Exception Processing
How Exception Processing Works......................................................................... 100
Exception Processing Registers..............................................................................101
Context Register (4) .............................................................................................102
Bad Virtual Address Register (BadVAddr) (8)................................................103
Count Register (9) ................................................................................................ 103
Compare Register (11).........................................................................................104
Status Register (12)...............................................................................................105
Status Register Format....................................................................................105
Status Register Modes and Access States..................................................... 109
Status Register Reset .......................................................................................110
Cause Register (13) ..............................................................................................110
Exception Program Counter (EPC) Register (14) ............................................ 112
WatchLo (18) and WatchHi (19) Registers ....................................................... 113
XContext Register (20)......................................................................................... 114
Error Checking and Correcting (ECC) Register (26)....................................... 115
Cache Error (CacheErr) Register (27)................................................................116
Error Exception Program Counter (Error EPC) Register (30)........................118
Processor Exceptions ...............................................................................................119
Exception Types................................................................................................... 119
Reset Exception Process..................................................................................120
Cache Error Exception Process......................................................................120
Soft Reset and NMI Exception Process......................................................... 121
General Exception Process .............................................................................121
Exception Vector Locations................................................................................ 122
Priority of Exceptions..........................................................................................123
Reset Exception ....................................................................................................124
Soft Reset Exception ............................................................................................125
Address Error Exception..................................................................................... 127
TLB Exceptions.....................................................................................................128
TLB Refill Exception........................................................................................129
TLB Invalid Exception.....................................................................................130
TLB Modified Exception.................................................................................131
Cache Error Exception......................................................................................... 132
Virtual Coherency Exception ............................................................................. 133
Bus Error Exception.............................................................................................134
Integer Overflow Exception ...............................................................................135
Table of Contents
MIPS R4000 Microprocessor User's Manual xvii
Table of Contents
Trap Exception .....................................................................................................136
System Call Exception.........................................................................................137
Breakpoint Exception ..........................................................................................138
Reserved Instruction Exception.........................................................................139
Coprocessor Unusable Exception......................................................................140
Floating-Point Exception.....................................................................................141
Watch Exception ..................................................................................................142
Interrupt Exception.............................................................................................. 143
Exception Handling and Servicing Flowcharts ...................................................144
xviii MIPS R4000 Microprocessor User's Manual
6
Floating-Point Unit
Overview................................................................................................................... 152
FPU Features.............................................................................................................153
FPU Programming Model.......................................................................................154
Floating-Point General Registers (FGRs).......................................................... 154
Floating-Point Registers......................................................................................156
Floating-Point Control Registers .......................................................................157
Implementation and Revision Register, (FCR0)..............................................158
Control/Status Register (FCR31)....................................................................... 159
Accessing the Control/Status Register......................................................... 160
IEEE Standard 754 ........................................................................................... 161
Control/Status Register FS Bit....................................................................... 161
Control/Status Register Condition Bit.........................................................161
Control/Status Register Cause, Flag, and Enable Fields...........................161
Control/Status Register Rounding Mode Control Bits..............................163
Floating-Point Formats............................................................................................164
Binary Fixed-Point Format...................................................................................... 166
Floating-Point Instruction Set Overview.............................................................. 167
Floating-Point Load, Store, and Move Instructions........................................169
Transfers Between FPU and Memory........................................................... 169
Transfers Between FPU and CPU..................................................................169
Load Delay and Hardware Interlocks.......................................................... 169
Data Alignment................................................................................................ 170
Endianness........................................................................................................170
Floating-Point Conversion Instructions............................................................170
Floating-Point Computational Instructions..................................................... 170
Branch on FPU Condition Instructions............................................................. 170
Floating-Point Compare Operations.................................................................171
FPU Instruction Pipeline Overview.......................................................................172
Instruction Execution ..........................................................................................172
Instruction Execution Cycle Time .....................................................................173
Scheduling FPU Instructions.............................................................................. 175
FPU Pipeline Overlapping.................................................................................. 175
Instruction Scheduling Constraints ..............................................................176
Instruction Latency, Repeat Rate, and Pipeline Stage Sequences.............181
Resource Scheduling Rules ............................................................................ 182
Table of Contents
MIPS R4000 Microprocessor User's Manual xix
Table of Contents
7
Floating-Point Exceptions
Exception Types........................................................................................................188
Exception Trap Processing......................................................................................189
Flags ...........................................................................................................................190
FPU Exceptions......................................................................................................... 192
Inexact Exception (I)............................................................................................ 192
Invalid Operation Exception (V)........................................................................ 193
Division-by-Zero Exception (Z).........................................................................194
Overflow Exception (O)...................................................................................... 194
Underflow Exception (U).................................................................................... 195
Unimplemented Instruction Exception (E) ...................................................... 196
Saving and Restoring State ..................................................................................... 197
Trap Handlers for IEEE Standard 754 Exceptions............................................... 198
8
R4000 Processor Signal Descriptions
System Interface Signals..........................................................................................201
Clock/Control Interface Signals ............................................................................203
Secondary Cache Interface Signals........................................................................ 205
Interrupt Interface Signals ......................................................................................207
JTAG Interface Signals............................................................................................. 207
Initialization Interface Signals................................................................................208
Signal Summary .......................................................................................................209
xx MIPS R4000 Microprocessor User's Manual
9
Initialization Interface
Functional Overview ...............................................................................................214
Reset Signal Description.......................................................................................... 215
Power-on Reset..................................................................................................... 216
Cold Reset .............................................................................................................217
Warm Reset...........................................................................................................217
Initialization Sequence.............................................................................................218
Boot-Mode Settings..................................................................................................222
10
Clock Interface
Signal Terminology..................................................................................................228
Basic System Clocks.................................................................................................229
MasterClock..........................................................................................................229
MasterOut .............................................................................................................229
SyncIn/SyncOut................................................................................................... 229
PClock....................................................................................................................229
SClock.................................................................................................................... 230
TClock....................................................................................................................230
RClock.................................................................................................................... 230
PClock-to-SClock Division .................................................................................230
System Timing Parameters..................................................................................... 233
Alignment to SClock............................................................................................ 233
Alignment to MasterClock .................................................................................233
Phase-Locked Loop (PLL)................................................................................... 233
Connecting Clocks to a Phase-Locked System.....................................................234
Connecting Clocks to a System without Phase Locking.....................................235
Connecting to a Gate-Array Device ..................................................................235
Connecting to a CMOS Logic System............................................................... 238
Processor Status Outputs ........................................................................................ 241
Table of Contents
MIPS R4000 Microprocessor User's Manual xxi
Table of Contents
11
Cache Organization, Operation, and Coherency
Memory Organization............................................................................................. 244
Overview of Cache Operations.............................................................................. 245
R4000 Cache Description......................................................................................... 246
Secondary Cache Size..........................................................................................248
Variable-Length Cache Lines ............................................................................. 248
Cache Organization and Accessibility..............................................................248
Organization of the Primary Instruction Cache (I-Cache)......................... 249
Organization of the Primary Data Cache (D-Cache)..................................250
Accessing the Primary Caches.......................................................................251
Organization of the Secondary Cache.......................................................... 252
Accessing the Secondary Cache.....................................................................254
Cache States............................................................................................................... 255
Primary Cache States...........................................................................................256
Secondary Cache States....................................................................................... 256
Mapping States Between Caches....................................................................... 257
Cache Line Ownership............................................................................................ 258
Cache Write Policy...................................................................................................259
Cache State Transition Diagrams...........................................................................260
Cache Coherency Overview ................................................................................... 264
Cache Coherency Attributes...............................................................................264
Uncached ..........................................................................................................265
Noncoherent.....................................................................................................265
Sharable.............................................................................................................265
Update...............................................................................................................265
Exclusive ........................................................................................................... 266
Cache Operation Modes......................................................................................266
Secondary-Cache Mode..................................................................................266
No-Secondary-Cache Mode........................................................................... 266
Strong Ordering ...................................................................................................267
An Example of Strong Ordering....................................................................267
Testing for Strong Ordering...........................................................................267
Restarting the Processor .................................................................................268
Maintaining Coherency on Loads and Stores......................................................269
Manipulation of the Cache by an External Agent............................................... 270
Invalidate...............................................................................................................270
Update ...................................................................................................................270
xxii MIPS R4000 Microprocessor User's Manual
Table of Contents
Snoop ..................................................................................................................... 270
Intervention...........................................................................................................271
Coherency Conflicts.................................................................................................271
How Coherency Conflicts Arise ........................................................................ 272
Processor Coherent Read Requests...............................................................272
Processor Invalidate or Update Requests ....................................................273
External Coherency Requests ........................................................................274
System Implications of Coherency Conflicts................................................... 275
System Model...................................................................................................276
Load...................................................................................................................278
Store...................................................................................................................278
Processor Coherent Read Request and Read Response.............................278
Processor Invalidate........................................................................................ 279
Processor Write................................................................................................ 279
Handling Coherency Conflicts........................................................................... 280
Coherent Read Conflicts.................................................................................280
Coherent Write Conflicts................................................................................281
Invalidate Conflicts .........................................................................................282
Sample Cycle: Coherent Read Request.............................................................283
R4000 Processor Synchronization Support........................................................... 286
Test-and-Set (Spinlock) .......................................................................................286
Counter..................................................................................................................288
LL and SC..............................................................................................................289
Examples Using LL and SC................................................................................ 290
MIPS R4000 Microprocessor User's Manual xxiii
Table of Contents
12
System Interface
Terminology..............................................................................................................294
System Interface Description..................................................................................294
Interface Buses......................................................................................................295
Address and Data Cycles ...............................................................................296
Issue Cycles ......................................................................................................296
Handshake Signals..............................................................................................298
System Interface Protocols......................................................................................299
Master and Slave States....................................................................................... 299
Moving from Master to Slave State...................................................................300
External Arbitration............................................................................................. 300
Uncompelled Change to Slave State .................................................................301
Processor and External Requests ...........................................................................302
Rules for Processor Requests.............................................................................. 303
Processor Requests...............................................................................................304
Processor Read Request..................................................................................306
Processor Write Request.................................................................................307
Processor Invalidate Request.........................................................................308
Processor Update Request..............................................................................310
Clusters..............................................................................................................311
External Requests.................................................................................................313
External Read Request.................................................................................... 316
External Write Request................................................................................... 316
External Invalidate Request ........................................................................... 316
External Update Request................................................................................316
External Snoop Request..................................................................................317
External Intervention Request....................................................................... 317
Read Response .................................................................................................317
Handling Requests...................................................................................................318
Load Miss..............................................................................................................318
Secondary-Cache Mode..................................................................................320
No-Secondary-Cache Mode........................................................................... 320
Store Miss..............................................................................................................321
Secondary-Cache Mode..................................................................................323
No-Secondary-Cache Mode........................................................................... 325
Store Hit.................................................................................................................326
Secondary-Cache Mode..................................................................................326
xxiv MIPS R4000 Microprocessor User's Manual
Table of Contents
No-Secondary-Cache Mode........................................................................... 326
Uncached Loads or Stores ..................................................................................326
CACHE Operations............................................................................................. 327
Load Linked Store Conditional Operation....................................................... 327
Processor and External Request Protocols............................................................329
Processor Request Protocols...............................................................................330
Processor Read Request Protocol.................................................................. 330
Processor Write Request Protocol................................................................. 333
Processor Invalidate and Update Request Protocol ................................... 335
Processor Null Write Request Protocol........................................................ 336
Processor Cluster Request Protocol .............................................................. 337
Processor Request and Cluster Flow Control.............................................. 338
External Request Protocols.................................................................................341
External Arbitration Protocol......................................................................... 342
External Read Request Protocol ....................................................................343
External Null Request Protocol .....................................................................344
External Write Request Protocol ...................................................................347
External Invalidate and Update Request Protocols....................................348
External Intervention Request Protocol .......................................................349
External Snoop Request Protocol.................................................................. 352
Read Response Protocol..................................................................................354
Data Rate Control.....................................................................................................356
Data Transfer Patterns......................................................................................... 356
Secondary Cache Transfers ................................................................................357
Secondary Cache Write Cycle Time.................................................................. 358
Independent Transmissions on the SysAD Bus ..............................................359
System Interface Endianness..............................................................................360
System Interface Cycle Time...................................................................................361
Cluster Request Spacing .....................................................................................361
Release Latency.................................................................................................... 362
External Request Response Latency.................................................................. 363
System Interface Commands and Data Identifiers.............................................. 364
Command and Data Identifier Syntax..............................................................364
System Interface Command Syntax ..................................................................365
Read Requests .................................................................................................. 366
Write Requests .................................................................................................367
Null Requests................................................................................................... 369
Invalidate Requests .........................................................................................370
MIPS R4000 Microprocessor User's Manual xxv
Table of Contents
Update Requests.............................................................................................. 370
Intervention and Snoop Requests .................................................................372
System Interface Data Identifier Syntax ........................................................... 374
Coherent Data ..................................................................................................374
Noncoherent Data............................................................................................374
Data Identifier Bit Definitions........................................................................ 375
System Interface Addresses....................................................................................377
Addressing Conventions ....................................................................................377
Sequential and Subblock Ordering....................................................................378
Processor Internal Address Map............................................................................ 378
13
Secondary Cache Interface
Data Transfer Rates..................................................................................................380
Duplicating Signals..................................................................................................380
Accessing a Split Secondary Cache........................................................................381
SCDChk Bus..............................................................................................................381
SCTAG Bus................................................................................................................ 381
Operation of the Secondary Cache Interface........................................................ 382
Read Cycles...........................................................................................................383
4-Word Read Cycle.......................................................................................... 383
8-Word Read Cycle.......................................................................................... 384
Notes on a Secondary Cache Read Cycle.....................................................384
Write Cycles..........................................................................................................385
4-Word Write Cycle......................................................................................... 385
8-Word Write Cycle......................................................................................... 386
Notes on a Secondary Cache Write Cycle....................................................387
xxvi MIPS R4000 Microprocessor User's Manual
14
JTAG Interface
What Boundary Scanning Is ................................................................................... 390
Signal Summary .......................................................................................................391
JTAG Controller and Registers............................................................................... 392
Instruction Register..............................................................................................392
Bypass Register.....................................................................................................393
Boundary-Scan Register......................................................................................394
Test Access Port (TAP)........................................................................................395
TAP Controller.................................................................................................396
Controller Reset ...............................................................................................396
Controller States...............................................................................................396
Implementation-Specific Details............................................................................400
15
R4000 Processor Interrupts
Hardware Interrupts................................................................................................ 402
Nonmaskable Interrupt (NMI)...............................................................................402
Asserting Interrupts.................................................................................................402
Table of Contents
MIPS R4000 Microprocessor User's Manual xxvii
Table of Contents
16
Error Checking and Correcting
Error Checking in the Processor.............................................................................408
Types of Error Checking.....................................................................................408
Parity Error Detection.....................................................................................408
SECDED ECC Code......................................................................................... 409
Error Checking Operation .................................................................................. 412
System Interface...............................................................................................412
Secondary Cache Data Bus.............................................................................412
System Interface and Secondary Cache Data Bus....................................... 412
Secondary Cache Tag Bus...............................................................................413
System Interface Command Bus ...................................................................413
SECDED ECC Matrices for Data and Tag Buses.............................................414
ECC Check Bits..................................................................................................... 414
Data ECC Generation.......................................................................................... 415
Detecting Data Transmission Errors................................................................. 418
Single Data Bit ECC Error ..............................................................................420
Single Check Bit ECC Error............................................................................ 421
Double Data Bit ECC Errors........................................................................... 422
Three Data Bit ECC Errors .............................................................................423
Four Data Bit ECC Errors ............................................................................... 424
Tag ECC Generation............................................................................................425
Summary of ECC Operations............................................................................. 426
R4400 Master/Checker Mode.................................................................................430
Connecting a System in Lock Step ....................................................................431
Master-Listener Configuration ..........................................................................432
Cross-Coupled Checking Configuration..........................................................433
Fault Detection .....................................................................................................435
Reset Operation....................................................................................................436
Fault History.........................................................................................................436
xxviii MIPS R4000 Microprocessor User's Manual
A
CPU Instruction Set Details
B
FPU Instruction Set Details
C
Subblock Ordering
Sequential Ordering.................................................................................................C-2
Subblock Ordering................................................................................................... C-2
D
Output Buffer ∆i/∆t Control Mechanism
Mode Bits...................................................................................................................D-1
Delay Times............................................................................................................... D-2
E
PLL Passive Components
F
Coprocessor 0 Hazards
Table of Contents
G
R4000 Pinouts
Pinout of R4000PC....................................................................................................G-2
Pinout of R4000MC/SC Package Pinout ..............................................................G-5
Index
MIPS R4000 Microprocessor User's Manual xxix
Table of Contents
xxx MIPS R4000 Microprocessor User's Manual
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