Midland Radio SD125V3 Users manual

User

Guide

SD 125V3 DATA RADIO

Topaz3, LLC. 10828 N.W. Airworld Dr. Kansas City, MO 64153 Tel: [phone] Fax: [phone]

August 2002

SD 125V3

THEORY OF OPERATION

The SD 125V3 radio is comprised of two PCB's (an RF PCB and a digital PCB).
These boards are connected with an 18 pin female and male connector. The digital
board is interfaced with external data equipment through the 9 pin d-sub male connec­tor, which controls the radio and data receiving and sending.

DIGITAL CIRCUIT

The digital circuit is charged to be control for all of the signal path and set the frequen­cies to be set and selecting the desired channel.

TX-Signal circuit

The TX data signal comes from Pin 2 of Con 401, and goes through U404D. The TX­signal is amplified by U406C. The TX-signal is filtered by U405A & B which is a 4'th
order low pass filter, therefore, the filtered signal supply to the RF board for TX modu­lation.

THEORY OF OPERATION

RX-Signal Circuit

RSSI Detector

EEPROM

Channel Selector

DC to DC Converter

The RX- data signal comes from the RF board, which is connected with pin 10 of Con

403. The RX-signal is switched by U404A and adjusted by RV403 and amplified by
U407. The amplified signal goes to pin10 of Con 401.

From the RF board, the RSSI (Received Signal Strength Indicator ) signal comes to
U403A & B through R461. The pulse is injected from pin 5 of U403B every 1 ms and
C451 is discharged. After then, it begins to be charged by R464. Simultaneously,
RSSI signal is input to pin 7 of U403A and those signals are compared. The compared
signal is output from U403A. Pin 1 and the CPU detects the pulse width. The pulse
width is varied by RSSI DC voltage. Therefore, the CPU determines the carrier detec­tion .

RX. TX channel and RSSI detection level as well as other data from the programmer
are stored in the EEPROM. The data stored is retained without power supplied. This
is a non-volatile memory . The EEPROM may have information re-programmed or
erased. U402 is an EEPROM with 2048 capacity and data is written and read serially.

One of 16 channels may be selected using the clip switch named SW401 . SW401
encodes the channel number, selected into 4-bit binary code. The binary code plus
one equals the channel number. The binary code is decoded by the CPU enabling the
appropriate RX or TX frequency and associated data to be selected from the
EEPROM. In the binary bit of SW401, the lower 2 bits are connected to Con402. It
causes the low 4 channels to be selected from the external equipment's.

The main DC power is injected to the DC to DC converter . The DC to DC converter
regulates the various input power supply voltage and outputs a constant voltage of 7.5
Volts. It is a source for all of the RF and digital circuits.
The DC to DC converter is formed by U801, Q801, Q802, L801 and R804. U801 is a
switch mode DC to DC Converter IC. Input DC various appears as a voltage various
through R804. U801 detects the voltage and controls the switching pulse. As the
switching pulses, Q801and Q802 switches the input DC of various supply voltages
and generates the constant DC of supply voltage.

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August 2002

RF CIRCUITS

TRANSMITTER

SD 125V3

The transmitter is comprised of:

1. Buffer

2. P.A Module

3. Low Pass Filter

4. Antenna Switch

5. A.P.C Circuits

Buffer

P. A . M o du l e

Low Pass Filter

Antenna Switch

Automatic Current
Control (ACC) Circuits

VCO output level is -6dBm and amplified to, +6dBm. The buffer consists of Q16 and
Q17 for isolation and gain.

The P.A Module contains Q501, Q502, and Q503. Three stage amplifier Q501 ampli­fies the TX signal from +10 dBm to 100 mW. Q502 is amplified to 0.5W. Q503 ampli­fies to 3W and then matched to 50 OHMs using the L.C. network, thereby reducing
the harmonics by -30 dB.

L7, L8, L11, C72, C73, C74 and C75 are the 7th order Chebyshev low pass filter.
Unwanted harmonics are reduced by -70 dBc.

When transmitting, the diodes D5 and D6 are forward biased enabling the RF signal
passage to the antenna. D6 is shorted to ground inhibiting the RF signal to front end.
In receive the diodes D5 and D6 are reversed biased passing the signal from the
antenna through L13 and C83 to the front end without signal loss.

The ACC circuit consists of R109, variable resistor RV1, IC3(B) and transistors Q21
and Q22. The supply current is monitored by the difference voltage on R109 (0.1
Ohm). If the current varies by RF power output or other reasons, it produces some
bias voltage by IC3A and Q19. The differential signal at the output of IC3 is passed to
Q21 and Q22 that produces a constant power output to the antenna. RV1 is used to
adjust the RF power level.

RF CIRCUITS PLL SYNTHESIZER

12.8 MHz TCXO

THEORY OF OPERATION

The TCXO contains the 3-stage thermistor network compensation and crystal oscilla­tor and modulation ports. Compensation is +/-5 PPM or less from -30c to +60c.

PLL IC Dual Modules
Prescaler

Page -2­August 2002

Input frequency of 12.8 MHz to IC2 MC14519 pin 20 is divided to 6.25 KHz or 5 KHz
by the reference counter, and then supplied to the comparator. RF signal input from
VCO is divided to 1/64 at the prescaler in IC2, divided by A and N counter in IC2 to
determine frequency steps, and then supplied to the comparator. PLL comparison
frequency is 6.25/5KHz so that minimum programmable frequency step is 5/6.25 KHz.
The A and N counter is programmed to obtain the desired frequency by serial data in
the CPU. In the comparator, the phase difference between reference and VCO signal
is compared. When the phase of the reference frequency is leading , Fv is the output,
but when VCO frequency is leading, Fr is the output. When Fv=Fr, phase detector out
is a very small pulse. 64/65 modulus prescaler is comprised in IC2, and has two out­put ports:
Port A pin 16: TX enable 2