Midas RTE-V831-PC User Manual
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
RTE-V831-PC
USER’S MANUAL (Rev. 2.00)
Midas lab
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
REVISION HISTORY
Date REV. Chapter Explanation of revision
Apr. 14 1997 1.02 First edition
Apr. 28 1998 2.00
5.19
8.3
8.9
A description of the use of the PARTNER monitor has been added.
Corrections have been made to the following descriptions:
JCPU-A, pin 26 (+3..3 V → +3.3 V), pin 98 (+5 V → GND)
Logical address in the table (BC00-0000H → 4500-2000H)
Request levels listed in the interrupt source table
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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CONTENTS
1. INTRODUCTION..................................................................................................................... 1
1.1. NUMERIC NOTATION ........................................................................................................................1
2. FUNCTIONS............................................................................................................................ 1
3. MAJOR FEATURES................................................................................................................ 2
4. BASIC SPECIFICATIONS.......................................................................................................2
5. BOARD CONFIGURATION..................................................................................................... 3
5.1. RESET SWITCH (RESET) .................................................................................................................3
5.2. POWER JACK (JPOWER).................................................................................................................3
5.3. SWITCH 1 (SW1).................................................................................................................................3
5.4. SWITCH 2 (SW2).................................................................................................................................4
5.5. LED ..........................................................................................................................................................4
5.6. TEST PINS FOR ROM EMULATOR (TP)......................................................................................4
5.7. CLOCK SOCKET (OSC1)..................................................................................................................5
5.8. 72-PIN-SIMM SOCKETS (SIMM#1, SIMM#2)...............................................................................5
5.9. ROM SOCKETS ...................................................................................................................................5
5.10. ROM SIZE SWITCHING JUMPER (JP1)........................................................................................5
5.11. ROM DIVISION SWITCHING JUMPER (JP2)...............................................................................5
5.12. JP3, JP4, JP5 ........................................................................................................................................6
5.13. JUMPER FOR SWITCHING BETWEEN BASIC CLOCKS FOR USER TIMERS (JP6)......6
5.14. SERIAL CONNECTOR (JSIO1, JSIO2)..........................................................................................6
5.15. PARALLEL CONNECTOR (JPRT)...................................................................................................7
5.16. AUDIO MINI-JACKS (JMIC-R, JMIC-L, JOUT) .............................................................................7
5.17. DEBUGGING CONNECTOR (JDBG)..............................................................................................8
5.18. EXTENSION BUS CONNECTOR (JEXT)......................................................................................8
5.19. CPU CONNECTOR (JCPU-A, JCPU-B).........................................................................................9
6. CONNECTION WITH THE HOST PC .................................................................................... 11
6.1. INSTALLATION ON THE ISA BUS............................................................................................... 11
6.2. STANDALONE USE OF THE BOARD......................................................................................... 11
7. HARDWARE REFERENCES ................................................................................................ 12
7.1. MEMORY AND I/O MAP..................................................................................................................12
7.2. DETAILS OF MAPPING................................................................................................................... 13
8. SYSTEM-I/O.......................................................................................................................... 14
8.1. SYSTEM-I/O LIST............................................................................................................................. 14
8.2. DIPSW1 READ PORT (4500-1000H [READ ONLY])............................................................... 14
8.3. 7-SEGMENT LED DISPLAY DATA OUTPUT PORT (4500-2000H [WRITE ONLY]) ....... 15
8.4. COMMAND REGISTER #0 PORT (4500-3000H [READ/WRITE])........................................ 15
8.5. COMMAND REGISTER #1 PORT (4500-4000H [READ/WRITE])........................................ 15
8.6. COMMAND REGISTER #2 PORT (4500-5000H [READ/WRITE])........................................ 16
8.7. UART/PRINTER (TL16C552A) (4500-8000H TO 4500-A00CH)........................................... 16
8.8. TIC (mPD71054) (4500-B000H TO 4500-B00CH)......................................................................17
8.9. INTERRUPT CONTROLLER (PIC) (4500-D000H TO 4500-D018H)....................................18
8.10. AUDIO CONTROLLER (AUDCNT) (4580-0000H TO 4580-0010H, 4580-2000H) ............ 19
8.11. mPD63310 REGISTER: AUDIO COD. (4580-1000H TO 4580-100FH)............................... 21
9. INTERRUPTS AND DMA ...................................................................................................... 22
9.1. INTERRUPT....................................................................................................................................... 22
9.2. USING NMI ......................................................................................................................................... 22
9.3. DMA CHANNEL................................................................................................................................. 23
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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10. EXT BUS SPECIFICATIONS................................................................................................. 24
10.1. PIN ARRANGEMENT AND SIGNALS.......................................................................................... 24
10.2. TIMING................................................................................................................................................. 25
10.3. NOTES ON USING THE EXT BUS............................................................................................... 26
11. SOFTWARE.......................................................................................................................... 27
11.1. INITIALIZATION................................................................................................................................. 27
11.2. LIBRARIES......................................................................................................................................... 27
11.3. USING TIMERS ................................................................................................................................. 28
11.4. FLASH ROM PROGRAMMING ..................................................................................................... 29
11.5 AUDIO I/O........................................................................................................................................... 31
12. DEVELOPMENT OF APPLICATIONS USING MASKABLE INTERRUPTS........................... 33
12.1. INTERRUPT VECTOR..................................................................................................................... 33
12.2. INTERNAL INSTRUCTION RAM...................................................................................................34
12.3. GENERAL RESTRICTIONS/NOTES............................................................................................ 34
12.4. RESTRICTIONS ON BREAKS IN THE INTERRUPT HANDLING ROUTINE.................... 35
13. APPENDIX A MULTI MONITOR........................................................................................... 36
13.1. BOARD SETTING ............................................................................................................................. 36
13.1.1. RTE for Win 32 installation ................................................................................................36
13.2. SWITCH SETTING............................................................................................................................36
13.2.1. SW1 Setting..........................................................................................................................36
13.2.2. SW2 Setting..........................................................................................................................37
13.3. MULTI MONITOR.............................................................................................................................. 38
13.3.1. Monitor Work RAM...............................................................................................................38
13.3.2. Interrupt ..................................................................................................................................38
13.3.3. Interrupt for Forced Break..................................................................................................38
13.3.4. _INIT_SP Setting .................................................................................................................38
13.3.5. Remote Connection.............................................................................................................38
13.3.6. Monitor Execution Area ......................................................................................................38
13.4. RTE COMMANDS............................................................................................................................. 39
13.4.1. HELP(?)..................................................................................................................................39
13.4.2. INIT..........................................................................................................................................39
13.4.3. VER.........................................................................................................................................39
13.4.4. INB, INH, INW.......................................................................................................................39
13.4.5. OUTB, OUTH, OUTW.........................................................................................................40
13.4.6. DCTR Command..................................................................................................................40
13.4.7. ITCR Command....................................................................................................................40
13.4.8. CMCR Command.................................................................................................................40
13.4.9. SFR Command.....................................................................................................................40
14. APPENDIX B PARTNER MONITOR..................................................................................... 41
14.1. SWITCH SETTING............................................................................................................................41
14.1.1. SW1 Setting..........................................................................................................................41
14.1.2. SW2 Setting..........................................................................................................................42
14.2. PARTNER MONITOR....................................................................................................................... 43
14.2.1. Monitor Work RAM...............................................................................................................43
14.2.2. Interrupt ..................................................................................................................................43
14.2.3. Interrupt for Forced Break..................................................................................................43
14.2.4. SP Setting..............................................................................................................................43
14.2.5. Remote Connection.............................................................................................................43
14.2.6. Monitor Execution Area ......................................................................................................43
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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1. INTRODUCTION
The RTE-V831-PC is an evaluation board, conforming to the IBM-PC/AT ISA bus specification, that is
designed to evaluate the NEC V831 RISC processor. The board features a V831 capable of operating at
a maximum speed of 100 MHz, memory, serial and parallel interfaces, and inputs/outputs such as audio
inputs/outputs. For interfacing with memory, the memory controller built into the V831 is used.
These functions enable the RTE-V831-PC to be used for a wide variety of applications including processor
performance evaluation and application program development at the initial stage, and to also be used as
an engine for demonstration and simulation.
The GHS Multi or NEC PARTNER source-level debugger can be used as a development software tool
with the RTE-V831-PC. The type of monitor to be stored in ROM depends on the debugger type.
In ROM, the monitor specified at the time of purchase is stored. Even when neither of the debuggers is
purchased together with the RTE-V831-PC, they can be purchased at anytime subsequently.
1.1. NUMERIC NOTATION
This manual represents numbers according to the notation described in the following table.
Hexadecimal and binary numbers are hyphenated at every four digits, if they are difficult to read
because of many digits being in each number.
Number Notation rule Example
Decimal number Only numerals are indicated. "10" represents number 10 in decimal.
Hexa-decimal
number
A number is suffixed with letter H. "10H" represents number 16 in decimal.
Binary number A number is suffixed with letter B. "10B" represents number 2 in decimal.
Number Notation Rules
2. FUNCTIONS
The overview of each function block of the RTE-V831-PC is shown below.
V831
ISA Bus
Local Bus
ISA BUS I/F
JEXT
CONNECTOR
D-RAM
S-RAM
5V <> 3.3V
ROM
Audio
SIO/PRT
Mini jack *3
RS-232C
CONNECTOR
TIMER
USER
HW
PARALLEL
CONNECTOR
Internal
Control
FPGA,..
CPU
CONNECTOR
Flash
ROM
RTE-V831-PC Block Diagram
MULTI is a trademark of Green Hills Software, Inc. in the US.
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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3. MAJOR FEATURES
• Two types of monitor ROM are provided: one is used for the Green Hills Multi and the other for the NEC
PARTNER.
• Real-time execution and evaluation at a high-level language level using Multi or PARTNER.
• A ROM emulator can be connected.
• A high-speed 512K bytes SRAM is installed as standard. Up to 16M bytes of DRAM can be installed
using SIMMs.
• Two serial interfaces and one printer interface are provided.
• Two timer channels are provided. (One channel is used for the Multi monitor.)
• Two audio input channels and two audio output channels are provided.
4. BASIC SPECIFICATIONS
Processor V831
CPU clock 100 MHz (max.)
Bus clock 33 MHz (max.)
Power consumption +5 V (2.0 A)
Memory
EPROM
128 KB 64 K × 16 bits (40-pin DIP) × 1 (512K bytes max.)
Flash ROM
SRAM
8 MB 2 M × 8 bits × 4 (MBM29F016-120)
512 KB 128 K × 8 bits × 4
DRAM 8 MB EDO-SIMM-72pin
(16M bytes max. with two SIMMs)
I/O
Serial (2 ch) Equivalent to NS16550, 10-pin header, DB9 connector
Printer PS2-compatible, 26-pin header
Audio input/output (2 ch)
mPD66310, Mini-jack (MIC × 2, LINEOUT × 1)
Timer Equivalent to i8254, 500-ns resolution
I/O port LED (7-segment) display/switch input
Others
CPU connector
Standard external
extension connector
Connector with all function pins of the V831 connected
RTE-PC standard 16-bit interface (1M byte, 16-bit bus)
Reset switch Push type
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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5. BOARD CONFIGURATION
The physical layout of the major components on the RTE-V831-PC board is shown below. This chapter
explains each component.
SW2
RESET
JPOWER
JEXT
JSIO
JMIC-R
JMIC-L
JOUT
PLD
SIO/PRT
PLD3
LEDxx
FIFO * 4
timer
JDBG
5V -> 3V
JCPU-A(1-80)
JCPU-B(81-160)
SIMM#2
SIMM#1
PLD2
PLD1
ROM
RAMRAM
JP5JP4
JP3
JP2
JP1
JPRT
JSIO2
RAM RAM
V831
7seg LED
TP
Audio
OSC3
OSC1OSC2
1pin
SIM-72pin x 2
A20
B20
B1
A1
160
159
80
79
82
81
211pin
1pin
1pin
1pin
SW1
RTE-V831-PC Components Layout
5.1. RESET SWITCH (RESET)
RESET is a reset switch for the entire board. Pressing this switch causes all the circuits including the
CPU to be reset.
5.2. POWER JACK (JPOWER)
When this board is to be used as a standalone, that is, without being inserted in an ISA bus slot, the
board should be supplied with power from an external power supply by connecting it to the JPOWER
connector.
The external power should be one rated as listed below.
Voltage: 5 V
Current: Maximum of 2 A (excluding the current supplied to the JEXT connector)
Mating connector: Type A (5.5 mm in diameter)
Polarity:
GND
GND
+5V
+5V
[Caution] When attaching an external power supply to the board, be careful about its connector
polarity. When inserting the board into the ISA bus slot, do not attach the JPOWER connector to an
external power supply. It may result in a malfunction.
5.3. SWITCH 1 (SW1)
SW1 is a general-purpose input port switch. When the monitor is used, all SW1 switches except SW1-7
are already set. See Sections 13.2.1. and 14.1.1, for the switch settings for the Multi and PARTNER
monitors, respectively. When the port is read, a switch being set to OFF represents 1, while its being set
to ON represents 0. For details, see Section 8.2.
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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5.4. SWITCH 2 (SW2)
SW2 is a switch for selecting the I/O address of the ISA bus. Switches 1 to 8 correspond to ISA
addresses A4 to A11, respectively (A12 to A15 are fixed at 0). This means that the I/O address that can
be selected ranges between 00xH and 03FxH. When a switch is open, it corresponds to 1. When it is
closed, it corresponds to 0.
SW2 1 2 3 4 5 6 7 8
ISA address A4 A5 A6 A7 A8 A9 A10 A11
SW2-to-ISA Address Correspondence
5.5. LED
The LEDs are used to indicate statuses, as listed below.
LED Description
POWER Lights when power is supplied to the RTE-V831-PC board.
PLY Lights in green when voice is output.
Lights in red if an error occurs during voice output.
REC Lights in green when voice is recorded.
Lights in red if an error occurs during voice recording.
TOVER Lights when a time-out occurs.
FLBUSY Lights while the flash ROM is busy (during a write operation, erasure, etc.)
LED Indication
5.6. TEST PINS FOR ROM EMULATOR (TP)
Test pins are used to connect a ROM emulator. They accept control signals from the ROM emulator.
The following table lists the signal names and functions related to each test pin.
Signal
Input/
output
Function
RESET- Input When a low level is supplied to this test pin, the CPU is reset.
A reset request signal from the ROM emulator is connected to the test pin.
The test pin is pulled up with 1kΩ.
NMI- Input When a low level is supplied to this test pin, an NMI signal is given to the CPU. This
signal can be masked by software, so it is necessary to reset the mask. (See Section
8.9.)
An NMI request signal from the ROM emulator is connected to the test pin.
The test pin is pulled up with 1kΩ.
GND --- This test pin is at a ground level. The ground level of the ROM emulator is connected
to the test pin.
Test Pin Functions
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5.7. CLOCK SOCKET (OSC1)
An oscillator for generating the clock signal to be supplied to the CPU is mounted in the OSC1 socket.
With the V831, a PLL is used to generate a system clock. The frequency of the oscillator must be onethird the internal operating frequency of the V831. (A 33.33-MHz oscillator is mounted at the factory.)
The OSC1 socket accepts DIP 8-pin (half-type) oscillators.
[Caution] When you have to cut an oscillator pin for convenience, be careful not to cut it too short, or
otherwise the frame (housing) of the oscillator may touch a tine in the socket, resulting in a short-circuit
occurring.
5.8. 72-PIN-SIMM SOCKETS (SIMM#1, SIMM#2)
Each of the SIMM#1 and SIMM#2 sockets accepts an 8M-byte EDO type DRAM-SIMM; a total of 16M
bytes can be mounted. When mounting only one SIMM, use the SIMM#1 socket.
The evaluation board is factory-fitted with an EDO-type DRAM-SIMM (8M bytes), mounted in the
SIMM#1 socket. To install an additional SIMM in the SIMM#2 socket, use a SIMM of the same
specifications.
[Caution] Both the SIMM#1 and SIMM#2 sockets accept only 72-pin, 8M-byte EDO-type DRAM
SIMMs (for DOS/V). Never mount a SIMM of more than 8M bytes.
5.9. ROM SOCKETS
The RTE-V831-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128K bytes
(64K × 16 bits). When the ROM chips used here are to be replaced, their type should be 27C1024,
27C2048, or 27C4096, and the access time should be 150 ns or less. (JP1 and JP2 may need to be set
according to the type and purpose of the ROM chips to be used.)
5.10. ROM SIZE SWITCHING JUMPER (JP1)
Jumper JP1 must be set according to the size of the installed ROM. Leave the jumper open when a
ROM of 128K bytes (64K × 16 bits) or 256K bytes (128K × 16 bits) is mounted. Close the jumper when
a ROM of 512K bytes (256K × 16 bits) is mounted.
[Remark] Jumper JP1 is left open at the factory.
5.11. ROM DIVISION SWITCHING JUMPER (JP2)
Jumper JP2 is used to select between the two modes of a mounted 128K-byte ROM. In one mode, the
ROM is used as a contiguous 128K-byte area. In the second mode, the ROM is divided into two 64Kbyte areas.
The 128K-byte ROM contains two codes of the monitor as standard. The lower half of the 128K-byte
area contains one code (to be executed in the cacheable area), while the higher half contains the other
code (to be executed in the uncacheable area).
1-2 -3: At boot time, the ROM is viewed as a contiguous 128K-byte area.
The monitor is executed in the uncacheable area.
1- 2-3 : At boot time, only the lower 64K-byte area is visible.
The monitor is executed in the cacheable area.
[Remark] The factory-configured jumper setting depends on the monitor type. See Section 13.3.6. or
14.2.6.
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5.12. JP3, JP4, JP5
Use jumpers JP3, JP4, and JP5 as set at the factory.
JP3: Open
JP4: Closed
JP5: Closed
5.13. JUMPER FOR SWITCHING BETWEEN BASIC CLOCKS FOR USER TIMERS (JP6)
JP6 is used to select which of two clocks is to be supplied to the timers (CH#1, CH#2) that can be used
by applications.
1-2 : 2 MHz (factory-set)
3-4 : 4 MHz
5.14. SERIAL CONNECTOR (JSIO1, JSIO2)
The JSIO1 and JSIO2 connectors are used for the RS-232C interface that is controlled by the serial
controller (TL16C552A). JSIO1 is a 9-pin D-SUB RS-232C connector like that commonly used on the
PC/AT, while JSIO2 is a pin plug type connector with a pitch of 2.54 mm. All signals on both of these
connectors are converted to the RS-232C level. The figures and table below indicate the pin and signal
arrangements of these connectors.
For the signals to be connected to the host, the table indicates two modes of wiring on the host: one for
a 9-pin D-SUB connector, and the other for a 25-pin D-SUB connector. (Regular cross-cable wiring is
used for these connections.)
The pin arrangement of JSIO2 will be identical to that of JSIO1 when a push-fit connector is used with a
ribbon cable.
198765432
JSIO1 Pin Arrangement (Male)
1109876543
2
JSIO2 Pin Arrangement
Connector pin number on the host side
JSIO1
pin No.
JSIO2
pin No.
Signal name
Input/
output
D-SUB9 D-SUB25
1 1 DCD Input
2 3 RxD(RD) Input 3 2
3 5 TxD(SD) Output 2 3
4 7 DTR(DR) Output 1, 6 6, 8
5 9 GND 5 7
6 2 DSR(ER) Input 4 20
7 4 RTS(RS) Output 8 5
8 6 CTS(CS) Input 7 4
9 8 RI Input
-- 10 NC
JSIO1 and JSIO2 Connector Signals
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5.15. PARALLEL CONNECTOR (JPRT)
The JPRT connector is used for parallel communication controlled by the parallel (printer) controller
(TL16C552A). JPRT is a pin plug type connector with a 2.54 mm pitch. All signals on the connector are
5-V level signals. The figure and table below indicate the pin and signal arrangements of the connector.
The pin arrangement of JPRT will be identical to that of the 25-pin D-SUB connector, like that commonly
used on the PC/AT, when a push-fit connector is used with a ribbon cable.
1
2625242322212019181716151413121110
9876543
2
JPRT Pin Arrangement
JPRT pin No. Signal name JPRT pin No. Signal name
1 STB- 2 AUTO_FD3 D0 4 ERROR5 D1 6 INIT7 D2 8 SELECT_IN-
9 D3 10 GND
11 D4 12 GND
13 D5 14 GND
15 D6 16 GND
17 D7 18 GND
19 ACK- 20 GND
21 BUSY 22 GND
23 PE 24 GND
25 SELECT 26 NC
JPRT Connector Signals
5.16. AUDIO MINI-JACKS (JMIC-R, JMIC-L, JOUT)
Audio jacks are provided for two monaural microphone input channels and one stereo output channel.
The input/output conditions of these jacks are indicated below.
JMIC-R, JMIC-L
Electrical input condition
140 mVp-p (Internal amplification: About 20 dB)
Physical shape of mating plug
Monaural mini-plug (3.5 DIA.) × 2 channels
JOUT
Electrical output condition
1.4 Vp-p
Physical shape of mating plug
Stereo mini-plug (3.5 DIA.) × 1 channel
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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5.17. DEBUGGING CONNECTOR (JDBG)
The JDBG connector is used to connect a debug tool based on the debug function built into the V831.
On-board connector: 8930E-040-178MS manufactured by KEL
Pin No. Signal name Pin No. Signal name
A1 GND B1 GND
A2 CLKOUT B2 +3.3V
A3 GND B3 GND
A4 TRCDATA0 B4 GND
A5 GND B5 GND
A6 TRCDATA1 B6 GND
A7 GND B7 GND
A8 TRCDATA2 B8 GND
A9 GND B9 GND
A10 TRCDATA3 B10 GND
A11 GND B11 GND
A12 DDI B12 GND
A13 GND B13 GND
A14 DCK B14 GND
A15 GND B15 GND
A16 DMS B16 GND
A17 GND B17 GND
A18 DDO B18 GND
A19 GND B19 GND
A20 DRST- B20 GND
JDBG Connector Signals
5.18. EXTENSION BUS CONNECTOR (JEXT)
The JEXT connector is provided to enable memory or I/O extension. This connector is internally
connected to the local bus of the board. For detailed information about the bus specifications, see
Chapter 10.
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5.19. CPU CONNECTOR (JCPU-A, JCPU-B)
The CPU connector signals are connected directly to the V831. Many signals are used on the board.
So, be careful when extracting signals from the JCPU. The 3.3-V signal level is used.
Pin No. Signal name Pin No. Signal name
1 GND 2 D2
3 D3 4 D4
5 D5 6 D6
7 D7 8 D8
9 +3.3V 10 GND
11 D9 12 D10
13 D11 14 +3.3V
15 GND 16 D12
17 D13 18 D14
19 D15 20 D16
21 D17 22 D18
23 D19 24 D20
25 D21 26 +3.3V
27 GND 28 D22
29 D23 30 D24
31 +3.3V 32 GND
33 D25 34 D26
35 D27 36 D28
37 D29 38 D30
39 D31 40 +3.3V
41 GND 42 LLMWR43 LUMWR- 44 ULMWR45 UUMWR- 46 MRD47 TXD 48 RXD
49 GND 50 +3.3V
51 SI/PORT2 52 SO/PORT1
53 SCLK-/PORT0 54 +3.3V
55 NC. 56 JCX2(*1)
57 GND 58 Reserve
59 +3.3V 60 GND
61 +3.3V 62 RESET63 DRST- 64 NMI65 BT16B 66 GND
67 +3.3V 68 GND
69 DMACK0 70 DMAAK1
71 DMAAK2 72 DMAAK3
73 DMARQ0 74 DMARQ1
75 DMARQ2 76 DMARQ3
77 REFRQ- 78 INTP03
79 INTP02 80 +3.3V
JCPU-A Connector Signals
*1 JCX2 is a buffered signal.
RTE-V831-PC USER’S MANUAL (Rev. 2.00)
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Pin No. Signal name Pin No. Signal name
81 GND 82 INTP01
83 INP00 84 TCLR
85 TI 86 INTP13
87 INTP11 88 INTP12/TO11
89 INTP10/TO10 90 CS791 CS6- 92 +5V
93 GND 94 CS595 CS4- 96 CS397 +5V 98 GND
99 CS2- 100 CS1-
101 HLDAK- 102 HLDRQ103 READY- 104 BCYST105 IORD- 106 IOWR107 +5V 108 GND
109 A23 110 A22
111 DDO 112 DMS
113 DCK 114 DDI
115 TRCDATA3 116 TRCDATA2
117 TRCDATA1 118 TRCDATA0
119 CLKOUT 120 +5V
121 GND 122 A21
123 A20 124 A19
125 A18 126 A17
127 A16 128 A15
129 A14 130 A13
131 A12 132 +5V
133 GND 134 A11
135 A10 136 +5V
137 GND 138 A9
139 A8 140 A7
141 A6 142 A5
143 A4 144 A3
145 A2 146 +5V
147 GND 148 +5V
149 GND 150 A1
151 WE- 152 OE153 RAS- 154 UUCAS155 ULCAS- 156 LUCAS157 LLCAS- 158 D0
159 D1 160 +5V
JCPU-A Connector Signals
The connector used is the FX2-80P-1.27SV, manufactured by Hirose Electric Co., Ltd.
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6. CONNECTION WITH THE HOST PC
6.1. INSTALLATION ON THE ISA BUS
When the RTE-V831-PC is installed in the ISA bus slot of the PC, power (+5 V) is supplied from the ISA
bus to the board. In addition, the ISA bus can be used for communication with the debugger, so
programs are down-loaded at high speed.
The RTE-V831-PC can be installed in the ISA bus slot according to the following procedure.
<1> Set the I/O address of the PC using a DIP switch on the board. Be careful not to specify the
same I/O address as used for any other I/O unit. See Section 5.4. for switch setting.
<2> Turn off the power to the PC, open its housing, and check the ISA bus slot to be used. If the slot
is equipped with a rear panel, remove the rear panel.
<3> Insert the board into the ISA bus slot. Make sure that the board does not touch any adjacent
board. Fasten the rear panel of the board to the housing of the PC with screws.
<4> Turn on the power to the PC, and check that the POWER-LED on the board lights. If the LED
does not light, turn off the PC power immediately, and check the connection. If the system
does not start normally (for example, if an error occurs during installation of a device driver), it is
likely that the set I/O address is the same as one already in use. Check the I/O address of the
board by referring to the applicable manual of the PC or the board.
<5> When the system turns out to be normal, turn off the PC power again, and put back its housing.
6.2. STANDALONE USE OF THE BOARD
When the RTE-V831-PC is used as a standalone rather than being installed in the PC, it requires an
external power supply. In addition, communication with the debugger is supported by the RS-232C
interface.
The RTE-V831-PC can be used as a standalone according to the following procedure.
<1> Get an RS-232C cable for connection with the host and an external power supply (+5 V, 2 A) on
hand. Especially for the power supply, watch for its voltage and connector polarity. In addition,
attach spacers to the four corners of the board, so it will not pose any problem wherever it is
installed. See Sections 5.14. and 5.2. for RS-232C cable connection and the power supply
connector, respectively.
<2> Set the RS-232C baud rate using a DIP switch on the board. See Section 13.2.1. and 14.1.1. for
the switch settings for the Multi and PARTNER monitors, respectively.
<3> Connect the board to the host via an RS-232C cable. Also connect an external power supply to
the JPOWER jack, then check that the POWER-LED on the board lights. If the LED does not
light, turn off the power immediately, and check the connection.
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