How it Works
Midas
Loading...
RTE-V830-PC
User Manual
46 pgs272.82 Kb0

Midas RTE-V830-PC User Manual

RTE-V830-PC
User's Manual
Midas lab
RTE-V830-PC USER’ S MANUAL
1
REVISION HISTORY
9, 10
Correction of error in which SW1 was written as SW2 and vice versa Correction of error related to descriptions about SW1
(1-2 and 3-4) settings February 5, 1996 0.92 14 Correction of errors in tables in Sections 6.1 and 6.2 November 23, 1996 1.01e 16
21
Correction of errors in tables in Sections 6.2
(bit2-bit0 in port0 )
Correction of errors in tables in Sections 7
RTE-V830-PC USER’ S MANUAL
2
CONTENTS
1. INTRODUCTION ...............................................................................................................4
1.1. NUMERIC NOTATION..............................................................................................4
2. FEATURES AND FUNCTIONS..........................................................................................5
3. BOARD CONFIGURATION...............................................................................................6
3.1. RESET SWITCH (SWRESET)..................................................................................6
3.2. POWER SUPPLY CONNECTOR (JPOWER) ...........................................................6
3.3. SWITCH 1 (SW1)......................................................................................................6
3.4. SWITCH 2 (SW2)......................................................................................................7
3.5. LED...........................................................................................................................7
3.6. TEST PINS (TP)........................................................................................................7
3.7. SERIAL CONNECTOR (JSIO)...................................................................................8
3.8. CPU TEST PINS (J1)................................................................................................8
3.9. CLOCK SOCKET (OSC1) .........................................................................................8
3.10. DRAM-SIMM SOCKETS ...........................................................................................9
3.11. ROM SOCKETS........................................................................................................9
4. INSTALLATION AND USE.............................................................................................. 10
4.1. BOARD SETTING...................................................................................................10
4.2. INSTALLATION ON THE ISA BUS.......................................................................... 11
4.3. STANDALONE USE OF THE BOARD .................................................................... 12
5. HARDWARE REFERENCES........................................................................................... 13
5.1. MEMORY MAP .......................................................................................................13
5.2. I/O MAP ..................................................................................................................14
6. SYSTEM-I/O....................................................................................................................15
6.1. UART/TIMER (SCC2691)........................................................................................15
6.2. PIO (µPD71055)......................................................................................................15
6.3. OTHER PORTS ......................................................................................................19
7. JEXT BUS SPECIFICATION...........................................................................................21
8. OTHER CPU RESOURCES.............................................................................................23
8.1. RESET-...................................................................................................................23
8.2. NMI-........................................................................................................................23
9. MULTI MONITOR ............................................................................................................24
9.1. MONITOR WORK RAM..........................................................................................24
9.2. INTERRUPTS .........................................................................................................24
RTE-V830-PC USER’ S MANUAL
3
9.3. _INIT_SP SETTING ................................................................................................24
9.4. REMOTE CONNECTION........................................................................................24
10. RTE COMMANDS ........................................................................................................... 25
10.1. HELP (?) .................................................................................................................25
10.2. INIT.........................................................................................................................25
10.3. VER ........................................................................................................................ 25
10.4. INB, INH, AND INW ................................................................................................25
10.5. OUTB, OUTH, AND OUTW.....................................................................................26
10.6. DCTR COMMAND...................................................................................................26
10.7. ITCR COMMAND....................................................................................................26
10.8. PLLCR COMMAND.................................................................................................26
10.9. CMCR COMMAND ..................................................................................................26
11. APPENDIX DRAM TIMING............................................................................................27
11.1. DRAM INTERFACE OVERVIEW ............................................................................27
11.2. SIGNAL DESCRIPTIONS........................................................................................27
11.3. 32-BIT BUS MODE (SINGLE READ, NORMAL)...................................................... 28
11.4. 32-BIT BUS MODE (SINGLE READ, HIT)...............................................................29
11.5. 32-BIT BUS MODE (SINGLE READ, NOHIT).......................................................... 30
11.6. 32-BIT BUS MODE (SINGLE WRITE, NORMAL)....................................................31
11.7. 32-BIT BUS MODE (SINGLE WRITE, HIT)............................................................. 32
11.8. 32-BIT BUS MODE (SINGLE WRITE, NOHIT)........................................................33
11.9. 32-BIT BUS MODE (BURST READ, INTERLEAVE)................................................34
11.10. 32-BIT BUS MODE (BURST WRITE, INTERLEAVE)............................................ 35
11.11. 32-BIT BUS MODE (BURST READ, NONINTERLEAVE)......................................36
11.12. 32-BIT BUS MODE (BURST WRITE, NONINTERLEAVE) ....................................37
11.13. 16-BIT BUS MODE (SINGLE READ)..................................................................... 38
11.14. 16-BIT BUS MODE (SINGLE WRITE)...................................................................40
11.15. 16-BIT BUS MODE (BURST READ, INTERLEAVE)..............................................41
11.16. 16-BIT BUS MODE (BURST WRITE, INTERLEAVE)............................................ 42
11.17. 16-BIT BUS MODE (BURST READ, NONINTERLEAVE)......................................43
11.18. 16-BIT BUS MODE (BURST WRITE, NONINTERLEAVE) ....................................44
RTE-V830-PC USER’ S MANUAL
4
1. INTRODUCTION
This manual describes the RTE-V830-PC, which is an evaluation board for the V830, NEC's CPU. With the RTE-V830-PC, it is possible to develop and debug programs, and evaluate the CPU performance, using the GreenHills Multi debugger. Communication with this debugger is carried out using the IBM-PC/AT ISA bus or RS-232C serial interface. It is also possible to expand memory and I/O units using local bus connectors provided on the evaluation board.
1.1. NUMERIC NOTATION
This manual represents numbers according to the notation described in the following table. Hexadecimal and binary numbers are hyphenated at every four digits, if they are difficult to read because of many digits being in each number.
Number Notation rule Example
Decimal number
Only numerals are indicated. "10" represents number 10 in decimal.
Hexa­decimal number
A number is suffixed with letter H. "10H" represents number 16 in decimal.
Binary number
A number is suffixed with letter B. "10B" represents number 2 in decimal.
Number Notation Rules
RTE-V830-PC USER’ S MANUAL
5
2. FEATURES AND FUNCTIONS
The overview of each function block of the RTE-V830-PC is shown below.
V830
ISA Bus
Local Bus
ISA BUS I/F
JEXT
CONNECTOR
D-RAM
S-RAM
ROM
TIMER/SIO
Internal Control
RS-232C
CONNECTOR
PIO
USER
HW
RTE-V830-PC Block Diagram
Features
• ROM: 256 Kbytes (64K x 16-bit EPROM x 2)
• SRAM: 512 Kbytes (64K x 16-bit SRAM x 4)
• DRAM: 8, 16, or 32 Mbytes (standard of 8 Mbytes) installed in two 72-pin SIMM sockets
• RS-232C port (9-pin D-SUB connector)
• Communication function supported using the ISA bus of a PC/AT or compatible
• Local bus connector for user-installed expansion equipment
• Processor pin connector enabling measurement of all CPU signals
• External reset switch provided on the rear panel
• Connection pins for ROM in-circuit debugger
RTE-V830-PC USER’ S MANUAL
6
3. BOARD CONFIGURATION
The physical layout of the major components on the RTE-V830-PC board is shown below. This chapter explains each component.
RTE-V830-PC Board Top View
3.1. RESET SWITCH (SWRESET)
SWRESET is a reset switch. Pressing this switch causes the CPU to be reset.
3.2. POWER SUPPLY CONNECTOR (JPOWER)
When this board is to be used as a standalone, that is, without being inserted in an ISA bus slot, the board should be supplied with power from an external power supply by connecting it to the JPOWER connector. The external power should be one rated as listed below.
Voltage: 5 V Current: Maximum of 2 A (excluding the current supplied to the JEXT
connector) Mating connector: Type A (5.5 mm in diameter) Polarity:
GND
GND
+5V
+5V
[Caution] When attaching an external power supply to the board, be careful about its
connector polarity. When inserting the board into the ISA bus slot, do not attach the JPOWER connector to an external power supply.
3.3. SWITCH 1 (SW1)
SW1 is a switch for general-purpose input ports. When SW1 is in the OFF position, it represents 1. When it is in the ON position, it represents 0. See Section 6.2 for details.
SW2
SCC/
TIMER
SW RESET
JPOWER
JEXT
JSIO
PLD
PIO
SW1
PLD
PLD
PLD
PLD
ROM
(D16-31)
ROM
(D0-15)
RAMRAM
V830
J1(1-36)
J1(37-72)
J1(73-108)
J1(109-144)
TP
OSC1
1pin
SIM-72pin X 2
POWER
CS0
CS1
CS2
CS3
TOVER
RTE-V830-PC USER’ S MANUAL
7
3.4. SWITCH 2 (SW2)
SW2 is a switch for selecting the I/O address of the ISA bus. Switch contacts 1 to 8 corresponds to ISA addresses A4 to A11, respectively (A12 to A15 are fixed at 0). This means that the I/O address that can be selected ranges between 000xH and 0FFxH. When a switch contact is open, it corresponds to 1. When it is closed, it corresponds to 0.
SW2 contact
1 2 3 4 5 6 7 8
ISA address
A4 A5 A6 A7 A8 A9 A10 A11
SW2-to-ISA Address Correspondence
3.5. LED
The LEDs are used to indicate statuses, as listed below.
LED Description
POWER Lights when power is supplied to the RTE-V830-PC board.
CS0 Lights when the CS0 pin of the CPU is active (low). CS1 Lights when the CS1 pin of the CPU is active (low). CS2 Lights when the CS2 pin of the CPU is active (low). CS3 Lights when the CS3 pin of the CPU is active (low).
TOVER Lights when a time-out occurs.
LED Indication
3.6. TEST PINS (TP)
Test pins are used to connect a ROM in-circuit debugger. They accept control signals from the ROM in-circuit debugger. The following table lists the signal name and function related to each test pin.
Signal Input/
output
Function
RESET- Input When a low level is supplied to this test pin, the CPU is reset. A
reset request signal from the ROM in-circuit debugger is connected to the test pin. The test pin is pulled up with 1kΩ.
NMI- Input When a low level is supplied to this test pin, an NMI signal is given
to the CPU. This signal can be masked by software. An NMI request (break request) signal from the ROM in-circuit debugger is connected to the test pin. The test pin is pulled up with 1kΩ.
GND – – – This test pin is at a ground level. The ground level of the ROM
in-circuit debugger is connected to the test pin.
Test Pin Functions
RTE-V830-PC USER’ S MANUAL
8
3.7. SERIAL CONNECTOR (JSIO)
JSIO is a connector for the RS-232C interface controlled by the serial controller (SCC2691). It is a 9-pin D-SUB connector (D-SUB9) generally used with the PC/AT. All signals at this connector are at RS-232C level. Its pin arrangement and signal assignment are shown and listed below. For connection signals connected to the host computer, the table gives the wirings for both the D-SUB9 pins and D-SUB25 pins on the host side. (These are general cross-cable wirings.)
198765432
JSIO Pin Arrangement
Pin Signal name Input/
output
Connector pin number on
the host side
D-SUB9 D-SUB25
1 NC 2 RxD(RD) Input 3 2 3 TxD(SD) Output 2 3 4 DTR(DR) Output 1, 6 6, 8 5 GND 5 7 6 DSR(ER) Input 4 20 7 RTS(RS) Output 8 5 8 CTS(CS) Input 7 4 9 NC
JSIO Connector Signals
3.8. CPU TEST PINS (J1)
The CPU test pins are connected to the corresponding CPU pins. The test pin numbers correspond to the CPU pin numbers on a one-to-one basis. The test pins can be used to handle CPU signals for test purposes.
3.9. CLOCK SOCKET (OSC1)
The OSC1 socket is connected to an oscillator used to supply clock pulses to the CPU. The V830 uses a PLL for system clock generation. The SW1-7 setting specifies the frequency of the oscillator connected to the OSC1 socket. The frequency must be half or one-third the internal clock frequency. The oscillator connected to the OSC1 socket must be of an 8-pin DIP type (half type).
[Caution] When you have to cut an oscillator or crystal pin for convenience, be careful not to
cut it too short, or otherwise the frame (housing) of the oscillator or crystal may touch a tine in the socket, resulting in a short-circuit occurring.
RTE-V830-PC USER’ S MANUAL
9
3.10. DRAM-SIMM SOCKETS
The RTE-V830-PC has DRAM-SIMM sockets used to install two 4 Mbytes (standard) of SIMMs. Each socket can hold a 72-pin 4-, 8-, or 16-Mbyte SIMM (known as a module for DOS/V machines), so it is easy to expand the capacity of DRAM. Select SIMM chips that meet the access timing requirements listed in a table elsewhere. The selected SIMM chips must be of the same model. The capacity of installed SIMMs can be detected using a PIO port. (See Section 6.2.)
3.11. ROM SOCKETS
The RTE-V830-PC has ROM sockets to hold 40-pin ROM chips to provide standard 128 Kbytes (64K x 16 bits). When the ROM chips used here are to be replaced, the access time should be 150 ns or less.
RTE-V830-PC USER’ S MANUAL
10
4. INSTALLATION AND USE
The RTE-V830-PC board is designed to be installed in the ISA bus slot of a PC/AT or compatible (hereafter called the PC). However, it can also be used as a standalone, if it is powered from an external power supply. When the board is used for testing purposes or with the Multi debugger, communication software called RTE for Windows must be installed in the PC. Refer to the RTE for Windows Installation Manual for installation and test methods.
4.1. BOARD SETTING
The RTE-V830-PC board has DIP switches. The DIP switches can be used to set up the evaluation board. The switch layout is shown below.
Switches on the RTE-V830-PC Board
SW2 is a switch for selecting the I/O address of the ISA bus. Switch contacts 1 to 8 correspond to ISA addresses A4 to A11, respectively (A12 to A15 are fixed at 0). This means that the I/O address that can be selected ranges between 000xH and 0FFxH. When a switch contact is open, it corresponds to 1. When it is closed, it corresponds to 0. Generally, SW2 is set to any value between 20xH and 3FxH.
SW2
contact
1 2 3 4 5 6 7 8
Address A4 A5 A6 A7 A8 A9 A10 A11 I/O address
ON/
OFF
0 0 0 0 0
1
0 0 020xH
(factory-set)
SW2-to-ISA I/O Address Correspondence
SW1 is a switch for general-purpose input ports. For the Multi monitor in the factory-installed ROM, SW1 is used to set the RS-232C baud rate and profiler timer period.
SW1
contact
1 2 Baud rate
Setting ON
OFF
ON
OFF
ON
ON OFF OFF
Not used 38400 baud 19200 baud 9600 baud (factory-set)
Baud Rate Setting
SW2
SCC/
TIMER
SWRESET
JPOWER
JEXT
JSIO
PLD
PIO
SW1
PLD
PLD
PLD
PLD
ROM
(D16-31)
ROM
(D0-15)
RAMRAM
V830
J1(1-36)
J1(37-72)
J1(73-108)
J1(109-144)
TP
OSC1
1pin
SIM-72pin X 2
POWER
CS0
CS1
CS2
CS3
TOVER
RTE-V830-PC USER’ S MANUAL
11
SW1
contact
3 4 Profiler period
Setting ON
OFF
ON
OFF
ON
ON OFF OFF
Timer is not used. 200 Hz 5 ms 100 Hz 10 ms 60 Hz 16.67 ms (factory-set)
Profiler Period Setting
Contacts 5 and 6 of SW1 are not used for the Multi monitor (they are fixed at OFF).
SW1
contact
7 CMODE (V830 pin)
Setting ON
OFF
Triple mode Double mode
CMODE Setting
SW1
contact
8 SIZE16 (V830 pin)
Setting ON
OFF
32-bit mode 16-bit mode
SIZE16 Setting
4.2. INSTALLATION ON THE ISA BUS
When the RTE-V830-PC is installed in the ISA bus slot of the PC, power (+5V) is supplied from the ISA bus to the board. In addition, the ISA bus can be used for communication with the debugger, so programs are down-loaded at high speed. The RTE-V830-PC can be installed in the ISA bus slot according to the following procedure.
• Set the I/O address of the PC using a DIP switch on the board. Be careful not to specify the same I/O address as used for any other I/O unit. See Section 4.1 for switch setting.
‚ Turn off the power to the PC, open its housing, and confirm the ISA bus slot to be used. If
the slot is equipped with a rear panel, remove the rear panel.
ƒ Insert the board into the ISA bus slot. Make sure that the board does not touch any
adjacent board. Fasten the rear panel of the board to the housing of the PC with screws.
„ Turn on the power to the PC, and check that the POWER-LED on the board lights. If the
LED does not light, turn off the PC power immediately, and check the connection. If
the system does not start normally (for example, if an error occurs during installation of a device driver), it is likely that the set I/O address is the same as one already in use. Reconfirm the I/O address of the board by referring to the applicable manual of the PC or the board.
… When the system turns out to be normal, turn off the PC power again, and put back its
housing.
RTE-V830-PC USER’ S MANUAL
12
4.3. STANDALONE USE OF THE BOARD
When the RTE-V830-PC is used as a standalone rather than being installed in the PC, it requires an external power supply. In addition, communication with the debugger is supported only by the RS-232C interface. This configuration is useful when the host debugger used with the board is not one in the PC/AT or compatible as well as when the board is used for hardware confirmation and expansion. The RTE-V830-PC can be used as a standalone according to the following procedure.
• Get an RS-232C cable for connection with the host and an external power supply (+5 V, 1 A) on hand. Especially for the power supply, watch for its voltage and connector polarity. In addition, attach spacers to the four corners of the board, so it will not pose any problem wherever it is installed. See Sections 3.7 and 3.2 for RS-232C cable connection and the power supply connector, respectively.
‚ Set the RS-232C baud rate using a DIP switch on the board. See Section 4.1 for switch
setting.
ƒ Connect the board to the host via an RS-232C cable. Also connect an external power
supply to the JPOWER connector, then check that the POWER-LED on the board lights. If the LED does not light, turn off the power immediately, and check the connection.
RTE-V830-PC USER’ S MANUAL
13
5. HARDWARE REFERENCES
This chapter describes the hardware of the RTE-V830-PC.
5.1. MEMORY MAP
The memory assignment of the board is shown below.
0000-0000
4FFF-FFFF
8000-0000
4000-0000
7E00-0000
0000-0FFF
CS0 space
6000-0000
6010-0000
6020-0000
600F-FFFF
601F-FFFF
60FF-FFFF
80FF-FFFF
C000-0000
BFFF-FFFF
61FF-FFFF
6200-0000
6FFF-FFFF
XE80-0000
XE7F-FFFF
XE00-0000
XEFF-FFFF
XF00-0000
XFFB-FFFF
XFFC-0000
FE00-1000
XFFF-FFFF
FFFF-FFFF
Image of XE7F­0000 to XE00­0000
Image of XFFC-0000 to XFFF-FFFF
Access inhibited
CS1 space
CS2 space
CS3 space (*1)
DRAM
Reserved
SRAM
EXT-BUS
SYSTEM-I/O
ROM
0000-1000
0FFF-FFFF
2FFF-FFFF
2000-0000
3000-0000
Built-in data RAM
3FFF-FFFF
CS1 space
CS2 space
CS3 space
7000-0000
7DFF-FFFF
5FFF-FFFF
5000-0000
6000-0000
6FFF-FFFF
7FFF-FFFF
Access inhibited
Access inhibited
Access inhibited
FDFF-FFFF
FE00-0000
FE00-0FFF
CS0 space
Built-in instruction RAM
Cacheable area
Cacheable area
Un­cacheable
Cacheable area
6100-0000
Access inhibited
Reserved
X000-0000
XFFF-FFFF
X000-0000
X1FF-FFFF
X200-0000
XFFF-FFFF
Image of X000­0000 to X1FF­FFFF
*1 Access to the CS3 space at 3000-0000 to 3FFF-FFF is
inhibited.
Memory Map
DRAM spaces (0000-0000H to 01FF-FFFFH and 4000-0000H to 41FF-FFFFH)
These are spaces in 72-pin SIMM chips mounted on the RTE-V830-PC board. Two 4-Mbyte SIMM chips are used in a standard configuration. They can be replaced with 8- or 16-Mbyte SIMM chips for memory expansion. It is possible to specify RAS, CAS, and precharge widths. (See Section 6.2.)
Reserved and access-inhibited spaces
Do not attempt to access these spaces.
Loading...
+ 32 hidden pages
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use