Midas RTE-V821-PC User Manual
RTE-V821-PC
User's Manual
Midas lab
RTE-V821-PC USER’ S MANUAL
1
REVISION HISTORY
Date of
enforcement
Revision Page Description
August 11, 1995 1.0 First issue
December 25, 1995 1.1 11, 12 Correction of error related to descriptions about SW2
(1-2 and 3-4) settings
RTE-V821-PC USER’ S MANUAL
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CONTENTS
1. INTRODUCTION..........................................................................................................................4
1.1. NUMERIC NOTATION ........................................................................................................... 4
2. FEATURES AND FUNCTIONS.....................................................................................................5
3. BOARD CONFIGURATION..........................................................................................................6
3.1. RESET SWITCH (SWRESET)...............................................................................................6
3.2. POWER SUPPLY CONNECTOR (JPOWER).........................................................................6
3.3. SWITCH1 (SW1) ..................................................................................................................6
3.4. SWITCH2 (SW2) ..................................................................................................................7
3.5. LED ......................................................................................................................................7
3.6. TEST PINS (TP) .................................................................................................................... 7
3.7. SUBPORT (JSUBPORT).......................................................................................................7
3.8. SERIAL CONNECTOR (JSIO)...............................................................................................8
3.9. CPU TEST PINS (JCPU).......................................................................................................9
3.10. CLOCK SOCKET (OSC1)......................................................................................................9
3.11. DRAM-SIMM SOCKETS......................................................................................................10
3.12. ROM SOCKETS.................................................................................................................. 10
4. INSTALLATION AND USE.......................................................................................................... 11
4.1. BOARD SETTING............................................................................................................... 11
4.2. INSTALLATION ON THE ISA BUS.......................................................................................12
4.3. STANDALONE USE OF THE BOARD .................................................................................12
5. HARDWARE REFERENCES...................................................................................................... 13
5.1. MEMORY MAP....................................................................................................................13
5.2. I/O MAP..............................................................................................................................14
5.2.1. Port Unit (PORT)..........................................................................................................14
5.2.2. Wait Control Unit (WCU).............................................................................................. 14
5.2.3. DRAM Control Unit (DRAMC)....................................................................................... 15
5.2.4. ROM Controller (ROMC)...............................................................................................15
5.2.5. DMA Controller (DMAC)................................................................................................ 15
5.2.6. Realtime Pulse Unit (RPU) ...........................................................................................15
5.2.7. Serial Control Unit (SCU).............................................................................................. 15
5.2.8. Interrupt Control Unit (ICU)...........................................................................................16
5.2.9. Bus Arbitration Unit (BAU)............................................................................................ 16
5.2.10. Clock Generator (CG)............................................................................................... 16
5.2.11. Watchdog Timer Unit (WDT) ........................................................................................16
6. SYSTEM-I/O..............................................................................................................................17
6.1. UART/TIMER (SCC2691)....................................................................................................17
6.2. PIO (µPD71055)..................................................................................................................17
7. JEXT BUS SPECIFICATION.......................................................................................................19
8. OTHER CPU RESOURCES.......................................................................................................21
RTE-V821-PC USER’ S MANUAL
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8.1. RESET-...............................................................................................................................21
8.2. NMI-....................................................................................................................................21
9. Multi MONITOR .........................................................................................................................22
9.1. MONITOR WORK RAM ......................................................................................................22
9.2. INTERRUPTS..................................................................................................................... 22
9.3. _INIT_SP SETTING ............................................................................................................22
9.4. REMOTE CONNECTION.................................................................................................... 22
10. RTE COMMANDS......................................................................................................................23
10.1. HELP (?).............................................................................................................................23
10.2. INIT.....................................................................................................................................23
10.3. VER....................................................................................................................................23
10.4. INB, INH, AND INW.............................................................................................................23
10.5. OUTB, OUTH, AND OUTW................................................................................................. 24
10.6. SFR.................................................................................................................................... 24
11. APPENDIX.................................................................................................................................25
11.1. CPU PINS...........................................................................................................................25
RTE-V821-PC USER’ S MANUAL
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1. INTRODUCTION
This manual describes the RTE-V821-PC, which is an evaluation board for the V821, NEC's
CPU. With the RTE-V821-PC, it is possible to develop and debug programs, and evaluate the
CPU performance, using the GreenHills Multi debugger. Communication with this debugger is
carried out using the IBM-PC/AT ISA bus or RS-232C serial interface. It is also possible to
expand memory and I/O units using local bus connectors provided on the evaluation board.
1.1. NUMERIC NOTATION
This manual represents numbers according to the notation described in the following table.
Hexadecimal and binary numbers are hyphenated at every four digits, if they are difficult to read
because of many digits being in each number.
Number Notation rule Example
Decimal
number
Only numerals are indicated. "10" represents number 10 in decimal.
Hexadecimal
number
A number is suffixed with letter H. "10H" represents number 16 in decimal.
Binary
number
A number is suffixed with letter B. "10B" represents number 2 in decimal.
Number Notation Rules
RTE-V821-PC USER’ S MANUAL
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2. FEATURES AND FUNCTIONS
The overview of each function block of the RTE-V821-PC is shown below.
V82
1
JSUBPOR
T
CONNECTOR
ISA Bus
Local Bus
ISA BUS I/F
JEX
T
CONNECTOR
D-RAMS-RAMROM
TIMER/SIO
Interna
l
Control
RS-232C
CONNECTOR
PIO
USER
HW
RTE-V821-PC Block Diagram
Features
• ROM: 128 Kbytes (64K x 16 bits)
• SRAM: 128 Kbytes (64K x 16 bits)
• DRAM: 4, 8, or 16 Mbytes (standard of 4 Mbytes) installed in a 72-pin SIMM socket
• RS-232C port (9-pin D-SUB connector)
• Communication function supported using the ISA bus of a PC/AT or compatible
• Local bus connector for user-installed expansion equipment
• Connector which outputs synchronous serial signals of the CPU and some port signals
• Processor pin connector enabling measurement of all CPU signals
• External reset switch provided on the rear panel
• Connection pins for ROM in-circuit debugger
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3. BOARD CONFIGURATION
The physical layout of the major components on the RTE-V821-PC board is shown below. This
chapter explains each component.
RTE-V821-PC Board Top View
3.1. RESET SWITCH (SWRESET)
SWRESET is a reset switch. Pressing this switch causes the CPU to be reset.
3.2. POWER SUPPLY CONNECTOR (JPOWER)
When this board is to be used as a standalone, that is, without being inserted in an ISA bus slot,
the board should be supplied with power from an external power supply by connecting it to the
JPOWER connector.
The external power should be one rated as listed below.
Voltage: 5 V
Current: Maximum of 1 A (excluding the current supplied to the JEXT connector)
Mating connector: Type A (5.5 mm in diameter)
Polarity:
GND
GND
+5V
+5V
[Caution] When attaching an external power supply to the board, be careful about its
connector polarity. When inserting the board into the ISA bus slot, do not attach the JPOWER
connector to an external power supply.
3.3. SWITCH1 (SW1)
SW1 is a switch for selecting the I/O address of the ISA bus. Switch contacts 1 to 8
corresponds to ISA addresses A4 to A11, respectively (A12 to A15 are fixed at 0). This means
that the I/O address that can be selected ranges between 000xH and 0FFxH. When a switch
contact is open, it corresponds to 1. When it is closed, it corresponds to 0.
SW1
contact
1 2 3 4 5 6 7 8
Address A4 A5 A6 A7 A8 A9 A10 A11
SW1-to-ISA Address Correspondence
SW2
POWER
CS0
CS1
CS2
CS3
TOVER
P06
P07
SCC/
TIMER
LED TP
DRAM SIMM
JCPU
SWRESET
JPOWER
JEXT
V821
JSIO
JSUBPORT
SRAM
SW1
ROM
PLD
PLD
NMI-
RD_WRALL-
RESET-
GND
PIO
OSC1
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3.4. SWITCH2 (SW2)
SW2 is a switch for general-purpose input ports. When a switch contact is open, it
corresponds to 1. When it is closed, it corresponds to 0. See Section 6.1.2 for details.
3.5. LED
The LEDs are used to indicate statuses, as listed below.
LED Description
CS0 Lights when the CS0 pin of the CPU is active (low).
CS1 Lights when the CS1 pin of the CPU is active (low).
CS2 Lights when the CS2 pin of the CPU is active (low).
CS3 Lights when the CS3 pin of the CPU is active (low).
TOVER Lights when a time-out occurs.
P06 PIO: PORT0-6
P07 PIO: PORT0-7
LED Indication
3.6. TEST PINS (TP)
Test pins are used to connect a ROM in-circuit debugger. Some of them accept control
signals from the ROM in-circuit debugger, and the others output trace timing signals. The
following table lists the signal name and function related to each test pin.
Signal Input/
output
Function
RESET- Input When a low level is supplied to this test pin, the CPU is reset. A
reset request signal from the ROM in-circuit debugger is
connected to the test pin. The test pin is pulled up with 1kΩ.
NMI- Input When a low level is supplied to this test pin, an NMI signal is
given to the CPU. This signal can be masked by software. An
NMI request (break request) signal from the ROM in-circuit
debugger is connected to the test pin. The test pin is pulled up
with 1kΩ.
RD_WR_ALL- Output This signal is obtained by ORing (negative logic) the CPU's
UMWR-, LMWR-, MRD-, IOWR-, and IORD- signals. It is used
as a trace timing signal by the ROM in-circuit debugger.
GND ------- This test pin is at a ground level. The ground level of the ROM
in-circuit debugger is connected to the test pin.
Test Pin Functions
3.7. SUBPORT (JSUBPORT)
The JSUBPORT connector makes some CPU pins accessible to the outside. Its pin
arrangement is shown below. The pins of the JSUBPORT connector are defined in the
following table.
213456782019181716151413121110
9
JSUBPORT Pin Arrangement
RTE-V821-PC USER’ S MANUAL
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Number Signal Description
1,3,5,7,9,
11,13,15
GND
2 SCLK-/P07 Connected directly to the CPU and pulled up with 47 kΩ.
4 SI/P05 Connected directly to the CPU and pulled up with 47 kΩ.
6 SO/P06 Connected directly to the CPU and pulled up with 47 kΩ.
8 INTP00-/TO00 Connected directly to the CPU and pulled up with 10 kΩ.
10 INTP02-/TO01 Connected directly to the CPU and pulled up with 10 kΩ.
12 TCLR/P00 Connected directly to the CPU and pulled down with 47 kΩ.
14 INTP13-/TI Connected directly to the CPU and pulled up with 10 kΩ.
16 DREQ0/P01 Connected directly to the CPU and pulled up with 47 kΩ.
17 DACK0-/P02 Connected directly to the CPU and pulled up with 47 kΩ.
18 DREQ1/P03 Connected directly to the CPU and pulled up with 47 kΩ.
19 DACK1-/P04 Connected directly to the CPU and pulled up with 47 kΩ.
20 NC Not connected
JSUBPORT Connector Signals
3.8. SERIAL CONNECTOR (JSIO)
JSIO is a connector for the RS-232C interface controlled by the serial controller (SCC2691). It
is a 9-pin D-SUB connector (D-SUB9) generally used with the PC/AT. All signals at this
connector are at RS-232C level. Its pin arrangement and signal assignment are shown and
listed below.
For connection signals connected to the host computer, the table gives the wirings for both the
D-SUB9 pins and D-SUB25 pins on the host side. (These are general cross-cable wirings.)
198765432
JSIO Pin Arrangement
JSIO pin Signal name Input/
output
Connector pin number on
the host side
D-SUB9 D-SUB25
1 NC
2 RxD(RD) Input 3 2
3 TxD(SD) Output 2 3
4 DTR(DR) Output 1, 6 6, 8
5 GND 5 7
6 DSR(ER) Input 4 20
7 RTS(RS) Output 8 5
8 CTS(CS) Input 7 4
9 NC
JSIO Connector Signals
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