Microtronix
4045 Meadowbrook Drive, Unit 126
London, ON Canada N6L 1E31
www.microtronix.com
Camera Link Transmitter
HSMC Daughter Card
U
SER MANUAL
EVISION
R
1.0
Document
How to Contact
Revision History
Microtronix
This User Manual provides basic information about using the
Microtronix Camera Link Tranmitter HSMC Daughter Card, PN:
6287-01-01. The following table shows the document revision history.
Date Description
September 2012 Initial release – Version 1.0
E-mail
Sales Information: sales@microtronix.com
Support Information: support@microtronix.com
Website
General Website: http://www.microtronix.com
Downloads: http://www.microtronix.com/downloads/
Support FTP site: http://microtronix.leapfile.com
Phone Numbers
General: (001) 519-690-0091
Fax: (001) 519-690-0092
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Camera Link Transmitter HSMC Daughter Card User Manual
Table of Contents
Document Revision History.............................................................................................................. 2
How to Contact Microtronix.............................................................................................................. 2
E-mail ........................................................................................................................................... 2
Website......................................................................................................................................... 2
Phone Numbers ........................................................................................................................... 2
Card Features .................................................................................................................................. 4
Introduction ...................................................................................................................................... 5
Kit Contents .................................................................................................................................. 5
Related Documentation ................................................................................................................ 5
FPGA Host Board Compatibility ................................................................................................... 5
Hardware Description ...................................................................................................................... 6
Camera Link Connector ............................................................................................................... 6
HSMC to Camera Link Connector Mapping ............................................................................. 9
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Camera Link Transmitter HSMC Daughter Card User Manual
Card
Features
• Dual Camera Link Transmitter connectors
• Supports single Base, single Medium or single Full
• HSMC Type II or III differential LVDS interface
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Camera Link Transmitter HSMC Daughter Card User Manual
Introdu
ction
The Microtronix Camera Link Transmitter HSMC Daughter Card is
designed for building base, medium and full Camera Link transmitter
(Camera) interfaces. The card interfaces to Altera FPGA based
development boards using differential LVDS signals per a Type II or III
HSMC connector interface.
Two Camera Link (CL) connectors are provided which enables the card
to support one Base, one Medium or one Full Camera Link
configuration.
Kit Contents
The Microtronix Camera Link Transmitter HSMC Daughter Card is
supplied with the following components:
• Microtronix Camera Link Transmitter HSMC Daughter Card
• Mounting Hardware
• CD containing user documentation and board schematics
Related Documentation
The user may also want to refer to other Microtronix information
including:
• User Manuals for:
o Camera Link IP Core Design Kit
o Camera Link IP Core
• Altera High Speed Mezzanine Card (HSMC) Specification
FPGA Host Board Compatibility
The card interfaces to Altera FPGA based development boards using
differential LVDS signals which requires the use of a Type II or III
HSMC connector interface. Microtronix has tested Camera Link
Tranmitter board on the boards listed below.
• Microtronix boards:
o ViClaro III Video Host board
o ViClaro IV Video Host board
• Altera boards:
o Cyclone III (EP3C120) FPGA Development board
o Cyclone IV (EP4CGX150) FPGA Development board
NOTE: The Camera Link board may operate on other platforms.
However, the user should verify the availability of differential
LVDS signals, LVDS 100Ω resistor terminations and
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Camera Link Transmitter HSMC Daughter Card User Manual
Hardware
differential clock inputs capable of being routed to a PLL
within the FPGA.
The Microtronix Camera Link Tranmitter HSMC Daughter Card (PN:
Description
6287-01-01) is shown in Figure 1 below. It provides two Camera Link
MDR-26 female connectors (3M – 14B26-SZLB-X00-OLC). The card
can be configured to signal PoCL compatibility to frame grabbers that
support PoCL(Refer to notes on the Camera Link board schematics
S6287 for more information). The 26-pin CL connector pinout is shown
in Table 1 below.
Figure 1: Camera Link Transmitter HSMC Daughter Card
Camera Link Connector
The 26-pin Camera Link connectors are compliant with the Camera
Link standard. The connector assignments are shown in the tables
below. Connector J1 (the connector on left) supports a Base interface
and connector J2 (on the right) by default supports medium or full
configuration.
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Camera Link Transmitter HSMC Daughter Card User Manual
Table 1: Camera Link Camera J1 Base Connector Pinout
Board Signal Name Pin CL Signal Type Description
12VDC 1 12VDC Power Power PoCL Power
GND 14 Power Return Ground PoCL Power
FG0_n0 2 X0- LVDS Out CL X Channel Tx
FG0_p0 15 X0+ LVDS Out CL X Channel Tx
FG0_n1 3 X1- LVDS Out CL X Channel Tx
FG0_p1 16 X1+ LVDS Out CL X Channel Tx
FG0_n2 4 X2- LVDS Out CL X Channel Tx
FG0_p2 17 X2+ LVDS Out CL X Channel Tx
FG0_n3_clk 5 XClk- LVDS Out CL X Channel Tx Clock
FG0_p3_clk 18 XClk+ LVDS Out CL X Channel Tx Clock
FG0_n4 6 X3- LVDS Out CL X Channel Tx
FG0_p4 19 X3+ LVDS Out CL X Channel Tx
FG0_n5 20 SerTC+ LVDS In Serial Data Transmitter
FG0_p5 7 SerTC- LVDS In Serial Data Transmitter
FG0_n6 8 SerTFG- LVDS Out Serial Data Receiver
FG0_p6 21 SerTFC+ LVDS Out Serial Data Receiver
FG0_n7 9 CC1- LVDS In User Selectable Input
FG0_p7 22 CC1+ LVDS In User Selectable Input
FG0_n8 23 CC2+ LVDS In User Selectable Input
FG0_p8 10 CC2- LVDS In User Selectable Input
FG0_n9 11 CC3 - LVDS In User Selectable Input
FG0_p9 24 CC3+ LVDS In User Selectable Input
FG0_p10 12 CC4+ LVDS In User Selectable Input
FG0_n10 25 CC4- LVDS In User Selectable Input
GND 13 Power Return Ground PoCl Power
12VDC 26 12VDC Power Power PoCL Power
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Camera Link Transmitter HSMC Daughter Card User Manual
Table 2: Camera Link Camera J2 Medium & Full Connector Pinout
Cable Pin CL Signal Type Description
12VDC 1 12VDC Power Power PoCL Power
GND 14 Power Return Ground PoCL Power
FG1_n0 2 Y0- LVDS Out CL Y Channel Tx
FG1_p0 15 Y0+ LVDS Out CL Y Channel Tx
FG1_n1 3 Y1- LVDS Out CL Y Channel Tx
FG1_p1 16 Y1+ LVDS Out CL Y Channel Tx
FG1_n2 4 Y2- LVDS Out CL Y Channel Tx
FG1_p2 17 Y2+ LVDS Out CL Y Channel Tx
FG1_n3_clk 5 YClk- LVDS Out CL Y Channel Tx Clock
FG1_p3_clk 18 YClk+ LVDS Out CL Y Channel Tx Clock
FG1_n4 6 Y3- LVDS Out CL Y Channel Tx
FG1_p4 19 Y3+ LVDS Out CL Y Channel Tx
FG1_n5 7 100 Ω LVDS In
FG1_p5 20 TERMINATED LVDS In
FG1_n6 8 Z0- LVDS Out CL Z Channel Tx
FG1_p6 21 Z0+ LVDS Out CL Z Channel Tx
FG1_n7 9 Z1- LVDS Out CL Z Channel Tx
FG1_p7 22 Z1+ LVDS Out CL Z Channel Tx
FG1_n8 10 Z2- LVDS Out CL Z Channel Tx
FG1_p8 23 Z2+ LVDS Out CL Z Channel Tx
FG1_n9_clk 11 Zclk- LVDS Out CL Z Channel Tx Clock
FG1_p9_clk 24 Zclk+ LVDS Out CL Z Channel Tx Clock
FG1_n10 12 Z3- LVDS Out CL Z Channel Tx
FG1_p10 25 Z3+ LVDS Out CL Z Channel Tx
GND 13 Power Return Ground PoCl Power
12VDC 26 12VDC Power Power PoCL Power
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Camera Link Transmitter HSMC Daughter Card User Manual
HSMC to Camera Link Connector Mapping
Table 3 below shows the pinout of the HSMC connector, along with the
FPGA pin connections when the Camera Link Transmitter HSMC
Daughter Card is used on header J4 of the Microtronix ViClaro III Host
Video board and J3 on the Microtronx ViClaro IV Host board.
Table 3: Camera Link Connector (Base) Pinout
ViClaro IV ViClaro III HSMC Camera Link Board CL Interface
Signal
Cyclone IV
Pin #
J3 Board
Signal
Cyclone III Pin # J4 Board
Signal
-
- -
Pin Signal Name J2 Pin
12VDC
1
12VDC Power
- - - GND 14 Power Return
R29 HSMC3_TXn0 Y7 LVDS_n33 49 FG0_n0 2 X0-
T28 HSMC3_TXp0 W8 LVDS_p33 47 FG0_p0 15 X0+
P28 HSMC3_TXn1 V7 LVDS_n31 55 FG0_n1 3 X1-
P27 HSMC3_TXp1 V8 LVDS_p31 53 FG0_p1 16 X1+
R26 HSMC3_TXn2 V5 LVDS_n29 61 FG0_n2 4 X2-
R25 HSMC3_TXp2 V6 LVDS_p29 59 FG0_p2 17 X2+
T27 HSMC3_TXn3 U5 LVDS_n27 67 FG0_n3 5 XClk-
T26 HSMC3_TXp3 U6 LVDS_p27 65 FG0_p3 18 XClk+
T24 HSMC3_TXn4 R6 LVDS_n25 73 FG0_n4 6 X3-
T23 HSMC3_TXp4 R7 LVDS_p25 71 FG0_p4 19 X3+
N30 HSMC3_RXn0
N29 HSMC3_RXp0
W1 LVDS_n36 50 FG0_n5 20 SerTC+
W2 LVDS_p36 48 FG0_p5 7 SerTC-
T21 HSMC3_TXn5 M7 LVDS_n23 79 FG0_n6 8 SerTFG-
U21 HSMC3_TXp5 M8 LVDS_p23 77 FG0_p6 21 SerTFC+
P30 HSMC3_RXn2
R30 HSMC3_RXp2
R28 HSMC3_RXn3
R27 HSMC3_RXp3
W26 HSMC3_RXn4
W25 HSMC3_RXp4
U28 HSMC3_RXn5
U27 HSMC3_RXp5
- - - GND 13 Power Return
- - - 12VDC 26 12VDC Power
V3 LVDS_n32 62 FG0_n7 9 CC1-
V4 LVDS_p32 60 FG0_p7 22 CC1+
V1 LVDS_n30 68 FG0_n8 23 CC2+
V2 LVDS_p30 66 FG0_p8 10 CC2-
U1 LVDS_n28 74 FG0_n9 11 CC3 -
U2 LVDS_p28 72 FG0_p9 24 CC3+
U4 LVDS_n26 80 FG0_p10 12 CC4+
U3 LVDS_p26 78 FG0_n10 25 CC4-
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Camera Link Transmitter HSMC Daughter Card User Manual
Table 4: Camera Link Connector (Medium & Full) Pinout
Cyclone IV
Pin #
ViClaro IV ViClaro III HSMC
J3 Board Signal
Cyclone III
Pin #
J4 Board Signal Pin Board Signal J3 Pin
Camera Link
CL Interface
1 12VDC Power
14 Power Return
Y22 HSMC3_TXn8 M3 LVDS_n17 103 FG1_n0 2 Y0-
AA22 HSMC3_TXp8 L1 LVDS_p17 101 FG1_p0 15 Y0+
Y27 HSMC3_TXn9 P1 LVDS_n15 109 FG1_n1 3 Y1-
AA27 HSMC3_TXp9 P2 LVDS_p15 107 FG1_p1 16 Y1+
AB28 HSMC3_TXn10 N3 LVDS_n13 115 FG1_n2 4 Y2-
AB27 HSMC3_TXp10 N4 LVDS_p13 113 FG1_p2 17 Y2+
AA25 HSMC3_TXn11 L6 LVDS_n11 121 FG1_n3 5 YClk-
AB25 HSMC3_TXp11 L7 LVDS_p11 119 FG1_p3 18 YClk+
AB26 HSMC3_TXn12 J5 LVDS_n9 127 FG1_n4 6 Y3-
AC25 HSMC3_TXp12 J6 LVDS_p9 125 FG1_p4 19 Y3+
Y28 HSMC3_RXn8 L3 LVDS_n18 104 FG1_n5 7 100 Ω
Signal
AA28 HSMC3_RXp8 L4 LVDS_p18 102 FG1_p5 20 TERMINATED
AD28 HSMC3_TXn13 M1 LVDS_n7 133 FG1_n6 8 Z0-
AD27 HSMC3_TXp13 M2 LVDS_p7 131 FG1_p6 21 Z0+
AE28 HSMC3_TXn14 G5 LVDS_n5 139 FG1_n7 9 Z1-
AE27 HSMC3_TXp14 G6 LVDS_p5 137 FG1_p7 22 Z1+
AE26 HSMC3_TXn15 G3 LVDS_n3 145 FG1_n8 10 Z2-
AE25 HSMC3_TXp15 G4 LVDS_p3 143 FG1_p8 23 Z2+
AG29 HSMC3_TX_CLKn1
AH29 HSMC3_TX_CLKp1
C2 LVDS_n0 157 FG1_n9 11 Zclk-
D3 LVDS_p0 155 FG1_p9 24 Zclk+
AF28 HSMC3_TXn16 D1 LVDS_n1 151 FG1_n10 12 Z3-
AF27 HSMC3_TXp16 D2 LVDS_p1 149 FG1_p10 25 Z3+
13 Power Return
26 12VDC Power
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