Microsemi VSC8584 User Manual
VSC8584
User Guide
VSC8584 Evaluation Board
January 2014
VSC8584 Evaluation Board
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 1.0 ........................................................................................................................................ 1
2 Introduction ................................................................................................................................... 2
3 General Description ....................................................................................................................... 3
3.1 Key Features ....................................................................................................................................... 3
3.1.1 Copper Port RJ45 Connections ................................................................................................................ 3
3.1.2 SGMII/QSGMII MAC SMA ........................................................................................................................ 3
3.1.3 Switch Block Control ................................................................................................................................ 3
3.1.4 Zarlink ZL30343 SyncE G.8262/SETS ........................................................................................................ 3
3.1.5 External 1588 Clock Option ..................................................................................................................... 4
3.1.6 External RefClk Option ............................................................................................................................ 4
3.1.7 1588 Daisy-Chain SPI Time-Stamping Connection .................................................................................. 4
3.1.8 Network Interface Microcontroller Card ................................................................................................. 5
4 Quick Start ..................................................................................................................................... 6
4.1 Connecting the Power Supply ............................................................................................................ 6
4.2 PC Software Installation ..................................................................................................................... 6
4.3 Connecting to the Board to the PC ..................................................................................................... 6
4.3.1 Changing the IP Address of the Board ..................................................................................................... 6
4.4 Using the Control Software ................................................................................................................ 7
4.4.1 CAT5 to SGMII with Clause 37 AutoNeg Enabled .................................................................................... 7
4.4.2 Board Initialization and Running PGY Scripts .......................................................................................... 8
4.4.3 Copper Media Operation (1000BASE-T) .................................................................................................. 9
4.4.4 Fiber Media Operation (1000BASE-X) ................................................................................................... 10
4.4.5 Fiber Media Operation (100BASE-FX) ................................................................................................... 10
4.5 Useful Registers ................................................................................................................................ 10
4.5.1 Ethernet Packet Generator ................................................................................................................... 10
4.5.2 Copper PHY Error Counters ................................................................................................................... 10
4.5.3 Fiber PHY Error Counters ....................................................................................................................... 10
4.5.4 Configuring 1588 Daisy-Chain SPI Time-Stamping ................................................................................ 11
5 Additional Information ................................................................................................................ 12
VPPD-03500 VSC8584 User Guide Revision 1.0
VSC8584 Evaluation Board
1 Revision History
The revision history describes the changes that were implemented in this document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 1.0
Revision 1.0 of this datasheet was published in January 2014. This was the first publication of the
document.
VPPD-03500 VSC8584 User Guide Revision 1.0 1
VSC8584 Evaluation Board
2 Introduction
The VSC8584 device is a low-power, quad-port Gigabit Ethernet transceiver with four SerDes interfaces
for quad-port dual media capability. It also includes an integrated quad port I2C multiplexer (MUX) to
control SFPs or PoE modules. The VSC8584 supports IEEE 802.1AE 128/256-bit MACsec protocols to
meet the security requirements for protecting data traversing Ethernet LANs, and also includes Vitesse’s
patent-pending distributed timing technology VeriTime™ that delivers the industry’s most accurate IEEE
1588v2 timing implementation. The VSC8584 device offers a seamless integration between IEEE 1588v2
and the MACsec engine with no loss of precision. The VSC8584 also supports a ring resiliency feature
that allows a 1000BASE-T connected PHY port to switch between master and slave timing without
having to interrupt the 1000BASE-T link.
This document describes the architecture and usage of the VSC8584 Evaluation Board (VSC8584EV). The
VSC8584EV may be used to evaluate a family of devices which include VSC8584. These devices vary with
respect to the number of ports, supported interfaces, and available features. This document specifically
addresses the VSC8584 device. section describes how to bring-up the evaluation board The Quick Start
along with install and run the graphical user interface (GUI), used to control the evaluation board.
Figure 1 • VSC8584EV Evaluation Board
The following reference documents provide additional information about the operation of the VSC8584
evaluation board.
VSC8564 Datasheet ( )https://www.vitesse.com/products/product.php?number=VSC8564
VSC8582 Datasheet ( )https://www.vitesse.com/products/product.php?number=VSC8582
VSC8575 Datasheet ( )https://www.vitesse.com/products/product.php?number=VSC8575
VSC8584 Datasheet ( )https://www.vitesse.com/products/product.php?number=VSC8584
IEEE1588v2 and SyncE – Applications and Operation Using Vitesse’s Synchronization Solution
( )http://www.vitesse.com/products/download.php?fid=4767&number=VSC8574
VSC8584 GUI ( )https://www.vitesse.com/products/product.php?number=VSC8584
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VSC8584 Evaluation Board
3 General Description
The evaluation board in Figure 1 provides the user a way to evaluate the VSC8584 device in multiple
configurations. Four RJ-45 connectors are provided for copper media interfaces. The four SFP cages
allow for evaluation of the fiber media interconnects. The MAC interface is provided via SMA
connectors.
For access to all of the features of the device, an external microcontroller is used to configure the onboard clock chip via a two-wire serial bus and the VSC8584 via the MDIO bus. The graphical user
interface (GUI) enables the user to access the registers.
The evaluation board uses a Zarlink device to synthesize a 125 MHz reference clock signal from a 20
MHz crystal which serves as the REFCLK input.
3.1 Key Features
3.1.1 Copper Port RJ45 Connections
PHY Ports 2 and 3 use UDE RTA 1648BAK1A with integrated magnetic while PHY Ports 0 and 1 use
generic RJ45 connectors with discrete Pulse H5008 magnetics.
3.1.2 SGMII/QSGMII MAC SMA
SGMII SMA connections are provided for all PHYs while the QSGMII SMA connection is available only on
PHY0.
3.1.3 Switch Block Control
Set the SW1 switch as shown in the figure below.
Figure 2 • SW1 Switch Control
3.1.4 Zarlink ZL30343 SyncE G.8262/SETS
The Zarlink ZL30343 is initialized by default to provide a 125 MHz differential LVPECL clock to VSC8584
REFCLK inputs. (Note: the ZL30343 can be programmed to provide LVDS differential clock in conjunction
with an LVDS termination provided for REFCLK, please refer to the Zarlink manual for programming its
output drive).
Also, the ZL30343 can support synchronization with the VSC8584 PHY recovered clock for SyncE
operation. The ZL30343 is initialized to lock a recovered clock output if one is enabled and available
from the VSC8584 PHY. If no recovered clock signal is available, then the ZL30343 will select the crystal
oscillator (U16) as default reference source for holdover operation. ZL30343 will indicate locked versus
holdover status by driving LED D33 or D34. See the Zarlink documentation for more discussion
concerning its operation. See the VSC8584 datasheet for configuring recovered clock output pin
behavior.
Please ensure three-way resistive connections R19 and R22 are appropriately connected to feedback the
VSC8584’s recovered clock outputs into the ZL30343 device, if synchronization to a recovered clock
source is desired.
VPPD-03500 VSC8584 User Guide Revision 1.0 3
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