Microsemi VSC8489, VSC8490, VSC8491 User Manual
VSC8489/VSC8490/VSC8491
User Guide
VSC8489/VSC8490/VSC8491 Evaluation Board
June 2014
VSC8489/VSC8490/VSC8491 Evaluation Board
Contents
1 Revision History ............................................................................................................................. 1
1.1 Revision 1.0 ........................................................................................................................................ 1
2 Introduction ................................................................................................................................... 2
2.1 References .......................................................................................................................................... 2
2.2 General Description ............................................................................................................................ 2
3 Quick Start ..................................................................................................................................... 4
4 Hardware Options .......................................................................................................................... 5
4.1 Power Supply Options ........................................................................................................................ 5
4.2 Reference Clock Options .................................................................................................................... 5
5 Software ......................................................................................................................................... 6
5.1 USBXpress® Driver Installation ........................................................................................................... 6
5.2 GUI Setup ............................................................................................................................................ 6
5.3 Main Page ........................................................................................................................................... 7
5.4 FPGA ................................................................................................................................................... 8
5.5 Clocking Configuration ....................................................................................................................... 9
5.6 Routing ............................................................................................................................................. 10
5.7 BIST ................................................................................................................................................... 11
5.8 SFP+ .................................................................................................................................................. 13
5.9 Register List ...................................................................................................................................... 14
5.10 Vitesse Command Line Interface .................................................................................................... 15
6 Usage Examples ........................................................................................................................... 17
6.1 Packet BIST ....................................................................................................................................... 17
6.2 Packet BIST Part 2 ............................................................................................................................. 17
6.3 IEEE 1588 .......................................................................................................................................... 17
7 GPIO Pins ...................................................................................................................................... 18
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VSC8489/VSC8490/VSC8491 Evaluation Board
1 Revision History
The revision history describes the changes that were implemented in this document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 1.0
Revision 1.0 of this datasheet was published in June 2014. This was the first publication of the
document.
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2 Introduction
The VSC8489, VSC8490, and VSC8491 family of devices are dual and single channel (R)XAUI to SFI PHYs.
They support the standard 10.3125 Gbps Ethernet LAN mode per as well as the 9.95328 IEEE802.ae
Gbps WIS mode from IEEE 802.3ae Clause 50. In addition, the family supports IEEE 802.3ap and 1.25
Gbps rates as well. Certain device variants support the IEEE 1588v2 protocol and/or MACsec protocol.
One of the goals of the VSC8489/8490/8491 evaluation board (EVB) is to enable the user to observe the
signal quality of the SFI I/Os through SMA connectors. AC-coupling caps serves as jumpers to switch the
10 G signals between SMAs and the SFP+ connector. The (R)XAUI side can be looped back through the
VSC3316 crosspoint. The VSC3316 can optionally route the (R)XAUI signals to SMA connectors for
external connections. A smaller VSC3308 crosspoint facilitates routing of multiple input and output clock
signals.
For device variants that support IEEE 1588 and MACsec, the EVB can be used to demonstrate simple
features. For IEEE 1588 these basic features include load/save of the time to the LTC, read the egress
timestamp (TS) through MDIO or 1588_SPI and place the TS into the packet in one-step mode. Although
quite limited, the EVB may be used exercise the MACsec functions of encrypt and decrypt specific
defined frames. For more advanced IEEE 1588 and MACsec features the VSC5621EV should be used. This
platform includes a Vitesse switch running Vitesse software on the integrated MIPs processor as well as
both 1 Gbps and 10 Gbps IEEE 1588 and MACsec capable PHYs.
A GUI is provided for the user to control the EVB from a PC via a USB cable. The GUI allows the user to
configure devices, access registers, and run scripts. The GUI may be used without an EVB in a
demonstration mode to provide an introduction to the device features.
An external 5 V power supply is required to power to the EVB. On-board voltage regulators are used to
supply the 1.0 V, 1.2 V, and 2.5 V power rails for the device and the 3.3 V power rail used for auxiliary
components.
The default configuration of the EVB is such that one port is routed to a SFP+ connector (module not
included) and one port is routed to SMAs. This configuration allows the user to easily connect the
evaluation board to lab equipment such as a high speed oscilloscope, bit error rate tester, or protocol
analyzer (i.e., IXIA, Spirent, etc.) through SMA cables or fiber.
The following sections will provide more detailed information in configuring the evaluation board and
the features of the hardware and software associated with the board. The VSC8490EV is used
throughout this document whereas the VSC8489EV and VSC8490EV will behave similarly.
2.1 References
The following documents provide additional information regarding the device and evaluation board.
VSC8489 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8489
VSC8490 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8490
VSC8491 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8491
2.2 General Description
The evaluation board provides electrical connections via 2.92 mm SMA connectors to various signals.
The figure below shows the evaluation board. Channel 0 is found towards the top and upper right side
of the board while Channel 1 is available on the bottom and bottom right side.
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Figure 1 • VSC8490 Evaluation Board
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VSC8489/VSC8490/VSC8491 Evaluation Board
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3 Quick Start
The following items are recommended for use during an evaluation of the EVB:
VSC8489/8490/8491 Evaluation Board (included in the kit)
USB cable (included in the kit)
Wall AC adaptor (included in the kit)
GUI installation file (available on the website)
SR/LR SFP+ module (not included)
Fiber patch cable (not included)
Pattern generator or Protocol tester
Oscilloscope
Personal computer running Windows XP or 7
The user is advised to confirm that the following jumpers are properly configured:
Table 1 • Jumper Settings
Component State
J82 Jumper installed between GPIO0 – GPIO1
J94 Jumper installed between SCL[0]– FPGA/uC
Jumper installed between SDA[0]- FPGA/uC
J95 Jumper installed between SCL[1]- FPGA/uC
Jumper installed between SDA[1]- FPGA/uC
J96 Jumper installed between SCL[0]- F340
Jumper installed between SDA[0]- F340
J97 Jumper installed between SCL[1]- F340
Jumper installed between SDA[1]- F340
The following steps will allow a user to bring up the VSC8490EV, receive traffic from a tester, loop traffic
internal to the device, and transmit back to the tester.
Plug the AC adaptor into a 120 V outlet and the 5 V barrel end into J89. SW2 acts as the power on
/off switch. Slide it to the on position.
Connect the USB cable to the evaluation board (J86) and to a PC.
Insert a 10 G module into U2 (Channel 0).
Connect the optical patch cable to the module and to the 10 G tester.
Install the USB driver per Section 4.1.
Install the GUI Software per Section 4.2.
Launch the GUI.
From the EVB connection window, select the matching board serial number and click .Launch GUI
Go to the clocking page. Choose Channel 0. In the VSC3308-Clock Switch Box, select the crystal clock
(A5- VCC6_XTAL) for the Y4 XREF clock output.
On the Main page, click the 10 G LAN mode option. This will initialize the device. Due to the speed of
the microcontroller this operation may take upwards of 2 minutes. During initialization the bottom
status bar will indicate initialization in progress. When completed, the text will change to indicate
so. Closing the GUI and re-launching without the power cycling the board or pressing the reset
button will retain the previously initialized mode.
After initialization the respective line side or the host side RX and TX PLL status will show a green
state. The 10 G protocol tester should also indicate a
link up condition. Since there is no valid data present at the XAUI receiver, end to end traffic will not
flow.
On the routing tab, enable Loopback L2 for channel 0 (R)XAUI Rx. The 10G tester should now see
valid packets at its receiver.
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VSC8489/VSC8490/VSC8491 Evaluation Board
4 Hardware Options
This sections shows the hardware options for the VSC8489/90/91 evaluation boards.
4.1 Power Supply Options
There are two methods to supply power to this evaluation board, from a wall acadapteror from a bench
style power supply.
The evaluation board can be powered up using the 120 VAC wall socket. Simply plug in the AC adapter
(included in the kit) to a wall socket and the barrel end into the J89 connector. SW2 acts as the power on
/off switch.
The evaluation board can also be powered by an external 5 V power supply. Use a pair of banana cables
to connect a bench style power supply capable of 4 A at 5 V to the board. Connect 5 V to J90 and GND to
J91. SW2 acts as the power on/off switch.
4.2 Reference Clock Options
The EVB supports several device reference clock options. The on-board 156.25 MHz oscillator is the
primary reference clock, although two separate external references can be supplied on SMA connectors
J42 and J44 or J45 and J46. Additional clock rates can be generated using the Silabs 5338 device. These
optional reference clocks can be routed to the device inputs via the VSC3308 crosspoint which plays the
role of a clock distribution chip. Additional clock configuration options are available from the clocking
page of the GUI shown below.
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