Microsemi VSC8489, VSC8490, VSC8491 User Manual

VSC8489/VSC8490/VSC8491

User Guide

VSC8489/VSC8490/VSC8491 Evaluation Board

June 2014

VSC8489/VSC8490/VSC8491 Evaluation Board

Contents

1 Revision History ............................................................................................................................. 1

1.1 Revision 1.0 ........................................................................................................................................ 1

2 Introduction ................................................................................................................................... 2

2.1 References .......................................................................................................................................... 2

2.2 General Description ............................................................................................................................ 2

3 Quick Start ..................................................................................................................................... 4

4 Hardware Options .......................................................................................................................... 5

4.1 Power Supply Options ........................................................................................................................ 5

4.2 Reference Clock Options .................................................................................................................... 5

5 Software ......................................................................................................................................... 6

5.1 USBXpress® Driver Installation ........................................................................................................... 6

5.2 GUI Setup ............................................................................................................................................ 6

5.3 Main Page ........................................................................................................................................... 7

5.4 FPGA ................................................................................................................................................... 8

5.5 Clocking Configuration ....................................................................................................................... 9

5.6 Routing ............................................................................................................................................. 10

5.7 BIST ................................................................................................................................................... 11

5.8 SFP+ .................................................................................................................................................. 13

5.9 Register List ...................................................................................................................................... 14

5.10 Vitesse Command Line Interface .................................................................................................... 15

6 Usage Examples ........................................................................................................................... 17

6.1 Packet BIST ....................................................................................................................................... 17

6.2 Packet BIST Part 2 ............................................................................................................................. 17

6.3 IEEE 1588 .......................................................................................................................................... 17

7 GPIO Pins ...................................................................................................................................... 18

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1 Revision History

The revision history describes the changes that were implemented in this document. The changes are
listed by revision, starting with the most current publication.

1.1 Revision 1.0

Revision 1.0 of this datasheet was published in June 2014. This was the first publication of the
document.

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2 Introduction

The VSC8489, VSC8490, and VSC8491 family of devices are dual and single channel (R)XAUI to SFI PHYs.
They support the standard 10.3125 Gbps Ethernet LAN mode per as well as the 9.95328 IEEE802.ae
Gbps WIS mode from IEEE 802.3ae Clause 50. In addition, the family supports IEEE 802.3ap and 1.25
Gbps rates as well. Certain device variants support the IEEE 1588v2 protocol and/or MACsec protocol.

One of the goals of the VSC8489/8490/8491 evaluation board (EVB) is to enable the user to observe the
signal quality of the SFI I/Os through SMA connectors. AC-coupling caps serves as jumpers to switch the
10 G signals between SMAs and the SFP+ connector. The (R)XAUI side can be looped back through the
VSC3316 crosspoint. The VSC3316 can optionally route the (R)XAUI signals to SMA connectors for
external connections. A smaller VSC3308 crosspoint facilitates routing of multiple input and output clock
signals.

For device variants that support IEEE 1588 and MACsec, the EVB can be used to demonstrate simple
features. For IEEE 1588 these basic features include load/save of the time to the LTC, read the egress
timestamp (TS) through MDIO or 1588_SPI and place the TS into the packet in one-step mode. Although
quite limited, the EVB may be used exercise the MACsec functions of encrypt and decrypt specific
defined frames. For more advanced IEEE 1588 and MACsec features the VSC5621EV should be used. This
platform includes a Vitesse switch running Vitesse software on the integrated MIPs processor as well as
both 1 Gbps and 10 Gbps IEEE 1588 and MACsec capable PHYs.

A GUI is provided for the user to control the EVB from a PC via a USB cable. The GUI allows the user to
configure devices, access registers, and run scripts. The GUI may be used without an EVB in a
demonstration mode to provide an introduction to the device features.

An external 5 V power supply is required to power to the EVB. On-board voltage regulators are used to
supply the 1.0 V, 1.2 V, and 2.5 V power rails for the device and the 3.3 V power rail used for auxiliary
components.

The default configuration of the EVB is such that one port is routed to a SFP+ connector (module not
included) and one port is routed to SMAs. This configuration allows the user to easily connect the
evaluation board to lab equipment such as a high speed oscilloscope, bit error rate tester, or protocol
analyzer (i.e., IXIA, Spirent, etc.) through SMA cables or fiber.

The following sections will provide more detailed information in configuring the evaluation board and
the features of the hardware and software associated with the board. The VSC8490EV is used
throughout this document whereas the VSC8489EV and VSC8490EV will behave similarly.

2.1 References

The following documents provide additional information regarding the device and evaluation board.

VSC8489 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8489
VSC8490 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8490
VSC8491 Datasheet ( )http://www.vitesse.com/products/download.php?number=VSC8491

2.2 General Description

The evaluation board provides electrical connections via 2.92 mm SMA connectors to various signals.
The figure below shows the evaluation board. Channel 0 is found towards the top and upper right side
of the board while Channel 1 is available on the bottom and bottom right side.

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Figure 1 • VSC8490 Evaluation Board

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3 Quick Start

The following items are recommended for use during an evaluation of the EVB:

VSC8489/8490/8491 Evaluation Board (included in the kit)
USB cable (included in the kit)
Wall AC adaptor (included in the kit)
GUI installation file (available on the website)
SR/LR SFP+ module (not included)
Fiber patch cable (not included)
Pattern generator or Protocol tester
Oscilloscope
Personal computer running Windows XP or 7

The user is advised to confirm that the following jumpers are properly configured:

Table 1 • Jumper Settings

Component State

J82 Jumper installed between GPIO0 – GPIO1

J94 Jumper installed between SCL[0]– FPGA/uC

Jumper installed between SDA[0]- FPGA/uC

J95 Jumper installed between SCL[1]- FPGA/uC

Jumper installed between SDA[1]- FPGA/uC

J96 Jumper installed between SCL[0]- F340

Jumper installed between SDA[0]- F340

J97 Jumper installed between SCL[1]- F340

Jumper installed between SDA[1]- F340

The following steps will allow a user to bring up the VSC8490EV, receive traffic from a tester, loop traffic
internal to the device, and transmit back to the tester.

Plug the AC adaptor into a 120 V outlet and the 5 V barrel end into J89. SW2 acts as the power on
/off switch. Slide it to the on position.
Connect the USB cable to the evaluation board (J86) and to a PC.
Insert a 10 G module into U2 (Channel 0).
Connect the optical patch cable to the module and to the 10 G tester.
Install the USB driver per Section 4.1.
Install the GUI Software per Section 4.2.
Launch the GUI.
From the EVB connection window, select the matching board serial number and click .Launch GUI
Go to the clocking page. Choose Channel 0. In the VSC3308-Clock Switch Box, select the crystal clock
(A5- VCC6_XTAL) for the Y4 XREF clock output.
On the Main page, click the 10 G LAN mode option. This will initialize the device. Due to the speed of
the microcontroller this operation may take upwards of 2 minutes. During initialization the bottom
status bar will indicate initialization in progress. When completed, the text will change to indicate
so. Closing the GUI and re-launching without the power cycling the board or pressing the reset
button will retain the previously initialized mode.
After initialization the respective line side or the host side RX and TX PLL status will show a green
state. The 10 G protocol tester should also indicate a
link up condition. Since there is no valid data present at the XAUI receiver, end to end traffic will not
flow.
On the routing tab, enable Loopback L2 for channel 0 (R)XAUI Rx. The 10G tester should now see
valid packets at its receiver.

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4 Hardware Options

This sections shows the hardware options for the VSC8489/90/91 evaluation boards.

4.1 Power Supply Options

There are two methods to supply power to this evaluation board, from a wall acadapteror from a bench
style power supply.

The evaluation board can be powered up using the 120 VAC wall socket. Simply plug in the AC adapter
(included in the kit) to a wall socket and the barrel end into the J89 connector. SW2 acts as the power on
/off switch.

The evaluation board can also be powered by an external 5 V power supply. Use a pair of banana cables
to connect a bench style power supply capable of 4 A at 5 V to the board. Connect 5 V to J90 and GND to
J91. SW2 acts as the power on/off switch.

4.2 Reference Clock Options

The EVB supports several device reference clock options. The on-board 156.25 MHz oscillator is the
primary reference clock, although two separate external references can be supplied on SMA connectors
J42 and J44 or J45 and J46. Additional clock rates can be generated using the Silabs 5338 device. These
optional reference clocks can be routed to the device inputs via the VSC3308 crosspoint which plays the
role of a clock distribution chip. Additional clock configuration options are available from the clocking
page of the GUI shown below.

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5 Software

Although the device’s internal registers can be accessed via three different interfaces, MDIO, two-wire
serial, or SPI, the software makes use of the MDIO port. On the evaluation board a SiLabs F340
microcontroller acts as the MDIO master which controls the PHY. Other board resources are accessed
through other interfaces, such as SPI for the FPGA and two-wire for the SPF+ modules. The
microcontroller translates commands from the PC to the hardware slaves. The PC communicates with
the microcontroller via a USB connection.

5.1 USBXpress® Driver Installation

First, the USBXpress development kit needs to be downloaded from the Silicon Labs website (URL:

). Follow the installation directions after http://www.silabs.com/products/mcu/Pages/USBXpress.aspx

downloading the development kit.

Once the USBXpress driver is installed, connect the USB cable to the EVB and the PC. In order to double
check that the USBXpress driver is installed and recognizing the evaluation board, go to the Control
Panel, and click on System > Hardware > Device Manager. Inspect the Universal Serial Bus controllers
listed to see if “USBXpress Device” appears. The figure below shows the PC has recognized a connect
USBXpress device.

Figure 2 • USBXpress in PC’s Device Manager

5.2 GUI Setup

Run the setup file to install the GUI. Once installed, the user should launch the GUI which will bring up
an initial window as shown in Figure 3. The GUI will detect the serial number of the connected
evaluation board(s). If there are multiple boards connected on the same PC, click on the drop down
menu, and select the desired EVB serial number. The two status lights will turn green when the F340
microcontroller is detected and the appropriate device is present. Click .Launch GUI

If the device indicator (e.g., “VSC8490 Present”) does not turn green, first check the position of the on
/off switch, SW2. If correct, check the voltage rails with a multimeter to ensure the VDD rails reached
the proper levels, thus ruling out current limiting as the cause.

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Figure 3 • EVB Selection Window

5.3 Main Page

The following figure shows the GUI Main page. When the communication is successfully established, it
should say “CONNECTED” at the bottom left corner of the main page. The serial number of the EVB
shows up on the left corner of the page along with the silicon revision, communication protocol used
and the port address. MDIO is the communication protocol used and Channel 0’s default port address is
30 (0 × 1E).

The Mode Initialization box allows the user to choose the mode. 1 G LAN, 10 G WAN, and 10 G LAN are
the supported operating modes. During device initialization, which may take upwards of 2 minutes due
to the microcontroller limitations, the “INITIALIZING” message will appear in the lower corner of the
window. When complete the message will update indicating completion.

The PLL status box shows the host and line side PLL status per channel for the receive and transmit
sides. The LED illuminates green when the appropriate PLL is activated after the mode has been
initialized.

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Figure 4 • GUI Main Page

5.4 FPGA

The FPGA page, shown below, lists all the FPGA registers. Clicking on any register will show their short
description along with their address, default value, read/write capability, and its current value.

Figure 5 • GUI: FPGA Page

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5.5 Clocking Configuration

This page contains several panes including Output clock, VSC3308 Clock Switch, and the 1588 Block.
Figure 6 shows the Clocking page.

The Output Clock selection provides the option to enable and disable RX-Clkout (J4, J7–Channel 0 and
J20, J23–Channel 1) and TX-Clkout(J12, J15–Channel 0 and J27, J31–Channel 1) for both channels. The
channel is selected by the drop down box in the upper right corner. Enabling the output clock will both
turn on the output buffer as well as configure the output frequency based on the selected operating
mode. The 10G LAN mode supports a frequency of 161 MHz.

The VSC3308 Clock distribution device provides the option of routing different clock sources (Clk0, CLk1,
Clk2, CLk3, CLk_J42/J44, CLk_J45/J46 or VCC6_XTAL) to VSC8489/VSC8490/VSC8491 Evaluation Board
User Guide Revision 1.0 June 2014 Vitesse Proprietary and Confidential Page 13 of 23 destinations (J43,
WRef, 1588_Ref, J48/J47-SMA, XRef, SRef). In most applications, routing the A5- VCC6-XTAL (156.25
MHz) to the XREF input is desired.

The basic IEEE 1588 time stamping capabilities can be evaluated on the EVB. The following configuration
options are available.

Clock frequency can be selected as internal or external. 1588 supports external clock frequency of
125 MHz
Modes supported by 1588 are Egress, Ingress and both.
Ingress FIFO Timestamp:

Ingress timestamp will be read at the reserved bytes of the PTP packet. When only the ingress
mode is enabled, and external XAUI loopback or L1 is
selected, the modified timestamp will be in the PTP packets captured by the external 10G
protocol tester.

Egress FIFO Timestamp:

This block gives the timestamp of the PTP frames sent by the traffic generator.
The timestamp can be read using MDIO or SPI communication protocol.
This feature is unavailable for Ingress Mode.
Steps to read Timestamp:

Initialize Egress or Ingress-Egress Mode;
Enable line side loopback, L1, L2, or external XAUI from the Routing page.
Choose the communication protocol (Either MDIO or SPI).
Send PTP frames from traffic generator. For simplicity of comparison of the
loopback PTP frame and the egress timestamp captured by the PHY, it is
recommended to send a single burst of a few, say 5, PTP frames from the
traffic generator.
Hit the button. This shows the full 26 bytes separated into theRead
timestamp (10 bytes) and Frame Signature (16 bytes) of the first packet.
Hitting the button again will read the next packet and display the contents
in the next field.
Clear all clears the previous timestamps. It is always advisable to perform
a clear all after reading a set of timestamps.

The Local Time Counter allows loading and saving the time (in seconds and
nanoseconds) in the 1588 block. Enter the time in hex (0 to FFFFFFFF) in the
textboxes and click the Update button to Load/Save respectively. GPIO_0 and
GPIO_1 must be shorted together to make this functional.
The Add/Subtract 1ns feature adds and subtracts the appropriate textbox specified
nanoseconds to the local time.
Checking the Enable the 1 PPS Output checkbox will enable the output. With
appropriate oscilloscope triggering, the user can see the effects of shifting the 1
PPS signal.
The 1588 block is turned off by clicking Turn Off 1588 Engine. To turn the block
on again the user must initialize the mode (Egress/Ingress/Both) after choosing
the clock input.

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Figure 6 • GUI: Clocking Page

5.6 Routing

The Routing page controls the VSC3316 XAUI/RXAUI switch as well as device loopbacks. The Channel
Selection box in the upper right corner selects the active PHY channel to configure. A data path diagram
of the loopbacks is displayed on the top of this page.

There are 6 loopbacks and 2 BIST engines available. Three of the loopbacks are Host side loopbacks, (i.e.,
XAUI in and looped back to XAUI out). These include loopback H2, loopback H3, and loopback H4.
Loopback H2 is the shallow loopback located in the XAUI-PHY block before the 8b/10b endec. The
deeper loopback includes loopback SC8489/VSC8490/VSC8491 Evaluation Board User Guide Revision 1.0
June 2014 Vitesse Proprietary and Confidential Page 15 of 23 H3 in the PCS block right after the 64b/66b
gearbox and loopback H4 at the WIS block after the framer.

The other 3 loopbacks are line side loopbacks, (i.e., SFI in and looped back to SFI out). This includes
loopback L3, loopback L2, and loopback L1. Loopback L3 is the loopback at the PMA block while
loopback L2 is the loopback right before the data hits the XGXS block. The deepest loopback L1 is the
loopback after the 8b/10b endec. When using loopback L1 with an external 10G tester, the entire chip is
exercised with the exception of the XAUI input and output buffers.

The GUI allows the user to turn on Host and Line Side loopbacks for 10G LAN and 1G LAN modes.
Checking the box enables the loopback while un-checking disables it. Figure 7 shows L2 loopback as
turned on.

The evaluation board also supports looping back the data at the external XAUI bus. This could be looped
back to the same channel or across the two channels of the PHY. Selecting the XAUI_Rx_0 from
XAUI_Tx_0 is a same channel self loopback. Selecting the XAUI_Rx_0 from XAUI_Tx_1, and XAUI_Rx_1
from XAUI_Tx_0 at the same time, is a cross channel loopback.

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Figure 7 • GUI: Routing Page

5.7 BIST

The VSC8489 family of devices support two different built in self test (BIST) types. The first is an
unframed PRBS31 pattern as described in section 50.3.8 of IEEE 802.3ae. The second is a packet based
BIST. Each channel has its own BIST and the channel can be selected from the drop down selection box
in the upper right. Figure 8 gives an example of the Packet BIST. The user must first enable the packet
BIST by checking the box in the upper right.Enable

On the TX side, clicking will display both the Current Count (amount sent since the last Read) and Read
the Cumulative Count (amount sent since Start). Clicking will disable the packet transmission.Stop

On the RX side, there are options to read the count of Good Packets, Bad Packets, Fragments, Local
Faults and the Bit Error Rate. These counters behave in the same manner as the TX side.

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Figure 8 • GUI: BIST Page – Packet

Figure 9 shows the PRBS31 pattern generator and checker. Click and to Start Generator Start Checker
start the BIST. This begins the synchronization and error checking on the selected channel along with a
timer. The cumulative number of bit errors and the cumulative bit error rate are displayed.

Stop Checker will stop the timer and polling of the error count. The page will retain the last values. To
change from one channel to another the user may keep the generator on, but should stop and restart
the checker after changing the channel. While enabled, the error count register polling is not
interrupted when any other page is viewed.

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Figure 9 • GUI: BIST Page – PRBS31

5.8 SFP+

This page contains two tabs. One for address A0 h and the other for address A2 h.It reads out the value
of various data fields from the SFP+ transceiver for both these addresses. Be sure that the transceiver is
inserted properly otherwise the “Transceiver not found” message will appear after the user clicks the

button. After successful module reads, the module information will be decoded and displayed on Read
the page. Where options exist, the selected option will show as green while the remaining options will
show as red. Although the device’s two-wire serial master can read the module contents, the default
configuration accesses the module from the microcontroller.

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Figure 10 • GUI: SFP Page

5.9 Register List

The Register List page provides read and write access to device registers. They are grouped into 10 tabs.
To select a register, click on the name in the list. The register’s description, address, read/write
capability and current value are displayed. To write to a device register, highlight the desired register,
enter the hexadecimal value in the “Value (Hex)” box and click Write. Clicking Read will read the same
register showing the register’s new contents.

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Figure 11 • GUI: Register List Page

5.10 Vitesse Command Line Interface

Clicking on > from the toolbar opens the Vitesse Command Line Interface (CLI) window. uC Vitesse CLI
From here users can load initialization files or other scripts.
When the button is clicked, another window will appear allowing the user to select the Load Macro
script to be executed as seen below. Clicking on the button will erase all previous commands sent Clear
from the CLI window.

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Figure 12 • Command_Line_Interface

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6 Usage Examples

This section shows the usage examples for the VSC8489, VSC8490, and VSC8491 evaluation boards.

6.1 Packet BIST

Perform all steps outlined in section 2.
On the BIST page. Check in the Packet BIST box, this enables the Packet BIST. Click in Enable Read
the TX pane. The count of valid packets sent is seen in the Current Count box. Clicking again Read
will show the amount since the last read in the Current Count and the Cumulative Count since the
BIST was enabled. The button terminates packet transmission, and resets and erases the Stop Clear
counters.
In the RX pane, click to update the desired counter. Both current and cumulative counts are Read
shown similar to the TX pane.

6.2 Packet BIST Part 2

Perform all steps outlined in section 2.
On the BIST page, to exercise the PRBS31 BER, click on Start Generator and Start Checker. Starting
the checker will start the timer and show the current Error count and Bit Error Rate. The value of
error count and BER is continuous and updated once every second. The previous cumulative values
of both error count and BER are shown in the cumulative box fields respectively. Click Stop Checker
to stop the timer. The display will retain the last error count and BER.
Clicking Start Checker again will clear the error counts and restart the pollingand calculation.
The 1 second polling will continue even if the user moves to other pages. Upon returning to the BIST
page the error count and BER will display the cumulative numbers.

6.3 IEEE 1588

Perform all steps outlined in section 2.
On the Clocking page. In the 1588 Block, select from the Clock Selection list and click Internal Clock
the option. Click on .Egress Mode Egress timestamp using MDIO
Send up to 5 PTP packets from the traffic generator.
Click the button. This will display the 26 relevant bytes separated into the 10 byte timestamp Read
and 16 byte frame signature from the first packet. Clicking again will display the next packet in Read
the next set of fields.
In the same 1588 pane on the clocking page, load any time in the range of 0-FFFFFFFF into the Secs
and the Nanosecs field of the Local Time Counter and press in the Load pane. Once the time Update
is set, clicking in the save pane will fetch the local time from the device and display it into Update
the respective secs and NanoSecs fields.

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7 GPIO Pins

There are sixteen GPIO pins available on the device. Several different functions are multiplexed to these
pins. Refer to section 2.15.6 of the datasheet for further information about GPIO pin configuration.

On the EVB all GPIO signals are connected to headers with pull up resistors. Through the headers,
signals may be injected to the device as inputs, or if configured as outputs monitored by external
equipment or connected to off-board logic. The GPIO VSC8489/VSC8490/VSC8491 Evaluation Board
User Guide Revision 1.0 June 2014 Vitesse Proprietary and Confidential Page 23 of 23 signals are also
connected to the FPGA for on board control if desired. Two GPIO configuration examples are provided.

To configure GPIO_6 as an interrupt (INTR) signal:

Write the Global:GPIO_6_Config_Status (1Ex0124) register as follows:

Bits 2:0 should be 010 to select the WIS Interrupt Output feature
Bits 7:5 should be 001 to setup Interrupt B from channel 1 as the source.
Bits 15:8 and 4:3 are don’t care bits here.

Global:GPIO_6_Config2 (1Ex0125) does not apply in this situation.
Write Channel 1’s WIS:EWIS_INTR_MASKA_2 (2xEE05) bit 0 to “1” to enable HIGH_BER_PEND to
trigger an interrupt. Bits 15:1 should be “0” as no other alarms should active an interrupt in this
case.

To configure GPIO_9 for Rx Alarm:

Write the Global:GPIO_9_Config_Status (1Ex012A) register as follows:

Bits 2:0 should be 001 to select PCS Activity LED output.
Bits 4:3 should be 00 to select Rx activity alarm for channel 0..
Bits 15:5 are don’t care bit here.

Write the PMA:VendorSpecificPMAControl2 (1xA100) register as follows:

Bit 7 should be 1 to select the blink time interval of 100 ms.
Bits 4:3 should be 00 to select Rx activity alarm for channel 0..
Bits 15:5 are don’t care bit here.

Please note that the GPIO pins share many different functions. Some functions are available on any
GPIO while some are only available on dedicated pins. Refer to the device datasheet when selecting
functions and GPIO pin assignments.

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complete all performance and other testing of the products, alone and together with, or installed in , any end-products. Buyer shall not rely on any data
and per formance specifications or para meters provided by Microsemi. It is the Buyer's responsibility to ind ependently determine suitability of any
products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the
entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights,
licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietar y to Microsemi, and Micr osemi reserves the right to make any changes to the information in this document or to any products
and services at any time without notice.

Microsemi, a wholly owned subsidi ary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system
solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened
analog m ixed-signal integrated circuits, FPG As, SoCs and ASICs; power management products; timing and synchronization devices and p recise time
solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communica tion
solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi i s headquartered in Aliso Viejo, California, and has approxim ately 4,800 employees globally. Learn more at www.
microsemi.com.

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