Microsemi SmartTime User Manual
SmartTime Static Timing Analyzer
User Guide
SmartFusion2, IGLOO2, RTG4, and PolarFire
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SmartTime Static Timing Analyzer User Guide
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5-02-00560-6/01.17
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SmartTime Static Timing Analyzer User Guide
Table of Contents
About SmartTime (Enhanced Constraint Flow) ......................................................................... 7
Design Flows with SmartTime ................................................................................................... 9
Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and PolarFire ................. 10
SmartTime Components .......................................................................................................... 10
Setting SmartTime Options - SmartFusion2, IGLOO2, RTG4, and PolarFire ......................... 11
SmartTime Toolbar .................................................................................................................. 13
SmartTime Timing Analyzer ..................................................................................................... 14
SmartTime Timing Analyzer ........................................................................ 15
Components of the SmartTime Timing Analyzer ..................................................................... 16
Analyzing Your Design ............................................................................................................. 17
Performing a Bottleneck Analysis ............................................................................................ 19
Managing Clock Domains ........................................................................................................ 21
Managing Path Sets ................................................................................................................. 22
Displaying Path List Timing Information................................................................................... 24
Displaying Expanded Path Timing Information ........................................................................ 26
Using Filters ............................................................................................................................. 28
Advanced Timing Analysis ......................................................................... 31
Understanding Inter-Clock Domain Analysis ........................................................................... 32
Activating Inter-Clock Domain Analysis ................................................................................... 33
Displaying Inter-Clock Domain Paths ...................................................................................... 34
Deactivating a Specific Inter-Clock Domain ............................................................................. 35
Changing Output Port Capacitance ......................................................................................... 36
Generating Timing Reports ......................................................................... 37
Types of Reports ...................................................................................................................... 38
Generating a Timing Report ..................................................................................................... 39
Understanding Timing Reports ................................................................................................ 40
Generating a Timing Violation Report ...................................................................................... 43
Understanding Timing Violation Reports ................................................................................. 44
Generating a Constraints Coverage Report ............................................................................ 46
Understanding Constraints Coverage Reports ........................................................................ 47
Generating a Bottleneck Report ............................................................................................... 49
Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire ............. 50
Generating a Datasheet Report ............................................................................................... 52
Understanding Datasheet Reports ........................................................................................... 53
Generating a Combinational Loop Report ............................................................................... 55
Understanding Combinational Loop Reports ........................................................................... 56
Timing Concepts .......................................................................................... 57
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SmartTime Static Timing Analyzer User Guide
Static Timing Analysis Versus Dynamic Simulation ................................................................. 58
Timing Exceptions Overview .................................................................................................... 60
SmartTime Tutorials (Enhanced Constraints Flow) ................................................................. 67
Dialog Boxes ................................................................................................ 92
Add Path Analysis Set Dialog Box ........................................................................................... 93
Analysis Set Properties Dialog Box ......................................................................................... 95
Edit Filter Set Dialog Box ......................................................................................................... 96
Customize Analysis View Dialog Box ...................................................................................... 97
Manage Clock Domains Dialog Box ........................................................................................ 99
Set False Path Constraint Dialog Box.................................................................................... 100
SmartTime Options Dialog Box - SmartFusion2, IGLOO2, RTG4, and PolarFire ................. 102
Store Filter as Analysis Set Dialog Box ................................................................................. 105
Timing Bottleneck Analysis Options Dialog Box .................................................................... 106
Timing Datasheet Report Options Dialog Box ....................................................................... 110
Timing Report Options Dialog Box ......................................................................................... 111
Timing Violations Report Options Dialog Box ........................................................................ 115
Data Change History - SmartTime ............................................................ 117
Tcl Commands ........................................................................................... 118
create_set .............................................................................................................................. 119
expand_path .......................................................................................................................... 121
list_paths ................................................................................................................................ 123
remove_set ............................................................................................................................ 125
report ...................................................................................................................................... 126
save ........................................................................................................................................ 130
set_options (SmartFusion2, IGLOO2, RTG4, and PolarFire) ................................................ 131
Glossary ..................................................................................................... 134
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SmartTime Static Timing Analyzer User Guide
About SmartTime (Enhanced Constraint Flow)
SmartTime is the Libero SoC gate-level static timing analysis tool. With SmartTime, you can perform
complete timing analysis of your design to ensure that you meet all timing constraints and that your design
operates at the desired speed with the right amount of margin across all operating conditions.
Note: SmartTime in the Enhanced Constraint Flow has changed. Creation and Editing of timing constraints
are now handled in a separate Timing Constraints Editor. See the Timing Constraints Editor
with creating and editing timing constraints in the Enhanced Constraints Flow.
Static Timing Analysis (STA)
Static timing analysis (STA) offers an efficient technique for identifying timing violations in your design and
ensuring that it meets all your timing requirements. You can communicate timing requirements and timing
exceptions to the system by setting timing constraints. A static timing analysis tool will then check and report
setup and hold violations as well as violations on specific path requirements.
STA is particularly well suited for traditional synchronous designs. The main advantage of STA is that unlike
dynamic simulation, it does not require input vectors. It covers all possible paths in the design and does all
the above with relatively low run-time requirements.
The major disadvantage of STA is that the STA tools do not automatically detect false paths in their
algorithms as it reports all possible paths, including false paths, in the design. False paths are timing paths
in the design that do not propagate a signal. To get a true and useful timing analysis, you need to identify
those false paths, if any, as false path constraints to the STA tool and exclude them from timing
considerations.
The SmartTime user interface provides effici ent, us er -friendly ways to define these critical false paths.
for help
Timing Constraints
SmartTime supports a range of timing constraints to provide useful analysis and efficient timing-driven
layout.
Timing Analysis
SmartTime provides a selection of analysis types that enable you to:
• Find the minimum clock period/highest frequency that does not result in a timing violations
• Identify paths with timing violations
• Analyze delays of paths that have no timing constraints
• Perform inter-clock domain timing verification
• Perform maximum and minimum delay analysis for setup and hold checks
To improve the accuracy of the results, SmartTime evaluates clock skew during timing analysis by
individually computing clock insertion delays for each register.
SmartTime checks the timing requirements for violations while evaluating timing exceptions (such as
multicycle or false paths).
SmartTime and Place and Route
Because Libero SoC Place and Route uses SmartTime STA during timing-driven place-and-route in the
background; your analysis and place and route constraints are always consistent.
SmartTime and Timing Reports
From SmartTime > Tools > Reports, the following report files can be generated:
• Timing Report (for both Max and Min Delay Analysis)
• Timing Violations Report (for both Max and Min Delay Analysis)
• Bottleneck Report
• Constraints Coverage Report
• Combinational Loop Report
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SmartTime Static Timing Analyzer User Guide
SmartTime and Cross-Probing into Chip Planner
From SmartTime, you can select a design object and cross-probe the same design object in Chip Planner.
Design objects that can be cross-probed from SmartTime to Chip Planner include:
• Ports
• Macros
• Timing Paths
SmartTime and Cross-Probing into Constraints Editor
From SmartTime, you can cross-probe into the Constraints Editor. Select a Timing Path in SmartTime’s
Analysis View and add a Timing Exception Constraint (False Path, Multicycle Path, Max Delay, Min Delay) .
The Constraint Editor reflects the newly added timing exception constraint.
The Constraints Editor must be running for Cross-Probing to work.
See Also
Starting and Closi ng SmartTime
Components of SmartTime Timing Analyzer
Changing SmartTime Preferences
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SmartTime Static Timing Analyzer User Guide
Design Flows with SmartTime
You can access SmartTime in Libero SoC either implicitly or explic itly during the following phases of design
implementation:
• During Place and Route – When you select timing-dri ven place-and-route, SmartTime runs in the
background to provide accurate timing information.
• After Place and Route – Run S martT ime to per for m post-layout timing analysis and adjust timing
constraints. In the Libero SoC Design Flow window, expand Implement Design > Verify Post-Layout
Implementation. You can:
• Double-click Verify Timing to generate Timing Reports.
• Right-click Open SmartTime > Open Interactively to run SmartTime.
• During Back-Annotation – SmartTime runs in the background to generate the SDF file for timing
simulation.
You can also run SmartTime whenever you need to generate timing reports, regardless of which design
implementation phase you are in.
See Libero SoC for Enhanced Constraint Flow
Annotation.
for more information about Place and Route and Back-
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SmartTime Static Timing Analyzer User Guide
Starting and Closing SmartTime - SmartFusion2, IGLOO2, RTG4, and
PolarFire
You must have completed Place and Route for your design before using SmartTime interactively. If your
design has not yet been placed-and-routed, Libero SoC will complete that phase prior to starting SmartTime.
To open SmartTime interactively, in Implement Design > Verify Post Layout Implementation right-click
Open SmartTime > Open Interactively.
SmartTime reads your design and displays post- or pre-layout timing information.
To close SmartTime, from the File menu, choose Exit.
SmartTime Components
• The Maximum Delay Analysis View and the Minimum Delay Analysi s View enable you to
analyze your design
With SmartTime, you can:
• Browse through your design’s various clock domains to examine the timing paths and identify those
that violate your timing requirements
• Create customizable timing report s
• Navigate directly to the paths responsible for violating your timing requirements
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SmartTime Static Timing Analyzer User Guide
Setting SmartTime Options - SmartFusion2, IGLOO2, RTG4, and
PolarFire
You can modify SmartTime options for timing anal ysis by using the SmartTime Options dialog box.
To set SmartTime options:
1. From the SmartTime Maximum/Minimum Delay Analysis View window, choose Tools> Options.
The SmartTime Options dialog box has three categories: General, Analysis and Advanced.
2. In the General category, select the settings for the operating conditions. SmartTime performs
maximum or minimum delay analysis based on the Best, Typical, or Worst case.
3. Check or uncheck whether you want SmartTime to use inter-clock domains in calculations for timing
analysis.
4. Click Restore Defaults only if you want the settings in the General pane to revert to their default
settings.
5. Click Analysis to display the options you can modify in the Analysis view.
6. Enter a number greater than 1 to specify the maximum number of paths to include in a path set during
timing analysis.
7. Check or uncheck whether to filter the paths by slack value. If you check this box, you must then
specify the slack range between minimum slack and maximum slack.
8. Check or uncheck whether to include clock network deta ils .
9. Enter a number greater than 1 to specify the number of parallel paths in the expanded path.
10. Click Restore Defaults only if you want the settings in the Analysis View pane to revert to their default
settings.
11. Click Advanced to display advanced options.
12. Check or uncheck whether to use loopback in bidirectional buffers (bibufs) and/or break paths at
asynchronous pins. Check or uncheck whether to disable non-unate arc s in the clock path.
13. Click Restore Defaults only if you want the settings in the Advanced pane to revert to their default
settings.
14. Click OK.
Figure 1 · SmartTime Options Dial og Box – General Options
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SmartTime Static Timing Analyzer User Guide
Figure 2 · SmartTime Options Dial og Box – Analysis Options
Figure 3 · SmartTime Options Dial og Box – Advanced Options
See Also
SmartTime Options Dialog Box
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SmartTime Static Timing Analyzer User Guide
Icon
Description
constraints editor
the constraints editor
the constraints editor
analysis view
analysis view
manager
SmartTime Toolbar
The SmartTime toolbar contains commands for constraining or analyzing designs. Tool tips are available for
each button.
Table 1 · SmartTime Toolbar
Commits the changes
Prints the contents of the
Copies data to the clipboard
Pastes data from the clipboard
Modifies the selected object from
Deletes the selected object from
Undoes previous changes
Redoes previous changes
Opens the maximum delay
Opens the minimum delay
Opens the manage clock domains
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Opens the path set manager
Recalculates all
SmartTime Static Timing Analyzer User Guide
SmartTime Timing Analyzer
The SmartTime Timing Analyzer is an interactive Static Timing Analysis tool. Click Open SmartTime in the
Design Flow Window to invoke the SmartTime Timing Analyzer (Design Flow Window > Open SmartTime
> Open Interactively).
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SmartTime Static Timing Analyzer User Guide
SmartTime Timi ng A nalyzer
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SmartTime Static Timing Analyzer User Guide
Components of the SmartTime Timing Analyzer
Use the SmartTime Timing Analyzer to visualize and identify timing issues in your design for the selected
scenario. In this view, you can evaluate how far you are from meeting your timing requirements, create
custom sets to track, set timing exceptions to obtain timing closure, and cross-probe paths with other tools.
The timing analysis view includes:
• Domain Browser: Enables you to perform your timing analysis on a per domain basis.
• Path List: Displays paths in a specific set in a given domain sorted by slack.
• Path Details: Displays detailed timing analysis of a selected path in the paths list.
• Analysis View Filter: Enables you to filter the content of the paths list.
• Path Slack Histogram: When a set is selected in the Domain Browser, the Path Slack Histogram
displays a distribution of the path slacks for that set. Selecting one or multiple bars in the Path Slack
Histogram filters the paths displayed in the Path List.
You can copy, change the resolution and the number of bars of the chart from the right-click menu.
Figure 4 · SmartTime Timing Analyzer Components
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SmartTime Static Timing Analyzer User Guide
Analyzing Your Design
The timing engine uses the following priorities when analyzing paths and calculating slack:
1. False path
2. Max/Min delay
3. Multi-cycle path
4. Clock
If multiple constraints of the same priority apply to a path, the timing engine uses the tightest constraint.
You can perform two types of timing analysis: Maximum Delay Analysis and Minimum Delay Analysis.
To perform the basic timing analysis:
1. Open the Timing Analysis View using one of the following methods:
• In the Design Flow window, click the Timing Analyzer icon to display the
SmartTime Timing Analyzer.
• From the Sm artTime Tools menu, choose Timing Analyzer > Maximum
Delay Analysis or Minimum Delay Analysis.
• Click the icon for Maximum Delay Analysis or the icon for Minimum
Delay Analysis from the SmartTime window.
Note: When you open the Timing Analyzer from Designer, the Maximum Delay Analysis window is
displayed by default.
2. In the Domain Browser, select the clock domain. Clock domains with a indicate that the timing
requirements in these domains were met. Clock domains with an x indicate that there are vi olations
within these domains. The Paths List displays the timing paths sorted by slack. The path with the
lowest slack (biggest violation) is at the top of the list.
3. Select the path to view. The Path Details below the Paths List displays detailed information on how the
slack was computed by detailing the arrival time and required time calculation. When a path is
violated, the slack is negative and is displayed in red color.
4. Double-click the path to display a separate view that includes the path details and schematic.
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Figure 5 · Maximum Delay Analysis View
SmartTime Static Timing Analyzer User Guide
Note: In cases where the minimum pulse width of one element on the critical path limits the maximum
frequency for the clock, SmartTime displays an icon for the clock name in the Summary List.
Click on the icon to display the name of the pin that limits the clock frequency.
5. Repeat the above steps as required.
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SmartTime Static Timing Analyzer User Guide
Performing a Bottleneck Analysis
To perform a bottleneck analysis
1. From SmartTime’s Max/Min Delay Analysis View, select Tools > Bottleneck Analysis. The Timing
Bottleneck Analysis Options dialog box appears.
2. Select the options you wish to display for bottleneck information and click OK.
The Bottleneck Analysis View appears in a separate window (see image below).
A bottleneck is a point in the design that contributes to multiple timing violations. The Bottleneck Analysis
View contains two sections:
• Device Description
• Bottleneck Description
Device Description
The device section contains general information about the design and the parameters that define the
bottleneck computation:
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Figure 6 · Bottleneck Analysis View
SmartTime Static Timing Analyzer User Guide
• Design name
• Family
• Die
• Package
• Design state
• Data source
• Set selection type
• Max paths
• Bottleneck instances
• Analysis type
• Analysis max case
• Voltage
• Temperature
• Speed grade
• Cost type
• Max parallel paths
• Slack threshold
Bottleneck Description
This section displays a graphic representation of the bottleneck analy s is and li sts the core o f the bottl ene ck
information for the bar selected in the chart above. If no bar is selected, the grid lists all bottleneck
information.
Click the controls on the right to zoom in or out the contents in the chart.
Right-click the chart to export the chart or to copy the chart to the clipboard.
The list is divided into two columns:
• Instance name: refers to the output pin name of the instan ce .
• Bottleneck cost: displays the pin's cost giv en the cho sen cost type. Pin names are lis ted in decre asi ng
order of their cost type.
See Also
Timing Bottleneck Analysis Options dialog box (SmartTime)
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SmartTime Static Timing Analyzer User Guide
Managing Clock Domains
In SmartTime, timing paths are organized by clock domains. By default, SmartTime displays domains with
explicit clocks. Each clock domain includes at least three path sets:
• Register to Register
• External Setup (in the Maximum Analysis View) or External Hold (in the Minimum Analysis View)
• Clock to Out
You must select a path set to display a list of paths in that specific set.
To manage the clock domains:
1. Right-click anywhere in the Domain Browser, and choose Manage Clock Domains. The
Clock Domains dialog box appears (as shown below).
Tip: You can click the icon in the Sm artTime window bar to display the Manage Clock Domains
dialog box.
Manage
2. To add a new domain, select a clock domain from the Available clock domains list, and click either
Add or New Clock to add a non-explicit clock domain.
3. To remove a displayed domain, select a clock domain from the Show the clock domainin this order
list, and click Remove.
4. To change the display order in the Domain Browser, select a clock domain from the Show the clock
domainin this order list, and then use the Move Up or Move Down to change the order in the list.
5. Click OK. SmartTime updates the Domain Browser based on your specifications. If you have added a
new clock domain, then it will include at least the three path sets as mentioned above.
See Also
Manage Clock Domains Dialog Box
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Figure 7 · Manage Clock Domains Dialog Box
SmartTime Static Timing Analyzer User Guide
Managing Path Sets
You can create and manage custom path sets for timing analysis and tracking purposes. Path sets are
displayed under the Custom Path Sets at the bottom of the Domain Browser.
To add a new path set:
1. Right-click anywhere in the Domain Browser, and choose Add Set. The Add Path Analysis Set Dialog
Box dialog box appears (as shown below).
Tip: You can click the icon in the Sm artTime window bar to display the Add Path Analysis Set
dialog box.
2. Enter a name for the path set.
3. Select the source and sink pins. You can use the filters
4. Click OK. The new path set appears under Custom Path Sets in the Domain Browser (as shown
below).
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Figure 8 · Add Path Analysis Set Dialog Box
to control the type of pins displayed.
SmartTime Static Timing Analyzer User Guide
Figure 9 · Updated Domain Browser with User Sets
To remove an existing path set:
1. Select the path set from the User Sets in the Domain Browser.
2. Right-click the set to delete, and then choose Delete Set from the right-click menu.
To rename an existing path set:
1. Select the path set from User Set in the Domain Browser.
2. Right-click the set to rename, and then choose Rename Set from the right-click menu.
3. Edit the name directly in the Domain Browser.
See Also
Add Path Analysis Set Dialog Box
Using Filters
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SmartTime Static Timing Analyzer User Guide
Displaying Path List Timing Information
The Path List in the Timing Analysis View displays the timing information required to verify the timing
requirements and identify violating paths. The Path List is organized in a grid where each row represents a
timing path with the corresponding timing information displayed in columns. Timing information is
customizable; you can add or remove columns for each type of set.
By default, each type of set displays a subset of columns as follows:
• Register to Register: Source Pin, Sink Pin, Del ay, Slack, Arrival, Required, Setup, Minimum Period,
and Skew.
• External Setup: Source Pin, Sink Pin, Delay, Slack, Arrival, Required, Setup, and External Setup.
• Clock to Out: Source Pin, Sink Pin, Delay, Slack, Arrival, Required, and Clock to Out.
• Input to Output: Source Pin, Sink Pin, Delay, and Slack.
• Custom Path Sets: Source Pin, Sink Pin, Delay, and Slack.
You can add the following columns for each type of set:
• Register to Register: Clock, Source Clock Edge, Destination Clock Edge, Logic Stage Count, Max
Fanout, Clock Constraint, Maximum Delay Constraint, and Multicycle Constraint.
• External Setup: Clock, Destination Clock Edge, Logic Stage Count, Max Fanout, Clock Constraint,
Input Delay Constraint, Required External Setup, Maximum Delay Constraint, and Multicycle
Constraint.
• Clock to Out: Clock, Source Clock Edge, Logic Stage Count, Max Fanout, Clock Constraint, Output
Delay Constraint, Required Maximum Clock to Out, Maximum Delay Constraint, and Multicycle
Constraint.
• Input to Output: Arrival, Required, Setup, Hold, Logic Stage Count, and Max Fanout.
• Custom Path Sets.
To customize the set of timing information in the Path List:
1. Select the set to customize.
2. Select the whole Paths List by clicking in the upper-left corner .
3. Right-click anywhere on the column headings, and then choose Customize table from the right-click
menu. The Customize Analysis View Dialog Box
dialog box appears (as shown below).
4. To add one or more columns, select the fields to add from the Available fields list, and click Add.
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Figure 10 · Customize Analysis View Dialog Box
SmartTime Static Timing Analyzer User Guide
5. To remove one or more columns, select the fields to remove from the Show these fields in this order
list, and click Remove.
6. Click OK to add or remove the selected columns. SmartTime updates the Timing Analysis View.
See Also
Customize Analysis View
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SmartTime Static Timing Analyzer User Guide
Displaying Expanded Path Timing Information
SmartTime displays the list of paths and the path details for all parallel paths.
Figure 11 · Expanded Path View
The Path List displays all parallel paths in your design. The Path Details grid displays the path details for all
parallel paths.
To display the Expanded Path View:
From the Path List: double-click the path, or right-click a path and select expand selected paths.
From the Expanded Path View: double-click the path, or right -click the path and se lect expand path.
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SmartTime Static Timing Analyzer User Guide
Figure 12 · Expanded Path View
The Expanded Path Summary provides a summary of all parallel paths for the selected path. The Path
Profile chart displays the percentage of time taken by cells and nets for the selected path. If no parallel path
is selected in this view, the Path Profile shows the percentage for all paths. By default, SmartTime only
shows one path for each Expanded Path. You can change this default in the SmartTime Options
dialog box.
The Expanded Path View also includes a schematic of the path and a path profile chart for the paths
selected in the Expanded Path Summary.
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SmartTime Static Timing Analyzer User Guide
Using Filters
You can use filters in SmartTime to limit the Path List content (that is, create a filtered list on the source and
sink pin names). The filtering options appear on the top of the Timing Analysis View. You can save these
filters one level below the set under which it has been created.
To use the filter:
1. Select a set in the Domain Browser to display a given number of paths, depending on your
Options settings (100 paths by default).
2. Enter the filter criteria in both the From and To fields and click Apply Filter. This limits the display to
the paths that match your filter criteria.
Figure 13 · Maximum Delay Analysis View
3. Click Store Filter to save your filter criteria with a special name. The Create Filter Set dialog box
appears (as shown below).
SmartTime
Figure 14 · Create Filter Set Dialog Box
4. Enter a name for the filter, such as myfilter01, and click OK. Your new filter name appears below the
set under which it was created.
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SmartTime Static Timing Analyzer User Guide
Figure 15 · my_filter01
Figure 16 · Updated Maximum Delay Analysis View
Repeat the above steps and cascade as many sets as you need using the filtering mechanism.
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SmartTime Static Timing Analyzer User Guide
To remove a set created with filters:
1. Select the set that uses filters.
2. Right-click the set, and choose Delete Set from the shortcut menu.
To rename a set created with filters:
1. Select the set that uses filters.
2. Right-click the set, and choose Rename Set from the shortcut menu.
3. Edit the name directly in the Domain Browser.
To edit a specific filter in the set:
1. Select the filter to edit.
2. Right-click the filter, and choose Edit Set from the shortcut menu.
See Also
SmartTime Options
Store Filter as Analysis Set
Edit Set dialog box
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