The RoHS-compliant SmartFusion® Development Kit (A2F500-DEV-KIT -2) enables designers to develop
applications that involve one or more of the following:
•Microcontroller applications
•Real-time operating system (RTOS)/OS development
•Embedded ARM
•Motor control
•System management
•Power sequencing, trimming, and management
•Touch screen display control
•Audio processing
•FieldBus
•EtherCAT
•Industrial network
The board also provides a standard 100-pin mixed signal header for interfacing to the analog pins. This
provides access for plugging in a daughter board with a mixed signal interface.
®
Cortex™-M3 processor based systems
®
demonstrator
®
Figure 1 • A2F500-DEV-KIT-2
Revision 75
Introduction
Kit Contents
Table 1 lists the contents of the SmartFusion Development Kit.
Table 1 • Kit Contents – A2F500-DEV-KIT-2
QuantityDescription
1SmartFusion Development Board with SmartFusion A2F500M3G-FGG484ES device
1Low-cost programming stick (LCPS) or FlashPro 4 programmer
15 V power supply with international adapters
2USB 2.0 A to mini-B cable
1Quickstart card
SmartFusion Development Kit Web Resources
The SmartFusion Development Kit web resources are available on the Microsemi website:
The SmartFusion Development Kit Board is designed to pro vide a development platform for users to
evaluate all the features of the world’s only customizable system-on-chip (cSoC) with a hard ARM
Cortex-M3 processor powered microcontroller subsystem (MSS) along with programmable analog.
The board supports a SmartFusion cSoC device in an FG484 package. To enable the MSS, analog, and
evaluation of features, the board includes the following:
•Ethernet, EtherCAT, and USB-to-UART interface for communication with Ethernet and UART
peripherals of the SmartFusion MSS
•Static random access memory (SRAM), parallel flash, SPI flash, and electrically erasable
programmable read-only memory (EEPROM) that interface with EMC, SPI, and I2C peripherals of
the SmartFusion MSS
•Digital-to-analog converter (DAC) that interfaces either to SPI port 0 or SPI port 1 of the
SmartFusion MSS
•Organic light-emitting diode (OLED) that interfaces with either SPI or I
SmartFusion MSS
•I2C interface and temperature monitoring
•Mixed signal header for daughter card interfacing
•RealView ICE Simulation Unit (RVI) header for application programming and debug from either
®
Keil
ULINK® or IAR J-link
The board includes a FlashPro4 programming header to enable programming and debugging from
Microsemi design tools FlashPoint and SoftConsole.
®
2
C peripherals of the
6Revision 7
SmartFusion Development Kit
Table 2 describes SmartFusion Development Kit Board Components.
.
Table 2 • SmartFusion Development Kit Board Components
NameDescription
A2F500M3G-FGG484ES Microsemi SmartFusion cSoC with hard ARM Cortex-M3 processor
CURRENT SENSINGCurrent monitoring using thumbwheel POT (RV1)
PWM CIRCUITPulse Width Modulation Resistor Capacitor (PWMRC) circuit
OBDThree one-bit DACs used in comparator
OLED DISPLAYOrganic 96×16 pixel
white OLED PMO18701 with option to interface to I
2
C port 0 or SPI
port 0 of the SmartFusion MSS
I2C EEPROM512 Kbit I
2
C EEPROM ST M24512-WMN6TP connected to I2C port 1 of the SmartFusion
MSS
SPI FLASH8 MByte SPI flash Atmel AT25DF641-MWH-T connected to SPI port 1 of the SmartFusion
MSS
SPI DAC12-bit SPI DAC AD5320 with option to interface either to SPI port 0 or SPI port 1 of the
SmartFusion MSS
OSC-5050 MHz clock oscillator
OSC-2020 MHz/20 PPM clock oscillator
OSC-3232.768 KHz low power oscillator
USB/UARTUSB-to-UART adapter chip CP2102 and connector interfacing with UART Port 0 of the
SmartFusion MSS
RS485RS485 with DB9 female connector interfacing with MAX3240CSA, connected to UART
port 1 of the SmartFusion MSS
ETHERNETRJ45 connector (Ethernet jack with magnetics) interfacing with National Semiconductor
10/100 PHY chip DP83848C in RMII mode, interfacing with Ethernet port of the
SmartFusion MSS (on-chip MAC and external PHY)
®
AGLP125-CS289IGLOO
PLUS FPGA implementing level converter between 3.3 V and 1.8 V to connect
1.8 V PSRAM/flash with external memory controller (EMC, which has native voltage level
of 3.3 V) of the SmartFusion MSS
EXPANSIONWhen external memory controller (EMC) is not used, the I/Os are available as
3.3 V GPIOs.
Asynchronous SRAMTwo 16-Mbit SRAM Cypress CY7C1061DV33-10ZSXI connected to each region of the
EMC interface of the SmartFusion MSS
FLASH Two 64-Mbit parallel flash memory Numonyx JS28F640J3D-75 connected to each region
of the EMC interface of the SmartFusion MSS
LG_PSRAM128-Mbit, 1.8 V asynchronous PSRAM Micron MT45W8MW16BGX connected to the EMC
interface of the SmartFusion MSS. This provides the option of bigger memory as an
alternative to the SRAM for memory intensive applications.
LG_FLASH128-Mbit, 1.8 V, parallel flash memory Numonyx JS28F128P30T85 873824 connected to
the EMC interface of the SmartFusion MSS. This provides the option of bigger memory as
an alternative to the flash for memory intensive applications.
CAN_IFTwo CAN interfaces with DB9 female connector interfacing with MAXIMMAX3051 CAN
transceiver connected to four GPIOs of the SmartFusion MSS
Revision 77
Introduction
Table 2 • SmartFusion Development Kit Board Components (continued)
NameDescription
ETHERCAT_IFTwo RJ45 connectors (Ethernet jack with magnetics) for EtherCAT ports interfacing with
Beckhoff ET1 100 and Micrel KS8721BL and connecting to the SmartFusion cSoC via soft
SPI implemented in the fabric using six general purpose I/Os
RVI HEADERRVI header for application programming an d debug from Keil ULINK or IAR J-Link
FP4 Programming
HEADER
Flashpro4 programming header for FPGA and cSoC programming and debugging with
Microsemi tools
PROG HDRDirect-C programming header
TEMP DIODETemperature diode
BATT BACKUPBattery backup circuit
DIPSWITCHTwo 4-switch DIP switch packs for GPIO
LEDSFour active Low LEDs that can be connected to any user I/O for debug to power-on the
board
PUSH-BUTTON RESET Push-button system reset for SmartFusion System
MIXED_CONN100To power-on the board mixed signal header
PUSH-BUTTON
Six push-button switches for test and navigation and PUB
SWITCHES
MIXED_CONN100Mixed signal header
A2F500_CONN100Microsemi SmartFusion A2F500M3F-FG484ES additional I/O connector
8Revision 7
1 – Installation and Settings
Software Installation
Download and install the latest release of Microsemi Libero® Integrated Design Environment (IDE), v9.0
or later, from the Microsemi website and register for your free Gold license. For instructions on how to
install Libero IDE and SoftConsole, refer to the Libero IDE Installation and Licensing Guide, available on
the Microsemi website. Refer to the Installing IP Cores and Drivers User’s Guide for download and
installation of Microsemi DirectCores, SGCores, and Driver firmware cores that must be localized on the
personal computer where Microsemi's Libero IDE is installed when designing with Microsemi FPGAs and
cSoCs. Microsemi has partnered with key industry leaders in the microcontroller space to provide the
robust SmartFusion ecosystem. Microsemi SmartFusion is supported by the latest release of IAR
Systems, the IAR Embedded Workbench for ARM. Refer to Designing SmartFusion with IAR Systems
document for more information. The Microsemi SmartFusion cSoC is also supported by the latest
release of Keil, the MDK-ARM Microcontroller Development Kit. Refer to the Designing SmartFusion with
Keil document for more information.
Hardware Installation
The FlashPro4 (FP4) programmer plugs directly into the A2F500-DEV-KIT-2 board. This allows
programming A2F500 and AGLP125 devices in chain mode or individually with appropriate jumper
settings (JP5).
Jumpers, Switches, LEDs and DIP Switch Settings
The recommended default jumpers, switches, LEDs, and dual in-line package (DIP) switch settings are
shown in Figure 1-1 and defined in Table 1-1 on page 10 through Table 1-4 on page 13. Connect the
jumpers with the default settings to enable the pre-programmed demonstration design to function
correctly.
IGLOO PLUS Header
Memory Device
Configuration Headers
AGLP DIP Switch
AGLP Header
Power Jack
SmartFusion Device
DirectC Header
Board Reset Switch
RJ45 Connector for
10/100 Ethernet
RJ45 Connectors for
EtherCAT Ports
10/100 Ethernet PHY
PSRAM
(1.8 V)
POT for
Current Monitor
AGLP125V5-
CSG289
EtherCAT
PHYs
A2F500
Connector
Mixed-Signal
Header
EtherCAT
ASIC
SRAM
(3.3 V)
DACOUT/
ADC Headers
DB9 Connector
for CAN0
Callibration POTs for
±15 V Bipolar Outputs
Transceivers
DAC0 and DAC1
CAN
DB9 Connector
for CAN1
DIP Switch
®
RealView
JTAG MUX
JTAG_SEL Switch
FlashPro Header
LCPS Connector
JTAG Chain Configuration Header
1.5 V Header
DB9 Connector for RS485 (UART1)
PUB Switch
RS485 Transceiver
50 MHz Oscillator
USB Connector for UART0
2
C Headers
I
SPI Headers
OLED
Push-Button
Switches
Header
Figure 1-1 • Jumper Locations
Revision 79
Installation and Settings
Table 1-1 • Jumper Settings
JumperFunctionDefault SettingNotes
JP1Jumper to select first 3.3 V power supply for board1–2 Closed
JP2Jumper to select second 3.3 V power supply for board1–2 Closed
JP3Jumper for SPI DAC output VOUT Open
JP4Jumper settings to use comparator Pins 2, 6,10 are
Pin 3–4 = DACOUT0 to ADC0 Open
connected to
AGND
Pin 7–8 = DACOUT1 to ADC1Open
Pin 1–3 = DACOUT0 to OBD_DACOUT0Closed
Pin 7–9 = DACOUT1 to OBD_DACOUT1Closed
JP5Jumper for JTAG device option (A2F500 and AGLP125)
Pin 1–3 = A2F500 in chainOpen
Pin 1–2 and Pin 4-3 = A2F500 and AGLP125 daisy chainedClosed
JP6Jumper to select either 1.5 V external regulator or SmartFusion
cSoC device 1.5 V internal regulator
Pin 1–2 = 1.5 V internalOpen
Pin 3–2 = 1.5 V externalClosed
JP7Jumper to select between RVI header or LCPS header for
application debug
Pin 1–2 = LCPS for SoftConsoleClosed
Pin 2–3 = RVI for Keil U-link/ IAR J-linkOpen
2
J7Jumper/Header for SPI_0, I
C, EEPROM, OLED, and I2C
loopback
I2C0 to OLED
Pin 2–3 = I2C_0_SCL to OLED_SCLClosedConfiguration 1:
Pin 14–15 = I2C_0_SDA to OLED_SDA_INClosed
I2C0 -> OLED and
I2C1 -> EEPROM
I2C1 to EEPROM
Pin 6–7 = I2C_1_SCL to EEPROM_SCLClosed
Pin 10–11 = I2C_1_SDA to EEPROM_SDAClosed
I2C0 and I2C1 LoopbackConfiguration 2:
Pin 2–6 = I2C_0_SCL to I2C_1_SCLOpen
I2C0 <-> I2C1
(Loop Back)
Pin 10–14 = I2C_1_SDA to I2C_0_SDAOpen
SPI to OLEDConfiguration 3:
Pin 3–4 = SPI_SCK to OLED_SCLOpen
SPI -> OLED and
I2C1 -> EEPROM
Pin 15–16 = SPI_SDA to OLED_SDAOpen
I2C1 to EEPROM
Pin 6–7 = I2C_1_SCL to EEPROM_SCLClosed
Pin 10–11 = I2C_1_SDA to EEPROM_SDAClosed
JP8Jumper/Header for SPI, OLED, SPI flash, and loopback
SPI_0 to OLED
Pin 1–2 = SPI_0_OUT to OLED_SDA_IN (Need shunt pin 15–
OpenConfiguration 1:
16 jumper on J7)
Pin 5–6 = SDI_0_IN to OLED_SDA_OUTOpen
Pin 9–10 = SCLK_0_OUT to OLED_SCL (Need shunt pin 3–4
Open
jumper on J7)
Pin 13–14 = SS_0_OUT to OLED_CS#Open
SPI_1 to SPI flash
Pin 3–4 = SDI_1_IN to SPI_1_SO (SO output of SPI flash)Closed
Pin 7–8 = SDO_1_OUT to SPI_1_SI (SI input of SPI flash)Closed
Pin 11–12 = SCLK_1_OUT to SPI_1_SCK (SCK input of SPI
Closed
flash)
Pin 15–16 = SS_1_OUT to SPI_CS_N (CS# input of SPI flash)Closed
SPI0 to SPI1 (loopback)Configuration 2:
Pin 2–3 = SDO_0_OUT to SDI_1_INOpen
Pin 6–7 = SDI_0_IN to SDO_1_OUTOpen
Pin 10–11 = SCLK_0_OUT to SCLK_1_OUTOpen
Pin 14–15 = SS_0_OUT to SS_1_OUTOpen
JP11Jumper to connect 3.3 V to VJTAG1–2 Closed
JP12Jumper to connect 3.3 V to VPUMP1–2 Closed
JP13VREF_OUT to OP_AMP (U44A & U51A) positive1–2 Closed
JP14OP_AMP (U44C) output to ABPS0 of FPGA fabric1–2 Open
SPI_0 to OLED
and SPI_1 to SPI
flash
SPI0 and SPI1
loopback
JP15OP_AMP (U44C) output to ABPS4 of FPGA fabric1–2 Open
JP16Jumper to control F*F of AGLP125 device
Pin 1–2 = F*F connected to 3.3 V (deasserted)Open
Pin 2–3 = F*F connected to GND (asserted)Closed
JP17Jumper to select between 1.8 V and 3.3 V memory Interface
connected to region 0 of EMC
Pin 1–2 = 1.8 V interfaceOpen
Pin 2–3 = 3.3 V interfaceClosed
To keep 3.3 V
devices tristated
Revision 711
Installation and Settings
Table 1-1 • Jumper Settings (continued)
JumperFunctionDefault SettingNotes
JP18Jumper to connect OLED_SDA_OUT and OLED_SDA_IN
2
Pin 1–2 = Closed for I
C configuration modeClosed
Pin 1–2 = Open for SPI mode
JP19Jumper to select between 1.8 V and 3.3 V memory interface
connected to EMC
To keep 3.3 V
devices tristated
Pin 1–2 = 1.8 V interfaceOpen
Pin 2–3 = 3.3 V interfaceClosed
JP20Jumper to select positive 10 V power supply for boardClosed
JP21OP_AMP (U51C) output to ABPS1 of FPGA fabric1–2 Open
JP22Jumper to connect OLED_BS1 (MCU interface selection Input)
to 3.3 V or GND
2
Pin 1–2 = 3.3 V (needed for I
C mode)Open
Pin 2–3 = GND (needed for SPI mode)Closed
JP23Jumper to connect OLED_BS2 (MCU interface selection input)
to 3.3 V or GND
Pin 1–2 = 3.3 V Closed
Pin 2–3 = GND (needed for both I2C & SPI modes)Open
JP24Jumper to connect FLASH_VPEN of 64-Mbit parallel flash
connected to both regions of EMC
Identified as
FLASH
Pin 1–2 = FLASH_VPEN to 3.3 V (enabled)Closed
Pin 2–3 = FLASH_VPEN to GND (disabled)Open
JP25Jumper to connect FLASH_WP# of 128-Mbit parallel flashIdentified as
Pin 1–2 = FLASH_WP# to 1.8 V (disabled)Open
LG_FLASH
Pin 2–3 = FLASH_WP# to GND (enabled)Closed
JP26Jumper to connect WE_N of EEPROM to 3.3 V
Pin 1–2 = 3.3 V (EEPROM write disabled)Closed
JP27 OP_AMP (U51C) output to ABPS5 of FPGA fabric
JP28Jumper to select 1.8 V power supply for board1–2 Closed
JP30Jumper to connect VJTAG of PROG HDR to 3.3 VOpen
JP31Jumper to connect VPUMP of PROG HDR to 3.3 VOpen
J32VAREFOUT to ADC0, ADC1, ADC2 VAREF inputs
1–2 VAREFOUT to VAREF0Closed
3–4 VAREFOUT to VAREF1Closed
5–6 VAREFOUT to VAREF2Closed
12Revision 7
SmartFusion Development Kit
Table 1-2 • SmartFusion Development Kit LEDs
LEDSmartFusion PinComment
D1B19Test LED for user application
D2B20Test LED for user application
D3C19Test LED for user application
D4H17Test LED for user application
D5N/A5 V Power Supply Indicator LED. This LED is ON when board is powered on
D6N/ASPEED LED: The LED is ON when device is in 100 Mbps and OFF when in 10 Mbps.
D8N/AUART over USB link indicator LED
Table 1-3 • SmartFusion Development Board DIP Switches
DIP Switch (S1)SmartFusion PinComment
DIP1H20Test switch for user application
DIP2C21Test switch for user application
DIP3D21Test switch for user application
DIP4F19Test switch for user application
Table 1-4 • SmartFusion Development Kit Test Points
T est PointComment
TP1, TP12 5 V power supply (measures 4.3 V due to diode drop)
TP2, TP5, TP6, TP7, TP8Digital ground (GND)
TP3, TP4, TP13Analog ground (AGND)
TP910 V rail for OLED
TP103.3 V supply for SmartFusion
TP113.3 V analog supply
Table 1-5 • SmartFusion Development Kit Push-Button Switches
Push-Button SwitchSmartFusion PinComment
SW1G19Test and navigation switch
SW2G20Test and navigation switch
SW3G21Test and navigation switch
SW4E1Tes t and navigation switch
SW5E14Test and navigation switch
SW6N/ASwitch ON 5 V DC into SmartFusion cSoC device regulators
SW7 W7Push-button switch for PUB. This negative active switch is connected to
the PUB pin, which is a digital input to the FPGA fabric. PUB is the
connection for the external momentary switch used to turn on the 1.5 V
voltage regulator.
SW8R1System reset for DUT
SW9R16 (JTAGSEL)Switch to select A2F500 programming with FlashPro4 or Cortex-M3
processor debug. OFF position selects A2F500 programming and ON
position selects Cortex-M3 processor for application debug.
Revision 713
Installation and Settings
Testing the Hardware
If the board is shipped directly from Microsemi, it contains a test program that determines whether the
board works properly. If while using the board you suspect that the board is damaged, you can rerun the
"Manufacturing Test" on page 79 to verify the key components of the board functionality.
14Revision 7
2 – Hardware Components
SmartFusion cSoC Description and Connections
The SmartFusion Development Kit Board is populated with a SmartFusion A2F500M3G-FGG484ES, the
world’s only cSoC with hard ARM Cortex-M3 processor. The key features of the SmartFusion cSoC are
listed below and in Table 2-1 on page 16.
The MSS consists of the following:
•100 MHz 32-Bit ARM Cortex-M3 1.25 DMIPS/MHz throughput from zero wait state memory
•Internal memories
– Embedded flash memory (eNVM), 64 Kbytes to 512 Kbytes
– Embedded high-speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, implemented in two physical
blocks to enable simultaneous access from two different masters
•Multi-layer AHB communications matrix
– Provides up to 16 Gbps of on-chip memory bandwidth
•10/100 Ethernet MAC with RMII interface
•Programmable external memory controller, which supports:
– Asynchronous memories
– NOR flash, SRAM, PSRAM
– Synchronous SRAMs
•Two I
•Two 16550 compatible UARTs
•Two SPI peripherals
•Two 32-bit timers
•32-bit watchdog timer
•8-Channel DMA controller
•Clock sources
•High-performance FPGA fabric
•Based on Microsemi's proven ProASIC
•Analog front-end (AFE)
•Up to three 12-Bit SAR ADCs
•One first-order ΣΔ DAC (sigma-delta) per ADC
•Up to five new high-performance analog signal conditioning blocks (SCB) per device
•Two high-speed comparators
•Analog compute engine (ACE)
2
C peripherals
– 1.5 MHz to 20 MHz main oscillator
– Battery-backed 32 KHz low-power oscillator with real-time counter (RTC)
– 100 MHz embedded RC oscillator 1% accurate
– Embedded PLL with 4 ou tput phases
®
3 FPGA fabric
– Offloads CPU from analog initialization and processing of ADC, DAC, and SCBs
– Sample sequence engine for ADC and DAC parameter set-up
– Post-processing engine for functions such as low-pass filtering and linear transformation
Revision 715
Hardware Components
Table 2-1 • A2F500 I/Os
DevicePackage
A2F500FG484
Direct analog input12
Total analog input32
Total analog output3
MSS I/Os
FPGA I/Os128
Total I/Os204
Notes:
1. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if no t needed for the MSS. These I/Os support
2. 9 MSS I/Os are primarily for 10/00 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if
1, 2
Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, and 3.3 V) standards.
Ethernet MAC is not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS
(1.5 / 1.8 / 2.5, and 3.3 V) standards.
41
Figure 2-1 • SmartFusion Block Diagram
I/O Pin Connections
The pin list is provided in the "Pin List" section on page 61.
16Revision 7
SmartFusion Development Kit
SmartFusion cSoC Hard ARM Cortex-M3 Processor
The SmartFusion cSoC comes with a hard Cortex-M3 advanced processor-based MSS. The ARM
Cortex-M3 microcontroller is a low power processor that features low gate count, low predictable
interrupt latency, and low-cost debug. It is intended for deeply embedded applications that require fast
interrupt response features. SmartFusion cSoCs use the R1P1 version of the Cortex- M3 processor core.
Some of the important subsystems are listed below:
•Memory protection unit (MPU)
•Single-cycle multiplication and hardware divide
•JTAG debug (4 wire), Serial Wire Debug (SWD – 2 wire) and serial wire viewer (SWV) interfaces
The development board is populated with components to enable development using the MSS. These
components include SRAM, PSRAM, flash, SPI flash, I2C, EEPROM, OLED, SPI DAC, communication
interfaces such as Ethernet, and USB-to-UART.
Revision 717
Hardware Components
Power Sources
This board is powered through an external 5 V power supply brick.
SmartFusion Power Sources
Seven voltage rails (10 V, 5 V, 3.3 V, 1.8 V, 1.5 V, and ± 15 V) are provided on the board:
•A single regulator, Linear LT3684EMSE (3.3 V, 2 A), supplies both analog and digital 3.3 V going
to the SmartFusion cSoC device. Sufficient isolation is provided through low-pass filter and layout
to prevent noise from the digital domain to propagate to the analog domain.
•Linear LT3684EMSE (1.8 V, 2 A), supplies 1.8 V rails.
•Linear LT3684EMSE (1.5 V, 2 A), supplies 1.5 V rails.
•Linear LT1615 step-up converter supplies 10 V, 100 mA typical, for driving OLED.
•A single regulator, Linear L T1615, supplies both the +15 V and –15 V with 4 mA rating required by
the DAC comparators.
18Revision 7
3 – Components Description and Operation
VAREF_OUT
VAREF_1
VAREF_OUT
VAREF_OUT
VAREF_OUT
VAREF_0
VAREF_1
VAREF2
VAREF2
VAREF_0
AGND
AGND
AGND
AGND
AGND
C63
10uF
C63
10uF
12
J5
HEADER 1x2
J5
HEADER 1x2
2
4
6
1
3
5
J32
HEADER 3X2
J32
HEADER 3X2
C62
10uF
C62
10uF
1
J2
HEADER 1
J2
HEADER 1
12
J6
HEADER 1x2
J6
HEADER 1x2
C61
10uF
C61
10uF
C79
10uF
C79
10uF
12
J8
HEADER 1x2
J8
HEADER 1x2
VAREF Connections
The SmartFusion cSoC has one external VAREF input pin for each of the ADCs. The internal VAREF is
brought out as an output, available as VAREFOUT output pin. There are multiple options available to
drive the VAREF0 and VAREF1 from either external VAREF or the internal VAREF through VAREFOUT
output of the FPGA fabric.
Figure 3-1 • VAREF Jumper Selections
Table 3-1 • Use as Internal VAREF
JumperFunction
J321–2 VAREFOUT to VAREF0
Notes:
VAREF0 corresponds to ADC[3:0], CM[1:0], TM[1:0]
VAREF1 corresponds to ADC[7:4], CM[3:2], TM[3:2]
VAREF2 corresponds to ADC[11:8], CM4, TM4 (A2F500 only)
3–4 VAREFOUT to VAREF1
5–6 VAREFOUT to VAREF2
Revision 719
Components Description and Operation
Table 3-2 • Using External VAREF
VAREFJumper SettingsComment
VAREF0 J32: 1–2Open
Connect external voltage across J8 pins 1–2Do not place a jumper on J8
VAREF1J32: 3–4Open
Connect external voltage across J5 pins 1–2Do not place a jumper on J5
VAREF2J32: 5–6Open
Connect external voltage across J6 pins 1–2Do not place a jumper on J6
Note: You need an external VAREF to monitor voltages greater than 2.56 V on the DC/AC/AT channels. An internal
VREF is sufficient to monitor voltages less than 2.56 V on the ADC/AC/AT channels. All ABPS channels can
monitor voltages greater than 2.56 V using an internal VREF.
Current Sensing Circuit
For applications using the embedded current monitor, a current sensing circuit is provided on the
SmartFusion Development Kit board. The current monitoring is performed across AC0 and AT0 pins of
the SmartFusion cSoC device. The voltage across the potentiometer can be monitored via the AT0 pin.
The current sensing circuits is for the 3.3 V voltage rail as shown in Figure 3-2.
3
RV1
RV1
Figure 3-2 • Current Sensing
Note: The current monitoring circuit on the SmartFusion Development Kit board is connected to the
SmartFusion cSoC devices CM0 and TM0 inputs. CM0 can also be used to monitor the voltage
across the potentiometer. This input does not have a prescaler circu it. Because of the value chosen
for the potentiometer, the full-scale input is reached after turning the potentiometer about one
quarter of the maximum travel. Although this will not damage the SmartFusion cSoC device, you
may notice the potentiometer is very sensitive.
PWM Circuit
The PWM RC circuit depicted in Figure 3-3 and Figure 3-4 on page 21 can be used with Microsemi
CorePWM instantiated in the FPGA fabric to generate various voltage waveforms. These voltage
waveforms can be displayed on the OLED or used via the mixed signal header. In addition, one PWM RC
circuit source is routed to the AV input pin of an analog quad. This AV pin can be used to monitor the
generated voltage with high accuracy, depending on the ADC resolution configured in the FPGA fabric.
CURRENT MONITORING
AT0
2
1
R6
50K
50K
R6
AC0
100,1%
100,1%
R7
R7
5.36k
5.36k
S5BC-13-F
S5BC-13-F
D22
D22
V3P3
20Revision 7
Figure 3-3 shows the A2F500 pins driving PWM and the PWM circuit.
PWM0PWM1
F2-200-IO_8
F2-200-IO_6
F2-200-IO_7
DACOUT0{6}
AC4{6}
AC2{6}
AC3{6}
AV1_1{6}
DACOUT1 {6}
AT2 {6}
AT3 {6}
AV2_1 {6}
ATGND1 {6}
AT4 {6}
ATGND2 {6}
F2-200-4-FPGAIO
F2-200-6-FPGAIO
35
F2-200-7-FPGAIO
37
F2-200 PWM0
39
DGND8
41
AGND1
43
OBD0
45
AGND3
47
AC2
49
AGND5
51
AC3
53
AGND6
55
AC4
57
AGND8
59
AV1_1
61
63
F2-200-5-FPGAIO
DGND7
36
F2-200-8-FPGAIO
38
F2-200 PWM1
40
DGND9
42
AGND2
44
OBD1
46
AGND4
48
AT2
50
ATGND1
52
AT3
54
AGND7
56
AT4
58
ATGND2
60
AV2_1
62
64
PWM0
PWM1
F2-200-PWM1
F2-200-PWM0
C284
220nF
C284
220nF
R3164.7KR3164.7K
C283
220nF
C283
220nF
R3144.7KR3144.7K
R289100KR289100K
R281
100K
R281
100K
V3P3
V3P3
MSS_SYSRESETB {8,9,15,20,21,27}
Mfr P/N :DS1818R-10+T&R
Mfr: Dallas
RST
Mfr P/N :EVQ-PAD04M
Panasonic - ECG
Notes;
R35 need to place at U15
1
2
3
4
SW8
EVQ-PAD04M
SW8
EVQ-PAD04M
VCC
2
GND
3
RST
1
U15
DS1818
U15
DS1818
R34
10K
R34
10K
C74
1uF
C74
1uF
C73
0.1uF
C73
0.1uF
R3539R35
39
Figure 3-3 • PWM Pins
SmartFusion Development Kit
Figure 3-4 • PWM Circuit
Push-Button System Reset
A push-button system reset switch with a Schmitt trigger is provided on the board (Figure 3-5). The
Schmitt trigger reduces noise on the system reset push-button. SmartFusion MSS reset is synchronized
with this reset.
In addition, the board includes five push-button switches that are connected to pins G19, G20, G21, E1,
and F14 of the SmartFusion cSoC.
U7-17
U7-17
LED1_N
LED2_N
LED3_N
LED4_N
DIP1
DIP2
DIP3
B19
GBB0/IO18NDB0V0
B20
GBB1/IO18PDB0V0
C19
GBA0/IO19NPB0V0
H17
IO25NDB1V0
H20
GCC0/IO26NPB1V0
C21
GBC2/IO21PDB1V0
D21
IO21NDB1V0
F2-200/500-FGG484
F2-200/500-FGG484
Figure 3-10 • LED, DIP, and Push-Button I/Os
S1
8
7
6
5
A2F_DIPS1A2F_DIP
LED , DIP & PB
LED , DIP & PB
GCA2/IO23PDB1V0
GCB2/IO24PDB1V0
GFC2/IO67PPB5V0
GBC0/IO17NPB0V0
IO23NDB1V0
IO24NDB1V0
DIP1
DIP2
DIP3
DIP4
F19
G19
G20
G21
E1
E14
DIP4
SWITCH1
SWITCH2
SWITCH3
SWITCH4
SWITCH5
Revision 723
Components Description and Operation
One-Bit DAC (OBD) Circuit
For applications that require conversion from a digital to analog domain , two analog conditi oning circui ts
are provided. This is useful in closed-loop applications. Figure 3-11 shows the circuit. Table 3-5 on
page 25 and Table 3-6 on page 26 show the jumper settings.
VAREF_OUT{6}
OBD_DACOUT0
{6}
AGND
OBD_DACOUT1{6}
AGND
JP13
JP13
12
HEADER 1x2
HEADER 1x2
R1401K,1%R1401K,1%
VREF_OUT
R1511K,1%R1511K,1%
VREF_OUT
1P15V
U44A
U44A
2
-
-
3
+
+
1N15V
1P15V
U44B
U44B
5
+
+
6
-
-
1N15V
R139 500,1%R139 500,1%
1P15V
U51A
U51A
2
-
-
3
+
+
1N15V
1P15V
U51B
U51B
5
+
+
6
-
-
1N15V
R152 500,1%R152 500,1%
411
AD824ARZ-14
AD824ARZ-14
AD824ARZ-14
AD824ARZ-14
114
13
411
AD824ARZ-14
AD824ARZ-14
AD824ARZ-14
AD824ARZ-14
114
13
R1475.8K,1%R1475.8K,1%
1P15V
411
U44C
U44C
AGND
R178
R178
5.8K,1%
5.8K,1%
10
13
12
9
-
-
+
+
AD824ARZ-14
AD824ARZ-14
1N15V
MANUFACTURER P/N = AD824ARZ-14
MANUFACTURER P/N = AD824ARZ-14
1P15V
MANUFACTURER = Analog Devices Inc
MANUFACTURER = Analog Devices Inc
C161
C161
411
U44D
1N15V
U44D
-
-
+
+
AD824ARZ-14
AD824ARZ-14
C162
C162
0.01uF
0.01uF
0.01uF
0.01uF
8
AGND
14
1
7
2
1K
R211K,1%R211K,1%
R221K,1%R221K,1%
RV21KRV2
JP14
JP14
JP15
JP15
12
HEADER 1x2
HEADER 1x2
12
HEADER 1x2
HEADER 1x2
AV1_0 {6}
AV1_2 {6}
AGND
R1485.8K,1%R1485.8K,1%
1P15V
411
U51C
U51C
AGND
R179
R179
5.8K,1%
5.8K,1%
9
-
-
10
+
+
AD824ARZ-14
AD824ARZ-14
1N15V
1P15V
411
U51D
U51D
13
-
-
12
+
+
AD824ARZ-14
AD824ARZ-14
MANUFACTURER P/N = AD824ARZ-14
MANUFACTURER P/N = AD824ARZ-14
1N15V
MANUFACTURER = Analog Devices Inc
MANUFACTURER = Analog Devices Inc
C163
C163
0.01uF
0.01uF
8
C164
C164
0.01uF
0.01uF
AGND
14
1
7
2
R149 1K,1%R149 1K,1%
R150 1K,1%R150 1K,1%
RV31KRV31K
JP21
JP21
JP27
JP27
12
HEADER 1x2
HEADER 1x2
12
HEADER 1x2
HEADER 1x2
AV2_0 {6}
AV2_2 {6}
AGND
Figure 3-11 • OBD_DACOUT
The OBDs can be used in two applications.
These circuits take the OBD output of the SmartFusion quad and feed it back to the SmartFusion analog
inputs of ADC0 and ADC1 (Table 3-3). This is useful in closed-loop applications.
Table 3-3 • OBD Output to Loopback to ADC
JumperPinFunction
JP43-4DACOUT0 to ADC0
7-8DACOUT1 to ADC1
24Revision 7
SmartFusion Development Kit
The OBDs can also be fed into a voltage gain circuit as shown in Figure 3-11 on page 24 and described
in Table 3-4. In this application, the OBD sweep of 0–2.56 V can be translated to –15 V to +15 V. This is
useful in closed-loop applications for ABPS channels with prescalers.
Table 3-4 • OBD Connections for Voltage Gain
JumperPinPin
JP41–3DACOUT0 to OBD_DACOUT0
7–9DACOUT1 to OBD_DACOUT1
JP131–2Connect VAREF_OUT to bias the opamp
The output of the Opamp can be configured to be monitored by the ABPS channel (Table 3-5). This can
be done as below:
Table 3-5 • Output of the Opamps to ABPS Channels
JumperPinPinFunction
JP1412OP_AMP (U44C) output to ABPS0 of FPGA fabric
JP1512OP_AMP (U44C) output to ABPS4 of FPGA fabric
JP2112OP_AMP (U51C) output to ABPS1 of FPGA fabric
JP2712OP_AMP (U51C) output to ABPS5 of FPGA fabric
OLED Display
A 9616-pixel low-power OLED is made available on the board for display. This low-power device, WHITE
OLED, requires 3.3 V and 10 V power supplies. Either one of the SmartFusion MSS I2C0 or SPI0 can be
interfaced with the OLED.
The OLED displays sharp gaming images or text. For example, the SmartFusion RTC current time or
time between two events can be displayed on the OLED. Figure 3-12 on page 26 shows the OLED
connections on the board along with jumpers for BS1 and BS2 and the jumper settings for accessing the
OLED from SPI0.
Revision 725
Components Description and Operation
OLED_BS1OLED_BS2
OLED_BS1OLED_BS2
OLED_CS#
V3P3
V3P3V3P3
V10P
V3P3
OLED_D/C#{27}
MSS_SYSRESETB{8,12,15,20,21,27}
OLED_SCL {10}
OLED_SDA_OUT {10,11}
OLED_SDA_IN {10}
OLED_CS#
{11}
SCL
SDA
Mfr P/N :PMO13701
Mfr: PACER
Mfr P/N :3-644456-3
Mfr:Tyco Electronics
Mfr P/N :3-644456-3
Mfr:Tyco Electronics
TANT
R202MR20
2M
+
C67
4.7uF 25V
+
C67
4.7uF 25V
C68
0.01uF
C68
0.01uF
R201
10K
R201
10K
R17
10K
R17
10K
1
2
3
JP22JP22
R202
10K
R202
10K
R1651KR165
1K
R203
10K
R203
10K
R18
10K
R18
10K
1
2
3
JP23JP23
R3651KR365
1K
R207
10K
R207
10K
R19
10K
R19
10K
C69
1uF
C69
1uF
VCC
30
VCOMH
29
IREF
28
VDD
11
BS1
12
BS2
13
NC11NC28NC39NC410NC514NC6
31
VSS
2
TEST1
7
TEST2
6
TEST3
5
TEST4
4
TEST5
3
D0
20
D1
21
D2
22
D3
23
D4
24
D5
25
D6
26
D7
27
RD#
19
WR#
18
D/C#
17
RES#
16
CS#
15
U11
PMO13701
U11
PMO13701
Refer to the "Jumper Settings" section on page 26 for accessing the OLED from I2C0 and SPI0.
Figure 3-12 • OLED Connections
Jumper Settings
Table 3-6 • Interface MSS I2C0 to the OLED
JumperPinPinConnection Details
J723I2C_0_SCL to OLED_SCL
1415I2C_0_SDA to OLED_SDA_IN
JP1812Closed
JP2312OLED_BS1 connected to 3.3 V
JP2223OLED_BS2 connected to GND
Table 3-7 • Interface MSS SPI0 to the OLED
JumperPinPinConnection Details
J734SPI_SCK to OLED_SCL
JP812SPI_0_OUT to OLED_SDA_IN
JP1812Open
JP2323OLED_BS1 connected to GND
JP2223OLED_BS2 connected to GND
26Revision 7
1516SPI_SDA to OLED_SDA
56SDI_0_IN to OLED_SDA_OUT
910SCLK_0_OUT to OLED_SCL
1314SS_0_OUT to OLED_CS#
Figure 3-13 • JP8 Jumper Details
OLED_CS#
{9}
SPI_0_SCK
{10}
SDO_0_OUT
SDI_0_IN
SCLK_0_OUT
SS_0_OUT
SS_1_OUT
SCLK_1_OUT
SPI_1_SO
SPI_1_SI
SPI_1_SCK
SPI_CS_N
SDI_1_IN
SDO_1_OUT
SPI_0_SI
{10}
OLED_SDA_OUT{9,10}
2
3
4
6
7
8
10
11
12
14
15
16
1
5
9
13
JP8
HDR4X4
JP8
HDR4X4
SPI Configuration –1
SPI Port 0
SPI Port 1
OLED
SPI Flash
OLED
Display
SPI
Port 0
SPI
Port 1
SPI
Flash
OLED
Display
SPI
Port 0
SPI
Port 1
SPI
Flash
SmartFusion Development Kit
Figure 3-14 • MSS SPI0 and SPI1 Settings
Revision 727
Components Description and Operation
SPI_SO
V3P3
V3P3
SPI_CS_N
SPI_1_SI
SPI_1_SCK
SPI_1_SO
8 MByte
Mfr P/N : AT25DF641-MWH-T
Mfr: Atmel
R28
10K
R28
10K
R293
10K
R293
10K
SI
5
SCK
6
HOLD
7
CS
1
WP
3
VCC
8
GND
4
SO
2
U13
AT25DF641-MWH-T
U13
AT25DF641-MWH-T
C70
0.1uF 10V
C70
0.1uF 10V
R20639R20639
Table 3-8 • MSS SPI0 and MSS SPI1 Loopback and Off-Board SPI Device Connections
JumperPinSignalConnection Details
JP86SPI0_SDITo interface any SPI device to MSS SPI0
2SPI0_SDO
10SPI0_SCK
14SPI0_SS
3SPI1_SDITo interface any SPI device to MSS SPI1
7SPI1_SDO
11SPI1_SCK
15SPI1_SS
67MSS SPI0 and SPI1 loopback
23
1011
1415
SPI Flash
One 8-MByte SPI flash Atmel AT25DF641-MWH-T is also offered on the board. This can optionally be
interfaced to either the SPI0 or SPI1 peripherals of the SmartFusion MSS. Figure 3-15 and Figure 3-16
show the SPI flash circuit and the jumper settings to access it from SPI1.
JP834SDI_1_IN to SPI_1_SO (SO output of SPI flash)
78SDO_1_OUT to SPI_1_SI (SI input of SPI flash)
1112SCLK_1_OUT to SPI_1_SCK (SCK input of SPI flash)
1516SS_1_OUT to SPI_CS_N (CS# input of SPI flash)
28Revision 7
SPI DAC
One 12-bit SPI DAC AD5320 is available on the board. This can be optionally interfaced to either the
SPI0 or SPI1 of the SmartFusion MSS. Figure 3-16 shows the SPI DAC instance along with the header
that must be connected to the SPI_x_SDI, SPI_x_SCK, SPI_x_SS, and SPI_x_SDO pins of SPI0 or
SPI1.
One 512-Kbit I2C EEPROM ST M24512-WMN6TP is available on the board to interface with I2C Port1 of
the SmartFusion MSS. Alternatively the EtherCAT chip, Beckhoff ET1100, can interface with the
EEPROM.
Figure 3-17, and Figure 3-18 and Figure 3-19 on page 31 show the EEPROM connections, I2C interface,
and header with jumper settings for access to EEPROM.
Figure 3-17 • I2C EEPROM
Table 3-11 • To Interface MSS I2C1 to EEPROM
JumperPinPinConnection Details
J767I2C_1_SCL to EEPROM_SCL
1415I2C_1_SDA to EEPROM_SDA
JP26ClosedTo write protect EEPROM (WE_N)
30Revision 7
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