Microsemi MiV_RV32IMAF_L1_AHB User Manual

HB0801

MiV_RV32IMAF_L1_AHB V2.0

Handbook

11 2017

HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

Revision History

The revision history describes the changes that were implemented in the document. The changes
are listed by revision, starting with the most current publication.

1.1 Release 1.0

Revision 1.0 is the first production-level publication of this document. Created for
MiV_RV32IMAF_L1_AHB v2.0.

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

Contents

Revision History .............................................................................................................................. 3

1.1 Release 1.0 ................................................................................................................................................. 3

2 Introduction ............................................................................................................................. 8

2.1 Overview .................................................................................................................................................... 8

2.2 Features ..................................................................................................................................................... 9

2.3 Core Version ............................................................................................................................................... 9

2.4 Supported Families .................................................................................................................................... 9

2.5 Device Utilization and Performance .......................................................................................................... 9

3 Functional Description ........................................................................................................... 10

3.1 MiV_RV32IMAF_L1_AHB Architecture .................................................................................................... 10

3.2 MiV_RV32IMAF_L1_AHB Processor Core ................................................................................................ 11

3.3 Pipelined Architecture ............................................................................................................................. 11

3.4 Memory System ....................................................................................................................................... 12

3.5 Platform-Level Interrupt Controller ......................................................................................................... 12

3.6 Debug support through JTAG ................................................................................................................... 12

3.7 External AHB Interfaces ........................................................................................................................... 13

4 Interface ................................................................................................................................. 14

4.1 Configuration Parameters ........................................................................................................................ 14

4.1.1 MiV_RV32IMAF_L1_AHB Configurable Options ........................................................................ 14

4.1.2 Signal Descriptions .................................................................................................................... 14

5 Register Map and Descriptions .............................................................................................. 16

6 Tool Flow ................................................................................................................................ 17

6.1 License ..................................................................................................................................................... 17

6.1.1 RTL ............................................................................................................................................. 17

6.2 SmartDesign ............................................................................................................................................. 17

6.3 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign ............................................................................ 17

6.4 Debugging ................................................................................................................................................ 18

6.5 Simulation Flows ...................................................................................................................................... 18

6.6 Synthesis in Libero ................................................................................................................................... 19

6.7 Place-and-Route in Libero ........................................................................................................................ 19

7 System Integration ................................................................................................................. 20

7.1 Example System ....................................................................................................................................... 20

7.2 Reset Synchronization .............................................................................................................................. 20

7.2.1 RST ............................................................................................................................................. 20

7.2.2 TRST ........................................................................................................................................... 21

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

8 Design Constraints ................................................................................................................. 22

9 SoftConsole ............................................................................................................................ 24

10 Known Issues .......................................................................................................................... 25

10.1 Reset/Power Cycle the Target Hardware before each Debug Session ..................................................... 25

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

List of Figures

Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram ......................................................................................................... 8

Figure 2 MiV_RV32IMAF_L1_AHB Block Diagram ....................................................................................................... 11

Figure 3 Example Five Stage Pipelined Architecture ................................................................................................... 12

Figure 4 SmartDesign MiV_RV32IMAF_L1_AHB Instance View .................................................................................. 17

Figure 5 Configuring MiV_RV32IMAF_L1_AHB in SmartDesign .................................................................................. 18

Figure 6 RTG4 Example Simulation Subsystem............................................................................................................ 18

Figure 7 MiV_RV32IMAF_L1_AHB Example System .................................................................................................... 20

Figure 8 RST Reset Synchronization ............................................................................................................................. 21

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

List of Tables

Table 1 Device Utilization and Performance ................................................................................................................. 9

Table 2 MiV_RV32IMAF_L1_AHB Architecture ........................................................................................................... 10

Table 3 Example Pipeline Timing ................................................................................................................................. 12

Table 4 MiV_RV32IMAF_L1_AHB Configuration Options ............................................................................................ 14

Table 5 MiV_RV32IMAF_L1_AHB I/O Signals .............................................................................................................. 14

Table 6 Physical Memory Map (from E3 Coreplex Series) ........................................................................................... 16

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HB0801: MiV_RV32IMAF_L1_AHB V2.0 Handbook

MiV_RV32IMAF_L1_AHB

JT AG I/F

External

Interrupts

AHB Memo ry I/F

AHB M MIO I/F

Debug

Transport

Module

Debug Module

E31 Cor e

Uncached TileLink Interconnect

TileLink to

AHB B ridg e

TileLink to

AHB B ridg e

Plat form-Level Interrupt

Controller

8 KB Instruction Cache

RV 32IM AF

Integer Mul tiplier/Divide r

8 KB D ata C ache

2 Introduction

2.1 Overview

The MiV_RV32IMAF_L1_AHB is a softcore processor designed to implement the RISC-V instruction
set for use in Microsemi FPGAs. The processor is based on the Coreplex E31 designed by SiFive,
containing a high-performance single-issue, in-order execution pipeline E31 32-bit RISC-V core. The
core includes an industry-standard JTAG interface to facilitate debug access, along with separate
AHB bus interfaces for memory access and support for 31 dedicated interrupt ports.

Figure 1 MiV_RV32IMAF_L1_AHB Block Diagram

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