Microsemi SmartFusion2, M2S025, M2S050, M2S060, M2S090 User Manual
...
UG0445
User Guide
SmartFusion2 SoC FPGA and IGLOO2 FPGA Fabric
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50200445 . 7.0 4/19
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Revision 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Revision 5.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.5 Revision 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.6 Revision 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.7 Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.8 Revision 0.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Fabric Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Fabric Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.1 Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.2 Interface Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.3 I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.4 FPGA Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Fabric Array Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 LSRAM Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3.1 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Two-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.1 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.4 Block Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.5 Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6 How to Use LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.6.2 LSRAM Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4 Micro SRAM (µSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2 µSRAM Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3.2 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3.3 Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 iii
4.4.1 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4.2 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.5 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.5.1 Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.6 How to Use µSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.6.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Math Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Math Block Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.1 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.4 How to Use Math Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4.2 Math Block Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.4.3 Coding Style Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6 I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.1 Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.2 Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.3 Low-Power Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.4 On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3 I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4 Simultaneous Switching Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4.1 GND Bounce and V
6.5 Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.5.1 Single-Ended Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.5.2 Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.5.3 Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.6 I/O Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.6.1 Programmable Slew-Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.6.2 Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6.3 Programmable Weak Pull-Up and Pull-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.6.4 Programmable Schmitt Trigger Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6.5 Programmable Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6.6 Bus Keeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.7 Receiver ODT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.7.1 Receiver ODT Configuration for MSIO and MSIOD Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7.2 Receiver ODT Configuration for DDRIO Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.8 Driver Impedance Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.8.1 Driver Impedance Configuration for MSIO/MSIODs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.8.2 Driver Impedance Configuration for DDRIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.9 I/O Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.10 Internal Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.11 Low-Power Signature Mode and Activity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.11.1 Signature Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.11.2 Activity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.12 3.3 V Input Tolerance in 2.5 V MSIOD/DDRIO Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.13 5 V Input Tolerance and Output Driving Compatibility (only MSIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.13.1 5 V Input Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.13.2 5 V Output Driving Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.14 I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals . . . . . . . . . . . . . . . . . . . 107
Bounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
DDI
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6.14.1 DDRIOs with MDDR/FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.14.2 DDRIOs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.14.3 MSIOs/MSIODs with MSS or HPMS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.14.4 MSIOs/MSIODs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.15 JTAG I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.16 Dedicated I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.16.1 Device Reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.16.2 Crystal Oscillator I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.16.3 SerDes I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.1 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.2 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 v
Figures
Figure 1 SmartFusion2/IGLOO2 Fabric Architecture for M2S050/M2GL050 . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2 Functional Block Diagram of Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3 Functional Block Diagram of MSIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4 Logic Cluster Top-Level Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 Interface Cluster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6 Fabric Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7 M2S050/M2GL050 and M2S060/M2GL060 Fabric Logical Coordinates . . . . . . . . . . . . . . . . . . . . 10
Figure 8 M2S025/M2GL025 Fabric Logical Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9 M2S010/M2GL010 Fabric Logical Coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10 Simplified Functional Block Diagram for LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11 Data Path for Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12 Data Path for Two-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 Read Operation Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 RADDR Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 Write Operation Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16 Asynchronous Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17 Block Select Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 18 Ports of the LSRAM Configured as Dual-Port SRAM - DPSRAM Macro in Libero SoC . . . . . . . . 30
Figure 19 Ports of the LSRAM Configured as Two-Port SRAM - TPSRAM Macro in Libero SoC . . . . . . . . . 31
Figure 20 RAM1Kx18 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21 CoreAHBLSRAM IP in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22 CoreAPBLSRAM IP in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 23 Two-Port SRAM With W36 and R18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 24 Simplified Functional Block Diagram of µSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25 Timing Waveforms for Synchronous-Asynchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26 Timing Waveforms for Synchronous-Synchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 27 Timing Waveforms for Synchronous Latched Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 28 Timing Waveforms for Read Operations with Asynchronous Inputs Without Pipeline Registers . 48
Figure 29 Timing Waveforms for Read Operations with Asynchronous Inputs with Pipeline Registers . . . . . 48
Figure 30 Timing Waveforms for Read Operations with Asynchronous Inputs with Latched Outputs . . . . . . 49
Figure 31 Timing Waveforms for the Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 32 Timing Waveforms for Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 33 Timing Waveforms for Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 34 µSRAM IP Macro in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 35 RAM64x18 Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 36 Functional Block Diagram of the Math Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 37 Functional Block Diagram of the Math Block in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 38 Functional Block Diagram of the Math Block in DOTP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 39 Math Block Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 40 Non-Pipelined 35 x 35 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 41 Pipeline 35 x 35 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 42 9-Bit Complex Multiplication Using DOTP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 43 Rounding Using C-Input and CARRYIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 44 Rounding and Trimming of the Final Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 45 Rounding and Trimming of the Final Sum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 46 I/O Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 47 IOA Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 48 DDR Support in Low Power Flash Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 49 A Sample Switching Output Buffer Showing Parasitic Inductance . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 50 Basic Block Diagram of Quiet I/O Surrounded by SSO Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 51 Programmable Slew-Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 52 Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 53 Programmable Weak Pull-Up and Pull-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 54 Programmable Schmitt Trigger Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 vi
Figure 55 Programmable Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 56 Bus Keeper Configuration in I/O Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 57 Receiver ODT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 58 Output Drive Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 59 Driver Impedance Configurations for MSIO/MSIODs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 60 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 61 5 V-Input Tolerance Solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 62 5 V Input Tolerance Solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 63 5 V Input Tolerance Solution 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 64 Chip Level Resets From Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 vii
Tables
Table 1 Fabric Resources for SmartFusion2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2 Fabric Resources for IGLOO2 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3 Fabric Array Coordinate Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4 SmartFusion2 and IGLOO2 LSRAM (18Kb Blocks) Resource Table . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5 Port List for LSRAM Macro (RAM1KX18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6 Depth/Width Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7 Read/Write Operation Selection
Table 8 Address Bus Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9 Data Input Buses Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10 Data Output Buses Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11 Port Select Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12 Data Width Configurations for LSRAM in Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 13 Data Width Configurations for LSRAM in Two-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14 Read Operation Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 15 Write Operation Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16 Asynchronous Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17 Block Selection Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18 Collision Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19 Port Description for the DPSRAM Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20 Port Description for the TPSRAM Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21 Port Description for the CoreAPBLSRAM IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22 Port Description for the CoreAHBLSRAM IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 23 Two-Port Configurations Requiring Two LSRAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24 SmartFusion2 and IGLOO2 µSRAM (1Kb Blocks) Resource Table . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 25 Port List for µSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 26 Width/Depth Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 27 Address Bus Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 28 Data Input Buses Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 29 Data Output Buses Used and Unused Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 30 Port Select Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 31 Timing Parameters for Synchronous-Asynchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . 45
Table 32 Timing Parameters for Synchronous-Synchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . 46
Table 33 Timing Parameters for Synchronous Latched Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 34 Timing Parameters of the Asynchronous Read Mode Without Pipeline Registers . . . . . . . . . . . . . 48
Table 35 Timing Parameters of the Asynchronous Read Mode with Pipeline Registers . . . . . . . . . . . . . . . . 48
Table 36 Timing Parameters of the Asynchronous Read Mode with Latched Outputs . . . . . . . . . . . . . . . . . 49
Table 37 Timing Parameters of the Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 38 Timing Parameters of the Asynchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 39 Timing Parameters of the Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 40 Collision Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 41 Port Description for the µSRAM-IP Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 42 SmartFusion2 and IGLOO2 Math Blocks Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 43 Truth Table for Propagating Operand D of the Adder or Accumulator . . . . . . . . . . . . . . . . . . . . . . 59
Table 44 Math Block Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 45 Rounding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 46 MSIO SSO Guidelines for M2S010 - FG484 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 47 MSIOD SSO Guidelines for M2S010 - FG484 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 48 DDRIO SSO Guidelines for M2S010 - FG484 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 49 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S025 - FG484 Device . . . . . . . . . . . . . . . . . . 84
Table 50 MSIO SSO Guidelines for M2S050 - FG896 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 51 MSIOD SSO Guidelines for M2S050 - FG896 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 52 DDRIO SSO Guidelines for M2S050 - FG896 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 53 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S060 - FG676 Device . . . . . . . . . . . . . . . . . . 85
Table 54 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FG676 Device . . . . . . . . . . . . . . . . . . 85
,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 viii
Table 55 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S090 - FCS325 Device . . . . . . . . . . . . . . . . . 86
Table 56 MSIO, MSIOD, and DDRIO SSO Guidelines for M2S150 - FC1152 Device . . . . . . . . . . . . . . . . . 86
Table 57 Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 58 IOA Pair Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 59 Status of the V
Pin Assigned Rule for IOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
REF
Table 60 SmartFusion2 and IGLOO2 I/O Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 61 Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 62 Programmable Weak Pull-up and Pull-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63 I/O Programmable Features and Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 64 ODT Impedance Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 65 ODT Configuration Options for MSIO, MSIOD, and DDRIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 66 DDRIO ODT Configuration- for I/O Connected to Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 67 DDRIO ODT Configuration- for I/O Connected to DDR Controller . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 68 Driver Impedance Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 69 Driver Impedance Configurations for MSIO/MSIODs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 70 Driver Impedance Configurations for DDRIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 71 Driver Impedance Configurations for DDRIOs without DDR Controller . . . . . . . . . . . . . . . . . . . . 102
Table 72 F
Table 73 F
MAX
MAX
, I
, and Max DC Voltage and Current of MSIOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
RMS
, I
, and Max DC Voltage and Current of DDRIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
RMS
Table 74 Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 75 JTAG Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 76 Recommended Tie-Off Values for the TCK and TRST Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 77 Device Reset I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 78 Crystal Oscillator I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 ix
Revision History
1 Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1 Revision 7.0
The following is a summary of the changes in revision 7.0 of this document.
• Updated information about RADDR Synchronizer circuit. For more information see,Figure 14,
page 25 and Operating Modes, page 23.
• Updated Table 64, page 97. For more information see, Receiver ODT Configuration, page 95.
• Updated recommendation for A_BLK[1:0],B_BLK [1:0],and C_BLK signals. For more information
see, A_BLK[1:0], B_BLK [1:0], and C_BLK [1:0], page 42.
• Updated Synchronous Read Mode, page 44. For more information, see Operating Modes, page 44.
1.2 Revision 6.0
The following is a summary of the changes in revision 6.0 of this document.
• Updated SSO Guidelines to Simultaneous Switching Noise. For more information, see Simultaneous
Switching Noise, page 81.
• Added a table to provide the status of the V
information, see Table 59, page 89.
pin when assigned to P-side of the pair. For more
REF
1.3 Revision 5.0
The following is a summary of the changes in revision 5.0 of this document.
• Added 060 device information.
• Updated Figure 2, page 5. For more information, see Fabric Architecture, page 3.
• Updated Logic Element, page 5. For more information, see Fabric Architecture, page 3.
• Added note to Two-Port Mode, page 21. For more information, see LSRAM, page 13.
• Updated A_DOUT[17:0] and B_DOUT[17:0], page 18 with the unconnected information. For more
information, see LSRAM, page 13.
• Updated Table 7, page 16. For more information, see LSRAM, page 13.
• Updated Table 44, page 62. For more information, see Math Blocks, page 56.
• Added Input Reference Voltage, page 88. For more information, see I/Os, page 77.
• Added 3.3 V Input Tolerance in 2.5 V MSIOD/DDRIO Banks, page 104. For more information, see
I/Os, page 77.
• Added Simultaneous Switching Noise, page 81. For more information, see I/Os, page 77.
• Updated table note Table 64, page 97. For more information, see I/Os, page 77.
1.4 Revision 4.0
The following is a summary of the changes in revision 4.0 of this document.
• Updated Supported I/O Standards, page 87. For more information, see I/Os, page 77.
• Updated I/O Programmable Features, page 90 with ODT, Driver impedance, and other features. For
more information, see I/Os, page 77.
• Updated Figure 47, page 80 for DDRIO. For more information, see I/Os, page 77.
• Added Internal Clamp Diode, page 102. For more information, see I/Os, page 77.
1.5 Revision 3.0
The following is a summary of the changes in revision 3.0 of this document.
• Merged the SmartFusion2 SoC and IGLOO2 FPGA Fabric user guide.
• Removed all instances of and references to M2GL100 device from Table 1, page 4 and Table 3,
page 12. For more information, see Fabric Architecture, page 3.
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 1
Revision History
• Removed all instances of and references to M2GL100 device from Table 4, page 13 and Table 3,
• Removed all instances of and references to M2GL100 device from Table 24, page 37. For more
• Removed all instances of and references to M2GL100 device from Table 42, page 56. For more
• Updated Table 18, page 29. For more information, see LSRAM, page 13.
• Updated Micro SRAM (µSRAM), page 37.
• Updated Math Blocks, page 56.
• Updated Introduction, page 77 and Functional Description, page 77. For more information, see I/Os,
• Updated Figure 46, page 78. For more information, see I/Os, page 77.
• Updated Table 57, page 87 and Table 60, page 91. For more information, see I/Os, page 77.
• Updated Programmable Slew-Rate Control, page 91 and Table 63, page 94. For more information,
• Updated Receiver ODT Configuration, page 95. For more information, see I/Os, page 77.
• Updated 5 V Input Tolerance and Output Driving Compatibility (only MSIO), page 105. For more
• Updated I/O Banks, page 81. For more information, see I/Os, page 77.
• Updated the Receive Buffer, page 79 for DDR support in low power devices. For more information,
• Added the Sub-LVDS, page 90. For more information, see I/Os, page 77.
• Added Solution 3, page 106 for 5 V input tolerance section. For more information, see I/Os, page 77.
page 12. For more information, see LSRAM, page 13.
information, see Micro SRAM (µSRAM), page 37.
information, see Math Blocks, page 56.
page 77.
see I/Os, page 77.
information, see I/Os, page 77.
see I/Os, page 77.
1.6 Revision 2.0
The following is a summary of the changes in revision 2.0 of this document.
• Updated Introduction, page 3, Architecture Overview, page 5, and Table 3, page 12. For more
information, see Fabric Architecture, page 3.
• Updated Figure 36, page 57 and Coding Style Examples, page 72. For more information, see Math
Blocks, page 56.
• Updated Introduction, page 77, I/O Banks, page 81, Low-Power Signature Mode and Activity Mode,
page 103, Table 60, page 91, and Table 75, page 108. For more information, see I/Os, page 77.
1.7 Revision 1.0
The following is a summary of the changes in revision 1.0 of this document.
• Updated Figure 46, page 78, Figure 51, page 91, Figure 52, page 92. For more information, see
I/Os, page 77.
• Updated B-LVDS/M-LVDS, page 90. For more information, see I/Os, page 77.
• Updated 5 V Input Tolerance and Output Driving Compatibility (only MSIO), page 105. For more
information, see I/Os, page 77.
• Updated SerDes I/O Pins, page 111. For more information, see I/Os, page 77.
1.8 Revision 0.0
Revision 0.0 was the first publication of this document.
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 2
Fabric Architecture
2 Fabric Architecture
2.1 Introduction
SmartFusion®2 SoC FPGA and IGLOO2 FPGA fabric comprises an array of logic blocks and embedded
hard blocks such as large static random access memory (LSRAM), micro SRAM (µSRAM), and math
blocks for digital signal processing (DSP) capability. These elements are arranged as several rows inside
the fabric, interconnected by the clustered routing architecture of the SmartFusion2 and IGLOO2 device.
Each element in the fabric has a distinct logical coordinate value assigned to it. Figure 1, page 4 shows
the simple layout of the SmartFusion2 and IGLOO2 fabric architecture.
Three types of resources constitute the major part of the fabric logic blocks:
• Logic elements
• Interface logic elements
• I/O modules
The logic element is the basic element used for implementing the combinatorial circuits, arithmetic
functions, and sequential circuits inside the fabric. Each logic module consists of a 4-input LUT, a D-flipflop, and a dedicated carry chain.
The interface logic is the logic element that interfaces the embedded hard blocks to the fabric routing.
The interface logic enables the accessibility of the embedded hard block through the fabric routing. The
interface logic is structurally similar to the logic element except that it does not contain the dedicated
carry chain. The interface logic can also be used to implement the combinatorial and sequential circuits,
if the associated embedded hard block is not being used by the design.
The I/O module forms the digital part of the fabric user I/Os, also called as multi-standard inputs/outputs
(MSIOs). The I/O module enables the user I/Os to be connected to the fabric routing.
The SmartFusion2 and IGLOO2 fabric use a clustered routing architecture to interconnect the various
elements of the fabric. In clustered architecture, various logic elements are grouped together to form the
clusters. The SmartFusion2 and IGLOO2 fabric has three types of clusters:
• Logic clusters
• Interface clusters
• I/O clusters
The logic cluster is composed of 12 logic elements; the interface cluster is composed of 12 interface logic
elements. I/O clusters are composed of 3 to 4 I/O modules, which are distributed on four sides of the
device, as shown in the following figurer (north, south, east, and west I/O clusters).
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 3
Fabric Architecture
North I/O Clusters
East I/O Clusters
One Logic Element
Chip
Layout
Fabric Layout
One Logic Cluster
South I/O Clusters
West I/O Clusters
Logic Clusters
Mathblocks
LSRAM
uSRAM
CCC(x2)
Interface Clusters
Logic Element
Logic Cluster
Logic Cluster
Lo
Logic Cluster
Lo
Logic
gic Cluster
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Logic Element
Figure 1 • SmartFusion2/IGLOO2 Fabric Architecture for M2S050/M2GL050
2.2 Fabric Resources
The following tables list the fabric resources available on SmartFusion2 and IGLOO2 devices.
Table 1 • Fabric Resources for SmartFusion2 Devices
Fabric Resource M2S005 M2S010 M2S025 M2S050 M2S060 M2S090 M2S150
Logic elements
6,060 12,084 27,696 56,340 56,520 86,316 146,124
(4-input LUT + Flip-Flop)
LSRAM 18K blocks 10 21 31 69 69 109 236
µSRAM 1K blocks 11 22 34 72 72 112 240
Math blocks 11 22 34 72 72 84 240
PLLs and CCCs 2 2 6 6 6 6 8
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 4
Fabric Architecture
Y
Routing MUXes
LOGIC ELEMENT
LOGIC ELEMENT
S (SUM)
YQ
4-input LUT
with Carry
Chain
ABCD1
D2
EN
CLK
ALDATA
SLDATA
ALDATA
LOGIC ELEMENT
data
C
out
C
in
FF
D
EN
CLK
SLDATA
Q
C
out
C
in
Table 2 • Fabric Resources for IGLOO2 Devices
Fabric Resource M2GL005 M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150
Logic elements
6,060 12,084 27,696 56,340 56,520 86,316 146,124
(4-input LUT + FlipFlop)
LSRAM 18K blocks 10 21 31 69 69 109 236
µSRAM 1K blocks 11 22 34 72 72 112 240
Math blocks 11 22 34 72 72 84 240
PLLs and CCCs 2 2 6 6 6 6 8
2.3 Architecture Overview
The following sections of this chapter describe the SmartFusion2 and IGLOO2 fabric architecture in
detail.
• Logic Element
• Interface Logic Element
• I/O Module
• FPGA Routing Architecture
2.3.1 Logic Element
The logic elements can be used as a combinational logic element (CLE), and/or sequential logic element
(SLE) in the design. Each logic element consists of:
• A 4-input LUT
• A dedicated carry chain based on the carry look-ahead technique
• A separate flip-flop which can be used independently from the LUT
The following illustration shows the functional block diagram of the logic element with carry chain.
Figure 2 • Functional Block Diagram of Logic Element
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 5
Fabric Architecture
The 4-input LUT can be configured to implement any 4-input combinatorial function or to implement an
arithmetic function, where the LUT output is XORed with carry input (Cin) to generate the sum (S) output.
The sum output, S, is typically used as an output for arithmetic functions but can also be used as an
output for logical functions along with the other output, Y, when the LUT is used to implement
combinatorial functions.
Each logic element has a dedicated 3-bit look-ahead carry implementation, which is used to implement a
dedicated carry chain between the logic elements when the LUT is used to implement arithmetic
operations.
The carry chain has hardwired routing nets running between the logic elements, which reduces the carry
propagation delay through the carry chain, thus giving better performance. The logic element also
contains a dedicated flip-flop, which can be used in conjunction with or independently from the LUT. The
flip-flop can be configured as a register or latch. It has asynchronous and synchronous load and clock
enable inputs. Asynchronous load signal (ALDATA) can be used as asynchronous set or reset signal of
each fabric D flip-flops. It sets or resets the register depending on configuration. Synchronous load signal
(SLDATA) can be used as synchronous set or reset signal of each fabric D flip-flop. It sets or resets the
register depending on configuration. The data input of the flip-flop can be fed from the direct input (D1) or
from the outputs of the 4-input LUT inside the logic element.
2.3.2 Interface Logic Element
Embedded hard blocks (LSRAM blocks, µSRAM blocks, and math blocks) contain a dedicated interface
logic. The embedded hard blocks are connected to the fabric routing structure through LUTs and
flip-flops on their inputs and outputs, and these together form the interface logic element.
Each embedded hard block is associated with 36 interface logic elements. This interface logic element is
structurally equivalent to a logic element but does not have a dedicated carry chain. When a given
embedded hard block is used by the target design, the interface logic is used to connect the embedded
hard block’s I/Os to the fabric routing. If an embedded hard block is not used by the design, the interface
logic element is available for use as a normal logic elements for implementing combinatorial and
sequential circuits. These are in addition to the logic elements available in the fabric.
2.3.3 I/O Module
The I/O module includes the I/O digital (IOD) circuitry and the associated routing interface. Each user I/O
pad is connected to its own dedicated I/O module. The I/O module interfaces the user I/Os with the fabric
routing and enables the routing of external signals coming in through the I/Os to reach all the logic
elements. The I/O modules also enable the internal signals to reach the I/Os.
The following illustration shows the functional diagram of the complete MSIO with the IOD and I/O analog
(IOA) sections. The IOD consists of the input registers, output registers, output enable registers, and
routing multiplexers (MUXes). The output register provides the registered version of the output signals to
the I/Os. In the same way, the input registers are used to register the inputs received from the I/Os. The
output enable acts as a control signal for the output, if the I/O is configured as a tristated or bidirectional
I/O. These registers in the I/O modules are similar to the D-flip-flops available in the logic element. The
usage of the output registers in the I/O modules for registering the output signals at I/Os enables better
design performance. Also, in the case of a signal bus, these registers ensure that all the bits of the signal
bus are synchronized to the clock signal when being sent out through the I/Os. At the input side, the input
registers allow capturing the input signals and synchronizing them to the design clock.
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 6
Fabric Architecture
Figure 3 • Functional Block Diagram of MSIO
Output data
OCLK
Output enable
Output data
Output enable
non-registered
input data
registered input data
I/O Module (IOD)
ICLK
outreg
outreg
outreg
outreg
inreg
DO_P
OE_P
DO_N
OE_N
DI_P
RX
RX
Weak pull-up/pull-down
resistor control
Differential
ODT
01
PAD_P
PAD_N
V
REF
IOA
TX
ODT
0
1
0
1
TX
ODT
non-registered
input data
registered input data
DI_N
inreg
2.3.4 FPGA Routing Architecture
The SmartFusion2 and IGLOO2 fabric has a clustered routing architecture. Clustering is a hierarchical
grouping of fabric resources that allows a more area-efficient implementation of designs while
maintaining optimal performance. It also helps in reducing the run-time of the place-and-route software.
The SmartFusion2 and IGLOO2 fabric routing architecture is composed of three types of clusters:
• Logic Cluster
• Interface Cluster
• I/O Cluster
2.3.4.1 Logic Cluster
The logic cluster is a combination of 12 logic elements with a dedicated hardwired carry chain
implemented for all 12 logic elements. The logic clusters contain routing MUXes. Each routed signal is
driven by a unique logic element output or routing MUX. All the logic elements are interconnected with
feedback from outputs to inputs. The intra-routing inside the logic clusters has a very low propagation
delay as compared to the routing outside the logic clusters.
DIFF_IN
DIFF_OUT
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Fabric Architecture
Logic Elements
Cluster Carry IN
Cluster Carry Out
Intra-cluster
Routing
Buffers
Dedicated Carry Chain
Interface Cluster
Routing
Interface Cluster
Embedded Hard Blocks-LSRAMs, µSRAMs, Mathblocks, CCCs
3 Clusters Wide
Interface
Logic
LUT+ FF
Routing
Interface
Logic
LUT+ FF
12 Interface Logic 12 Interface Logic
Each LUT, D-flip-flop, and the carry-circuit in the logic cluster have an individual X-Y logical coordinate
assigned, and this makes them independently addressable. The following illustration shows the top-level
logic cluster layout diagram.
Figure 4 • Logic Cluster Top-Level Layout
2.3.4.2 Interface Cluster
The interface cluster is similar to the logic cluster except that it is a combination of 12 interface logic
elements. These clusters are used to interface the inputs and outputs of the embedded hard blocks
(LSRAM, µSRAM, math blocks, and CCCs) to fabric routing. Each embedded hard block is spanned by 3
interface clusters, as shown in the following figure. The interface logic can be used as a logic elements
(without carry chain) when the associated embedded hard block is not used by the design.
Figure 5 • Interface Cluster
2.3.4.3 I/O Cluster
I/O clusters are combinations of I/O modules and the associated routing interfaces. The north and south
I/O clusters each contain four I/O modules. The east and west I/O clusters, each contain three I/O
modules. Each I/O pad is associated with its own dedicated I/O module.
2.3.4.4 Routing Structure
The routing of any design is completed automatically by the software, thus, the utilization of the routing
resources is completely transparent to the user. The selection among various routing resources by the
placement-and-routing software is impacted by the design constraints provided. See SmartFusion2 and
IGLOO2 SmartTime, I/O Editor and ChipPlanner User Guide for more details on how to use the
constraints using Libero SoC software.
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 8
Fabric Architecture
Knowledge of the routing architecture and functional modules can be useful in providing effective design
constraints to the software, so that it can be guided to do an optimal design implementation on the
SmartFusion2 and IGLOO2 fabric.
In the SmartFusion2 and IGLOO2 device, the fabric routing is segregated into two parts:
• Inter-cluster routing
• Intra-cluster routing
The following illustration shows the fabric routing structure for the SmartFusion2 and IGLOO2 device.
Figure 6 • Fabric Routing Structure
From Other
Clusters
Inter-Cluster Routing
To Other
Clusters
Cluster
From Adjacent
To Adjacent
To Other
Clusters
Clusters
Clusters
From Other
Clusters
Intra-Cluster Routing (3 Levels of Routing Muxes)
Logic Elements
Output MUXes
Inter-Cluster Routing
Inter-cluster routing spans the clusters and connects them together. The inter-cluster routing resource is
common to all the clusters inside the fabric and is universal across the clusters.
Intra-cluster routing spans the modules that constitute a cluster. Intra-cluster routing is not unique and
varies from cluster to cluster, depending upon the functionality of the cluster. For example, the intracluster routing for an interface cluster is different from that of a logic cluster. There are differences in the
routing of the various interface clusters, depending upon the embedded hard block to which they
interface.
Inter-cluster routing and intra-cluster routing are completely separate. Inter-cluster routing never drives
the inputs of the functional modules (logic elements, interface logic elements, or I/O modules) directly
and the outputs of the functional modules do not drive the inter-cluster routing directly. Inter-cluster
routing has to pass through the intra-cluster routing to reach the functional modules. That makes
SmartFusion2 and IGLOO2 routing a fully clustered routing architecture.
The global network can also drive intra-cluster routing through special routing MUXes. These global
routing MUXes bring in flip-flop control signals such as clock, enable, and sets/resets.
There are a few short routing lines between the adjacent clusters and between the inter-cluster and intracluster routing MUXes. These short paths are provided to provide better performance to the signals
routed through these lines.
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 9
Fabric Architecture
2.4 Fabric Array Coordinate System
Every element in the SmartFusion2 and IGLOO2 fabric has individual logical X-Y coordinates associated
with the fabric array coordinate system. These logical coordinates are used by the place-and-route
software while implementing the design using the fabric elements. The place-and-route software can be
constrained to occupy the design components in specific locations inside the fabric using this coordinate
system. Regions can be created inside the fabric and a particular part of the design can be assigned to
that region using the Libero SoC floor-planner software.
The boundaries of these regions can be specified using the array coordinates. Similarly, the embedded
hard block is also addressable through the fabric coordinate system.
The array coordinates are measured from the bottom-left corner to the top-right corner of the FPGA
fabric. Table 3, page 12 provides the array coordinates of logical modules and embedded hard blocks of
SmartFusion2 and IGLOO2 devices. Figure 7, page 10, Figure 8, page 11, and Figure 9, page 11 show
the array coordinates of an M2S050/M2GL050, M2S060/M2GL060, M2S025/M2GL025, and
M2S010/M2GL010 devices. For more information on how to use array coordinates for region/placement
constraints, see Libero SoC User Guide or online help (available in the software) for SmartFusion2 and
IGLOO2 Libero SoC tools.
Figure 7 • M2S050/M2GL050 and M2S060/M2GL060 Fabric Logical Coordinates
(0,206)
LSRAM (36,194)
(887,206)
(851,194)
Mathblocks (0,158)
uSRAM (0,146)
LSRAM (0,134)
Mathblocks (0,95)
uSRAM (0,83)
Mathblocks (0,59)
uSRAM (0,47)
LSRAM (36,11)
(0,0)
(887,158)
(887,146)
(887,134)
(887,95)
(887,83)
(887,59)
(887,47)
(887,11)
(887,0)
Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0 10
Fabric Architecture
(0,146)
Mathblocks (0,110)
uSRAM (0,98)
LSRAM (36,11)
Mathblocks (0,35)
uSRAM (0,23)
LSRAM (36,194)
(635,146)
(635,110)
(635,98)
(635,11)
(635,0)
(635,35)
(635,23)
(599,194)
(0,0)
Figure 8 • M2S025/M2GL025 Fabric Logical Coordinates
Figure 9 • M2S010/M2GL010 Fabric Logical Coordinates
(0,104)
LSRAM (0,92)
Mathblocks (0,80)
uSRAM (0,68)
LSRAM (0,47)
Mathblocks (0,23)
uSRAM (0,11)
(0,0)
(407,104)
(371,92)
(407,80)
(407,68)
(407,47)
(407,23)
(407,11)
(407,0)
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Fabric Architecture
Table 3 • Fabric Array Coordinate Systems
Logic Elements µSRAM LSRAM Math Blocks
Min Max Bottom Middle Top Bottom Middle Top Bottom Middle Top
Device
M2S005
M2GL005
M2S010
M2GL010
M2S025
M2GL025
M2S050
M2GL050
M2S060
M2GL060
M2S090
M2GL090
M2S150
M2GL150
X Y X Y (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y)
0 0 407 56 NA NA (0,11) NA NA (0,44) NA NA (0,23)
0 0 407 104 (0,11) NA (0,68) (0,47) NA (0,92) (0,23) NA (0,80)
0 0 635 146 (0,23) NA (0,98) (36,11) NA (36,134)(0,35) NA (0,110)
0 0 887 206 (0,47) (0,83) (0,146) (36,11) (0,134) (36,194)(0,59) (0,95) (0,158)
0 0 887 206 (0,47) (0,83) (0,146) (36,11) (0,134) (36,194)(0,59) (0,95) (0,158)
0 0 1031 266 (0, 23) (0, 59)
(0, 194)
0 0 1463 314 (0, 35)
(0, 59)
(0, 107)
(0, 182)
(0, 242) (36, 11) (0, 119)
(0, 170)
(0, 230)
(0, 278)
(36, 11)
(0, 95)
(0, 143)
(0, 218)
(36,
254)
(0, 266)
(36,
302)
(0, 35) (0, 71) (0, 206)
(0, 47)
(0, 71)
(0, 119)
(0, 194)
(0, 242)
(0, 290)
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LSRAM
3 LSRAM
3.1 Introduction
The SmartFusion2 and IGLOO2 fabric has embedded 18 Kbit SRAM blocks used for storing data. These
large SRAM blocks (LSRAMs) are arranged in multiple rows within the FPGA fabric and can be
accessed through the fabric routing architecture. The number of LSRAM blocks available depends upon
the specific SmartFusion2 and IGLOO2 device, as shown in the following table. For example, in the
M2S050 or M2GL050 device, there are 69 LSRAM blocks available, which are spread across three rows
inside the fabric.
3.1.1 Features
The SmartFusion2 and IGLOO2 LSRAM blocks have the following features:
• Each LSRAM block can store up to 18,432 bits of data and can be configured in any of the following
depth x width combinations: 512 x 36, 512 x 32, 1k x 18, 1k x 16, 2k x 9, 2k x 8, 4k x 4, 8k x 2, or
16k x 1.
• Each LSRAM block contains two independent data ports—Port A and Port B.
• The LSRAM is synchronous for both read and write operations. These operations are triggered on
the rising edge of the clock.
• Supports maximum frequency up to 400 MHz.
• An optional pipeline register is available at the read data port to improve the clock-to-out delay.
• LSRAM supports two types of read operations:
• Flow-through read (or non-pipelined)
• Pipelined read
• LSRAM supports two types of write operations:
• Simple write
• Feed-through write (write-bypass write)
• LSRAM can be operated in two memory modes:
• Dual-port mode
• Two-port mode
• A write operation requires one clock cycle.
• A read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data
appears in the next cycle.
• Read from both ports at the same location is allowed.
• Read and write on the same location at the same time is not allowed. There is no built in collision
prevention or detection circuit in LSRAM.
3.2 LSRAM Resources
The following table lists LSRAM rows and 18K blocks available in SmartFusion2 and IGLOO2 devices.
Table 4 • SmartFusion2 and IGLOO2 LSRAM (18Kb Blocks) Resource Table
M2S005/
Device
Rows 1 2 2 3 3 4 6
LSRAM 18 K Blocks 10 21 31 69 69 109 236
Note: All numbers given above are per device.
M2GL005
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M2S010/
M2GL010
M2S025/
M2GL025
M2S050/
M2GL050
M2S060/
M2GL060
M2S090/
M2GL090
M2S150/
M2GL150
LSRAM
3.3 Functional Description
This section provides the detailed description of the following:
• Architecture Overview
• Port List
• Port Descriptions
Architecture Overview
SmartFusion2 and IGLOO2 LSRAM embedded memory includes the RAM1Kx18 macro. The following
illustration shows a simplified block diagram of the LSRAM memory block and Table 5, page 15 provides
the port descriptions. The following illustration shows two independent data ports, the pipeline registers
for read data delay, and the feed-through multiplexers to enable immediate access to the write data.
Figure 10 • Simplified Functional Block Diagram for LSRAM
A_ DIN[17 : 0 ]
A_ADDR[13:0 ]
A_WEN[1:0]
A_BLK[2 :0]
A_CLK
B_A DDR[ 13 : 0 ]
B_WEN[ 1: 0]
`
B_BLK[ 2:0 ]
B_C LK
B_ DIN[ 17:0 ]
Port A Row Decode
Write Control
Memory
Array
1K x 18
Port B Row Decode
Write Control
A_ARST_N
Column
Decode
Column
Dec ode
B_A RST_N
A_WMODE
Feed-through MUX
A
_DOUT_CLK
B_WMODE
B_ DOUT_CLK
A_DOUT[17 :0 ]
A_DOUT_LAT
B_DOUT[ 17 : 0]
B_DOUT_LAT
Pipeline Register
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LSRAM
3.3.1 Port List
Table 5 • Port List for LSRAM Macro (RAM1KX18)
Port Name Direction Type
PORT A
A_WIDTH[2:0] Input Static Port A Width/depth mode select
A_WEN[1:0]2 Input Dynamic High Port A Write enable
A_ADDR[13:0] Input Dynamic Port A Address input
A_DIN[17:0] Input Dynamic Port A Data input
A_DOUT[17:0] Output Dynamic Port A Data output
A_BLK[2:0] Input Dynamic High Port A Block select
A_WMODE Input Static High Port A Feed-through write select
A_CLK Input Dynamic Rising Port A Clock
A_ARST_N Input Dynamic Low Port A Asynchronous reset
A_DOUT_CLK Input Dynamic Rising Port A Pipeline register clock
A_DOUT_LAT Input Static Low Port A Pipeline register Select
A_DOUT_ARST_N Input Dynamic Low Port A Pipeline register asynchronous reset
A_DOUT_EN Input Dynamic High Port A Pipeline register enable
A_DOUT_SRST_N Input Dynamic Low Port A Pipeline register synchronous reset
PORT B
B_WIDTH[2:0] Input Static Port B Width/depth mode select
B_WEN[1:0]
B_ADDR[13:0] Input Dynamic Port B Address input
B_DIN[17:0] Input Dynamic Port B Data input
B_DOUT[17:0] Output Dynamic Port B Data output
B_BLK[2:0] Input Dynamic High Port B Block select
B_WMODE Input Static High Port B Feed-through write select
B_CLK Input Dynamic Rising Port B Clock
B_ARST_N Input Dynamic Low Port B Asynchronous reset
B_DOUT_CLK Input Dynamic Rising Port B Pipeline register clock
B_DOUT_LAT Input Static Low Port B Pipeline register select
B_DOUT_ARST_N Input Dynamic Low Port B Pipeline register asynchronous reset
B_DOUT_EN Input Dynamic High Port B Pipeline register enable
B_DOUT_SRST_N Input Dynamic Low Port B Pipeline register synchronous reset
Common Signals
A_EN Input Static Low Port A power-down
B_EN Input Static Low Port B power-down
SII_LOCK Input Static High Lock access to SII
BUSY Output Dynamic High Busy signal from SII
2
Input Dynamic High Port B Write enable
1
Polarity Description
1. Static inputs are defined at design time and can be or are controlled by flash configuration bits.
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LSRAM
2. If LSRAM is configured in two-port mode with a write data width of x36/x32 and read data width of x36/x32, both the
bits of A_WEN and B_WEN must be tied to logic 1 and should not be dynamically changed.
3.3.2 Port Descriptions
3.3.2.1 A_WIDTH[2:0] and B_WIDTH[2:0]
These signals represent the depth x width mode selections for each port. The following table shows the
depth x width based on ports width selection.
Table 6 • Depth/Width Mode Selection
A_WIDTH/B_WIDTH Depth/Width
000 16K x 1
001 8K x 2
010 4k x 4
011 2K x 9
2K x 8
100 1K x 18
1K x 16
101
110
111
(Two-port)
512 x 36
512 x 32
3.3.2.2 A_WEN[1:0] and B_WEN[1:0]
These signals represent the write enables for each port to select read/write operations. The following
table shows the depth x width operations based on port write enable selection.
Table 7 • Read/Write Operation Selection
Depth x Width A_WEN/B_WEN Operation
16K x 1
8K x 2
4K x 4
2K x 8
2K x 9
1K x 16
1K x 18
16K x 1
8K x 2
4K x 4
2K x 8
2K x 9
1K x 16
1K x 18
512 x 32
(Two-port write-Port B)
512 x 36
(Two-port write-Port B)
1, 2
00 Read
operation
1 Write
operation
A_WEN[1:0] = “11”
B_WEN[1:0] = “11”
B_WEN[1:0] = “11”
A_WEN[1:0] = “11”
Write [31:0]
Write [35:0]
1. In dual-port mode, every port reads when the corresponding write
enable (A_WEN/B_WEN) is "00" and corresponding port select
(A_BLK/B_BLK) is active.
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LSRAM
2. In two-port mode, the read port (Port A) reads in every clock cycle if
A_BLK is active.
3.3.2.3 A_ADDR[13:0] and B_ADDR[13:0]
These signals represent the address buses for the two ports. In x1 mode 14 bits are used to address the
16,384 independent locations. In wider modes (x2, x4, etc.) fewer address bits are used. The used
address bits are the most significant bits (MSB). The unused bits are the least significant bits (LSBs) and
they must be grounded. The following table shows the address bus used and unused bits for depth x
width selections.
Table 8 • Address Bus Used and Unused Bits
A_ADDR/B_ADDR
Depth x Width
16K x 1 [13:0] None
8K x 2 [13:1] [0]
4K x 4 [13:2] [1:0]
2K x 9
2K x 8
1K x 18
1K x 16
512 x 36 [13:5] [4:0]
Used Bits Unused bits (to be grounded)
[13:3] [2:0]
[13:4] [3:0]
3.3.2.4 A_DIN[17:0] and B_DIN[17:0]
These signals represent the data input buses for the two ports. In dual-port mode, the data width can
range from 1 bit to 18 bits. In two-port mode, Port B becomes the write-only port. Giving a write data
width of 36 bits, A_DIN[17:0] becomes write data[35:18] and B_DIN[17:0] becomes write data[17:0]. The
used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded. The
following table shows the data input buses used and unused bits for depth x width selections.
Table 9 • Data Input Buses Used and Unused Bits
Depth x Width A_DIN/B_DIN
Used Bits Unused bits (to be grounded)
16K x 1 [0] [17:1]
8K x 2 [1:0] [17:2]
4K x 4 [3:0] [17:4]
2K x 8 [7:0] [17:8]
2K x 9 [8:0] [17:9]
1K x 16 [16:9] is [15:8]
[7:0] is [7:0]
1K x 18 [17:0] None
512 x 32 A_DIN[16:9] is [31:24]
A_DIN[7:0] is [23:16]
B_DIN[16:9] is [15:8]
B_DIN[7:0] is [7:0]
[17]
[8]
A_DIN[17]
A_DIN[8]
B_DIN[17]
B_DIN[8]
512 x 36 A_DIN[17:0] is [35:18]
B_DIN[17:0] is [17:0]
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None
LSRAM
3.3.2.5 A_DOUT[17:0] and B_DOUT[17:0]
These signals represent the data output buses for the two ports. In dual-port mode, the data width can
range from 1 bit to 18 bits. In two-port mode, Port A becomes the read-only port. Giving a read data width
of 36 bits, A_DOUT[17:0] becomes read data[35:18] and B_DOUT[17:0] becomes read data[17:0]. The
used bits for any mode are LSB justified in the data bus and the unused MSB bits must be unconnected.
The following table shows the data output buses used and unused bits for depth x width selections.
Table 10 • Data Output Buses Used and Unused Bits
A_DOUT/B_DOUT
Depth x Width
16K x 1 [0] [17:1]
8K x 2 [1:0] [17:2]
4K x 4 [3:0] [17:4]
2K x 8 [7:0] [17:8]
2K x 9 [8:0] [17:9]
1K x 16 [16:9] is [15:8]
1K x 18 [17:0] None
512 x 32 A_DOUT[16:9] is [31:24]
512 x 36 A_DOUT[17:0] is [35:18]
Used Bits Unused bits (unconnected)
[7:0] is [7:0]
A_DOUT[7:0] is [23:16]
B_DOUT[16:9] is [15:8]
B_DOUT[7:0] is [7:0]
B_DOUT[17:0] is [17:0]
[17]
[8]
A_DOUT[17]
A_DOUT[8]
B_DOUT[17]
B_DOUT[8]
None
3.3.2.6 A_BLK[2:0] and B_BLK[2:0]
These signals represent the port select control signals for each port. The following table shows
operations (Read, Write, and No operation) based on selection of port select control signals.
Table 11 • Port Select Control Signals
Port Select Signal Value Result
A_BLK[2:0] 111 Perform read or write operation on Port A.
A_BLK[2:0] 000
001
010
011
100
101
110
B_BLK[2:0] 111 Perform read or write operation on Port B.
B_BLK[2:0] 000
001
010
011
100
101
110
No operation in memory from Port A. Port A output is forced to logic 0.
No operation in memory from Port B. Port B output is forced to logic 0.
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LSRAM
3.3.2.7 A_WMODE and B_WMODE
These signals represent the Write mode control signals for Port A and Port B.
• Logic 0: Output data port holds the previous value.
• Logic 1: Feed-through; write data appears on the corresponding output data port. In two-port mode,
feed-through write is not supported.
3.3.2.8 A_CLK and B_CLK
These signals represent the clock inputs for Port A and Port B. All inputs must be set up before the rising
edge of the clock. The read or write operation begins with the rising edge.
3.3.2.9 A_ARST_N and B_ARST_N
These signals represent Active Low, asynchronous reset inputs for Port A and Port B. Assertion of these
resets during read operation forces the data output lines to logic 0. Assertion of these resets during write
operation results in garbage values written into the memory.
3.3.2.10 A_DOUT_ARST_N and B_DOUT_ARST_N
These signals represent Active Low, asynchronous reset inputs for the output pipeline registers for Port A
and Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode,
these inputs should be tied to logic 1.
3.3.2.11 A_DOUT_LAT and B_DOUT_LAT
These signals represent Latch mode inputs for the output pipeline registers for Port A and Port B.
• Logic 0: Register operation
• Logic 1: Latch operation
3.3.2.12 A_DOUT_EN and B_DOUT_EN
These signals represent Active High; enable inputs for the output pipeline registers for Port A and Port B.
• Logic 1: Normal register operation
• Logic 0: Register holds previous data
3.3.2.13 A_DOUT_SRST_N and B_DOUT_SRST_N
These signals represent Active Low, synchronous reset inputs for the output pipeline registers for Port A
and Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode,
these inputs should be tied to logic 1.
3.3.2.14 A_EN and B_EN
These are Active Low, power-down configuration bits for each port.
3.3.2.15 SII_LOCK
This control signal, when asserted to logic 1, locks the entire LSRAM memory for being accessed by the
system controller interface bus (SII). The system controller can access the LSRAM for the following
purposes:
• Testing the memory
• Moving data between LSRAM and embedded nonvolatile memory (eNVM) or external memories
• Moving data between various LSRAMs or between µSRAMs and LSRAMs
• LSRAMs cannot be accessed when the system controller is accessing them
3.3.2.16 BUSY
This signal acts as a Status signal when the system controller is accessing the particular LSRAM. Logic
1 on this signal indicates system controller access. This signal can be used to monitor the completion of
LSRAM access.
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LSRAM
3.4 Memory Modes
LSRAM can be configured as a dual-port SRAM or two-port SRAM.
3.4.1 Dual-Port Mode
LSRAM configured as dual-port SRAM provides a data storage capability of 18 Kbits with two
independent access ports: Port A and Port B, as shown in the following illustration. Read and write
operations can be done from both the ports independently at any location as long as there is no collision.
In dual-port mode, the maximum data width can be x18 for either port. In dual-port mode, each port of the
LSRAM can be configured in the following depth x width configurations:
• 1k x 18, 1k x 16
• 2k x 9, 2k x 8
• 4k x 4
• 8k x 2
• 16k x 1
The following illustration shows the data path for the dual-port SRAM (DPSRAM).
Figure 11 • Data Path for Dual-Port Mode
PORT A
A_DIN B_DIN
18
18
PORT B
DATA In A DATA In B
Port A
Signals
DATA Out A DATA Out B
Pipeline
Register A
18 18
Data can be written to either or both ports and also can be read from either or both ports. Each port has
its own address, data in, data out, clock, block select, and write enable. The read and write operations
are synchronous and require a clock edge.
There is no collision detection or prevention circuit built into LSRAM. Simultaneous write operations from
both the ports to the same address location result in data uncertainty. Simultaneous read and write
operations from both the ports to the same address location results in correct data written into the
memory but garbage values being read out.
Pipeline
Register B
B_DOUTA_DOUT
Port B
Signals
The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data
appears in the next cycle. The write operation requires one clock cycle.
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LSRAM
When the read operation is configured with output pipeline registers, the input clock sourcing the pipeline
registers has to be synchronized to the LSRAM's clock input; that is, A_DOUT_CLK should be
synchronized to A_CLK and B_DOUT_CLK should be synchronized to B_CLK.
The following table describes the data width configurations that are supported by LSRAM configured in
dual-port mode.
Table 12 • Data Width Configurations for LSRAM in Dual-Port Mode
Port A Data Width (represented
as “x number of bits”) Port B Data Width (represented as “x number of bits”)
x1 x1, x2, x4, x8, x16
x2 x1, x2, x4, x8, x16
x4 x1, x2, x4, x8, x16
x8 x1, x2, x4, x8, x16
x16 x1, x2, x4, x8, x16
x9 x9, x18
x18 x9, x18
3.4.2 Two-Port Mode
LSRAM configured as two-port SRAM provides a data storage capability of 18 Kbits, with Port A
dedicated to read operations and Port B dedicated to write operations, as shown in the following figure.
In two-port mode, the maximum data width for the read port (Port A) and the write port (Port B) is x36.
Figure 12 • Data Path for Two-Port Mode
PORT A
Port A
Signals
PORT B
A_DIN B_DIN
18
DATA In A DATA In B
DATA Out A DATA Out B
Pipeline
Register A
18 18
18
Pipeline
Register B
B_DOUTA_DOUT
Port B
Signals
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