Microsemi IGLOO PLUS Starter Kit User Manual
IGLOO PLUS Starter Kit
User’s Guide
IGLOO PLUS Starter Kit User’s Guide
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
IGLOO PLUS Starter Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Board Components and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IGLOO PLUS Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connectors, Jumpers, and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 FPGA Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Key Features of AGLP125-CSG289 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Decaps and Ground Post Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Potentiometer and Voltage-Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4 Operation of Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Flash*Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
.DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
OLED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Low-Cost Programming Stick (LCPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6 IGLOO PLUS Board Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Demos Included in the Starter Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Powering Up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Getting Started with the IGLOO PLUS Starter Kit Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
B List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Revision 1 3
Table of Contents
C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4 Revision 1
Introduction
IGLOO PLUS Starter Kit Contents
The RoHS-compliant, environmentally friendly IGLOO® PLUS Starter Kit is packaged in a recyclable
cardboard box made from recycled materials. This development kit includes an on-board programmer
and demonstrates the ultra-low power of Microsemi® IGLOO PLUS devices. Ta bl e 1 lists the contents of
the box.
Table 1 • IGLOO PLUS Starter Kit Contents
Quantity Contents
1 IGLOO PLUS board with AGLP125 IGLOO PLUS field programmable gate array (FPGA)
1 Programmer for use with IGLOO PLUS board
1 5 V power supply
2 USB 2.0 high-speed cables
1 Packet of jumpers
®
1 Microsemi Libero
1 Quickstart Guide
System-on-Chip (SoC) software DVD
Figure 1 • IGLOO PLUS Starter Kit Board
Revision 1 5
1 – Board Components and Settings
This chapter describes the components and settings for the IGLOO PLUS Starter Kit Board.
Board Description
The IGLOO PLUS Starter Kit board is intended to provide a low-cost system platform for evaluating
IGLOO PLUS (AGLP) technology, such as low power, I/O state preservation during Flash*Freeze mode,
and Schmitt Triggered I/Os. Other advanced features include the ability to use the FPGA I/Os of the
Expansion Header as hot-swappable and the Schmitt Triggered FPGA inputs for improved noise
immunity.
This evaluation board enables you to measure power consumption (dynamic, static, and Flash*Freeze
modes) with the core operating between 1.2 V and 1.5 V. When using the board in conjunction with the
Microsemi power analysis tools, you will have a clear picture of application power consumption at each
stage in your design. In addition, the Libero SoC tool suite now includes power-driven layout (PDL),
which can reduce the power consumption of designs up to 30 percent.
The evaluation board has a small form factor, measuring 3.7 inches by 4 inches, and supports an
AGLP125 IGLOO PLUS device in the 14 mm × 14 mm CSG289 package. All components used on the
board, such as LEDs, reset (µA range), and oscillator, are low-power components. Also included on the
evaluation board is a USB-to-UART interface to allow HyperTerminal on a PC to communicate with the
IGLOO PLUS device on the board.
The top of the board has a programming stick header which allows the low-cost programming stick
LCPS) to be attached to the board for programming the IGLOO PLUS AGLP125-CSG289 device
(Figure 1-1). FPGA I/Os have been wired to test pin pads on the board for debug and expandability.
Figure 1-1 • IGLOO PLUS Starter Kit Board
Note: The clock oscillator for the IGLOO PLUS Starter Kit Board is behind the board.
Revision 1 7
Board Components and Settings
IGLOO PLUS Board Stackup
The IGLOO PLUS board is built on a 10-layer PCB. Figure 1-1 and Figure 1-1 on page 7 show the top
(L1) and bottom (L10) silkscreens. The full PCB design layout is provided on the Microsemi SoC
Products Group website, on the IGLOO PLUS Starter Kit page:
www.microsemi.com/soc/products/hardware/devkits_boards/iglooplus_starter.aspx. To view the PCB
design layout files, you can use the Allegro Free Physical Viewer, which can be downloaded from the
Cadence Allegro Downloads page.
• Top Signal (Figure 1-1 on page 7)
•GND 1
•Signal
•GND 2
•PWR 1
•PWR 2
•GND 3
•Signal
•GND 4
• Bottom Signal (Figure 1-2 on page 9)
8 Revision 1
IGLOO PLUS Starter Kit User’s Guide
Figure 1-2 • IGLOO PLUS Top Silkscreen (L1)
Revision 1 9
Board Components and Settings
Figure 1-3 • IGLOO PLUS Bottom Silkscreen (L10)
10 Revision 1
IGLOO PLUS Starter Kit User’s Guide
Connectors, Jumpers, and Switch Settings
Recommended default jumper settings are defined in Table 1-1. The voltage selection jumpers are
highlighted in grey. Connect jumpers in the default settings described in Ta bl e 1-1 to enable the preprogrammed demo design to function correctly.
Table 1-1 • Jumper and Connector Settings
Jumper Default Setting Comment
J1 Ground post header
J2 Ground post header
J3 LC JTAG header for programmer
J4 JTAG header
J5 USB mini receptacle
J6 Pin 2-3 Remove jumper to disconnect VCCI_0 power
J7 Remove Remove jumper to disconnect external battery source
J8 Pin 2-3 Remove jumper to disconnect VCCI_1 power
J9 Pin 1-4 Select WALL, BAT, VUSB for 5V_SOURCE
Pin 1-4 = VUSB
Pin 2-4 = BAT
Pin 3-4 = WALL
J10 5 V Brick
J11 Pin 1-2 Select VCC or VCC_SWEEP for VCORE
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
J12 Pin 2-3 Current measurement header for VCORE
J13 Pin 2-3 Current measurement header for VCCI_3
J14 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_1
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
J15 Pin 3-2 Select VJTAGENB or 3.3 V
Pin 3-2 = VJTAGENB
Pin 1-2 = 3.3 V
J16 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_1
Pin 2-4 = 3.3 V
Pin 3-4 = 1.5 V or 1.2 V
Pin 1-4 = 2.5 V
J17 Pin 2-3 Current measurement header for VCCI_2
J18 Pin 1-2 Select VCC or VCC_SWEEP for VCCI_0
Pin 1-2 = VCC
Pin 3-2 = VCC_SWEEP
Revision 1 11
Board Components and Settings
Table 1-1 • Jumper and Connector Settings (continued)
Jumper Default Setting Comment
J19 Pin 2-4 Select 3.3 V, 1.5 / 1.2 V, or 2.5 V for VCCI_0
Pin 2-4 = 3.3 V
Pin 3-4 = 1.5 V or 1.2 V
Pin 1-4 = 2.5 V
J20 Pin 2-3 Current measurement header for VJTAG
J21 Pin 1-2 Select 3.3 V or 1.5 / 1.2 V for VJTAG
Pin 1-2 = 3.3 V
Pin 2-3 = 1.5 V or 1.2 V
J22 Pin 2-3 Current measurement header for VPUMP
J23-J24 Pin 1-2 Remove each jumper to disconnect any of the 2 FET Switches[1:2] from
FPGA.
J23 = 3V3_SWITCH1
J24 = 3V3_SWITCH2
J25-J27 Pin 1-2 Remove each jumper to disconnect any of the 3 FET LEDs from FPGA.
J25 = FET_P1
J26 = FET_N
J27 = FET_P2
J28-J35 Pin 1-2 Remove each jumper to disconnect any of the 8 user DIP switches[1:8] from
FPGA.
J28 = D_SWITCH1
J29 = D_SWITCH2
J30 = D_SWITCH3
J31 = D_SWITCH4
J32 = D_SWITCH5
J33 = D_SWITCH6
J34 = D_SWITCH7
J35 = D_SWITCH8
J36-J39 Pin 1-2 Remove each jumper to disconnect any of the 4 push-button switches[1:4] from
FPGA.
J36 = SWITCH1
J37 = SWITCH2
J38 = SWITCH3
J39 = SWITCH4
J40-J47 Pin 1-2 Remove each jumper to disconnect any of the 8 user LEDs[1:8] from FPGA.
J42 = LED1
J41 = LED2
J40 = LED3
J47 = LED4
J46 = LED5
J45 = LED6
J44 = LED7
J43 = LED8
12 Revision 1
IGLOO PLUS Starter Kit User’s Guide
Table 1-2 • Switch Settings
Switch Default Setting Comment
SW1–SW4 Push-button switches for SWITCH[1:4]
SW5 CLOSE Contains DIP switches for 3V3_SWITCH[1:2]
DSW5 CLOSE Contains DIP switches for D_SWITCH[1:8]
SW7 Push-button switch for system reset PBRESET_N
SW8 OFF Flash*Freeze: To enable Flash*Freeze mode, SW8 toward ON.
In Flash*Freeze mode, current consumption of FPGA goes below 50 µA.
Revision 1 13
2 – FPGA Description
The IGLOO PLUS board is populated with an IGLOO PLUS AGLP125-CSG289 FPGA.
Key Features of AGLP125-CSG289
• Low power
• 1.2 V to 1.5 V core voltage support for low power
• Supports single-voltage system operation
• 5 µW power consumption in Flash*Freeze mode
• Low-power active FPGA operation
• Flash*Freeze technology enables ultra-low power consumption while maintaining FPGA content
• Configurable hold previous state, tristate, HIGH, or LOW state per I/O in Flash*Freeze mode
• Easy entry to / exit from ultra-low-power Flash*Freeze mode
• Reprogrammable flash technology
• In-system programming (ISP) and security
• High-performance routing hierarchy
• Advanced I/O
• Selectable Schmitt trigger inputs
• Clock conditioning circuit (CCC) and PLL
• Embedded memory
Table 2-1 lists specifications for the AGLP125-CSG289 FPGA.
Table 2-1 • IGLOO PLUS AGLP125-CSG289 FPGA Features
Feature Specification
System Gates 125,000
Typical Equivalent Macrocells 1,024
VersaTiles (D-flip-flops) 3,120
Flash*Freeze Mode (Typical, µW) 16
RAM kbits (1,024 bits) 36
4,608-Bit Blocks 8
FlashROM (bits) 1 K
Secure (AES) ISP Yes
Integrated PLLs in CCCs 1
VersaNet Globals 18
I/O Banks 4
Maximum User I/Os 212
For further information, refer to the IGLOO PLUS datasheet:
www.microsemi.com/soc/documents/IGLOOPLUS_DS.pdf
Revision 1 15
FPGA Description
VCCPLF
VCCIB0_1
B7
VCCIB0_2
B12
VCCIB0_3
C5
VCCIB0_4
E11
VCCIB1_1
E16
VCCIB1_2
H15
VCCIB1_3
L14
VCCIB1_4
M17
VCCIB2_1
N10
VCCIB2_2
P13
VCCIB2_3
R6
VCCIB2_4
T9
VCCIB3_1
E1
VCCIB3_2
F4
VCCIB3_3
J3
VCCIB3_4
M2
VCC1
L9
VCC2
G9
VCC3
J7
VCC4
J11
VCOMPLF
H1
VCCPLF
J1
GND1
A4
GND2
A9
GND3
A14
GND4
B2
GND5
B17
GND6
C10
GND7
C15
GND8
D3
GND9
D8
GND10
D13
GND11
F14
GND12
G2
GND13
G7
GND14
G8
GND15
G10
GND16
G11
GND17
G17
GND18
H7
GND19
H8
GND20
H9
GND21
H10
GND22
H11
GND23
J8
GND24
J9
GND25
J10
GND26
K1
GND27
K7
GND28
K8
GND29
K9
GND30
K10
GND31
K11
GND32
K16
GND33
L4
GND34
L7
GND35
L8
GND36
L10
GND37
L11
GND38
N5
GND39
N15
GND40
P3
GND41
P8
GND42
R1
GND43
R11
GND44
T4
GND45
T14
GND46
U2
GND47
U7
GND48
U12
SEC 5/6
AGLP125 CSG289
POWER
GND
U5E
AGLP125-CSG289
SEC 5/6
POWER
GND
U5E
Power and Ground Pins
Figure 2-1 shows the power and ground pins for AGLP125-CSG289.
Figure 2-1 • Power and Ground Pins for AGLP125-CSG289
16 Revision 1
Bank I/O Signals
Figure 2-2 through Figure 2-5 on page 19 show the schematics for the bank I/O signals.
TP105TPTP105
TP112TPTP112
TP69TPTP69
TP71TPTP71
TP110TPTP110
TP85TPTP85
TP74TPTP74
TP86TPTP86
TP108TPTP108
TP106TPTP106
TP101TPTP101
TP120TPTP120
TP72TPTP72
TP70TPTP70
TP113TPTP113
TP87TPTP87
TP114TPTP114
TP121TPTP121
TP107TPTP107
TP73TPTP73
TP115TPTP115
TP75TPTP75
TP95TPTP95
TP122TPTP122
TP94TPTP94
TP123TPTP123
AGL_B0_PIN_B3
AGL_B0_PIN_D5
AGL_B0_PIN_A3
AGL_B0_PIN_C4
AGL_B0_PIN_D6
AGL_B0_PIN_A2
AGL_B0_PIN_E6
AGL_B0_PIN_B4
AGL_B0_PIN_F7
AGL_B0_PIN_B5
AGL_B0_PIN_E7
AGL_B0_PIN_C6
AGL_B0_PIN_D7
AGL_B0_PIN_A5
AGL_B0_PIN_F8
AGL_B0_PIN_B6
AGL_B0_PIN_E8
AGL_B0_PIN_C7
AGL_B0_PIN_A6
AGL_B0_PIN_F9
AGL_B0_PIN_A7
AGL_B0_PIN_C8
AGL_B0_PIN_B8
AGL_B0_PIN_F10
AGL_B0_PIN_A8
AGL_B0_PIN_B9
AGL_B0_PIN_E9
AGL_B0_PIN_C9
AGL_B0_PIN_D9
AGL_B0_PIN_A10
AGL_B0_PIN_E10
AGL_B0_PIN_B10
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP207TPTP207
TP
TP222TPTP222
TP
TP
TP239TPTP239
TP
TP
TP240TPTP240
TP
TP
TP247TPTP247
TP
TP
TP236TPTP236
TP
AGLP125 CSG289
B3
IO06RSB0
D5
IO07RSB0
A3
IO08RSB0
C4
IO09RSB0
D6
IO10RSB0
A2
IO11RSB0
E6
IO12RSB0
B4
IO13RSB0
F7
IO14RSB0
B5
IO15RSB0
E7
IO16RSB0
C6
IO17RSB0
D7
IO18RSB0
A5
IO19RSB0
F8
IO20RSB0
B6
IO21RSB0
E8
IO22RSB0
C7
IO23RSB0
A6
IO24RSB0
F9
IO25RSB0
A7
IO26RSB0
C8
IO27RSB0
B8
IO28RSB0
F10
IO29RSB0
A8
IO30RSB0
B9
IO31RSB0
E9
IO32RSB0
C9
IO33RSB0
D9
IO34RSB0
A10
IO35RSB0
E10
IO36RSB0
B10
IO37RSB0
U5A
U5A
SEC 1/6
SEC 1/6
BANK0
BANK0
AGLP125-CSG289
IO38RSB0
IO39RSB0
IO40RSB0
IO41RSB0
IO42RSB0
IO43RSB0
IO44RSB0
IO45RSB0
IO46RSB0
IO47RSB0
IO48RSB0
IO49RSB0
IO50RSB0
IO51RSB0
IO52RSB0
IO53RSB0
IO54RSB0
IO55RSB0
IO56RSB0
GAA0/IO00RSB0
GAA1/IO01RSB0
GAB0/IO02RSB0
GAB1/IO03RSB0
GAC0/IO04RSB0
GAC1/IO05RSB0
GBA0/IO61RSB0
GBA1/IO62RSB0
GBB0/IO59RSB0
GBB1/IO60RSB0
GBC0/IO57RSB0
GBC1/IO58RSB0
A11
B11
A12
D10
A13
C11
B13
C12
B14
D11
A15
B15
C13
F11
C14
F12
A16
D12
E12
C2
B1
D4
A1
C3
E5
C16
D15
D14
E13
A17
B16
IGLOO PLUS Starter Kit User’s Guide
GPIOA_1 {3}
GPIOA_3 {3}
GPIOA_5 {3}
GPIOA_7 {3}
GPIOA_9 {3}
GPIOA_13 {3}
GPIOA_15 {3}
GPIOA_17 {3}
GPIOA_19 {3}
GPIOA_21 {3}
GPIOA_23 {3}
GPIOA_25 {3}
GPIOA_27 {3}
GPIOA_29 {3}
GPIOA_31 {3}
GPIOA_33 {3}
GPIOA_35 {3}
AGL_B0_PIN_D12
AGL_B0_PIN_E12
AGL_B0_PIN_C2
AGL_B0_PIN_B1
AGL_B0_PIN_D4
AGL_B0_PIN_A1
AGL_B0_PIN_C3
AGL_B0_PIN_E5
AGL_B0_PIN_C16
AGL_B0_PIN_D15
AGL_B0_PIN_D14
AGL_B0_PIN_E13
AGL_B0_PIN_A17
AGL_B0_PIN_B16
TP96TPTP96
TP116TPTP116
TP79TPTP79
TP124TPTP124
TP117TPTP117
TP77TPTP77
TP97TPTP97
TP89TPTP89
TP80TPTP80
TP78TPTP78
TP118TPTP118
TP98TPTP98
TP111TPTP111
TP76TPTP76
TP109TPTP109
TP103TPTP103
TP81TPTP81
TP93TPTP93
TP92TPTP92
TP102TPTP102
TP22TPTP22
TP90TPTP90
TP68TPTP68
TP83TPTP83
TP91TPTP91
TP82TPTP82
TP84TPTP84
TP88TPTP88
TP100TPTP100
TP99TPTP99
TP119TPTP119
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
Figure 2-2 • Bank 0 I/O Signals for AGLP125-CSG289
Revision 1 17
FPGA Description
{3}
{3}
{3}
{3}
GPIOA_2{3}
GPIOA_4
GPIOA_6{3}
GPIOA_8{3}
GPIOA_10
GPIOA_12{3}
GPIOA_16{3}
GPIOA_18{3}
GPIOA_20{3}
GPIOA_22
GPIOA_24{3}
GPIOA_26{3}
GPIOA_28{3}
GPIOA_30
GPIOA_32{3}
GPIOA_34{3}
GPIOA_36{3}
U5B
U5B
AGLP125 CSG289
SEC 2/6
TP38TPTP38
TP
TP45TPTP45
TP
TP44TPTP44
TP
TP40TPTP40
TP
TP26TPTP26
TP
TP27TPTP27
TP
TP33TPTP33
TP
TP46TPTP46
TP
TP17TPTP17
TP
TP25TPTP25
TP
TP28TPTP28
TP
TP47TPTP47
TP
TP32TPTP32
TP
TP36TPTP36
TP
TP23TPTP23
TP
TP37TPTP37
TP
TP35TPTP35
TP
AGL_B1_PIN_L16
TP49TPTP49
TP
AGL_B1_PIN_K15
TP21TPTP21
TP
AGL_B1_PIN_K13
TP34TPTP34
TP
AGL_B1_PIN_K14
TP16TPTP16
TP
AGL_B1_PIN_M16
TP30TPTP30
TP
AGL_B1_PIN_M15
TP18TPTP18
TP
TP41TPTP41
AGL_B1_PIN_L15
TP
G13
IO64RSB1
D16
IO66RSB1
C17
IO68RSB1
G14
IO69RSB1
D17
IO70RSB1
F16
IO71RSB1
G12
IO72RSB1
E17
IO73RSB1
H13
IO74RSB1
F15
IO75RSB1
G16
IO76RSB1
F17
IO77RSB1
G15
IO78RSB1
K12
IO88RSB1
J15
IO89RSB1
J14
IO90RSB1
L17
IO91RSB1
L16
IO92RSB1
K15
IO93RSB1
K13
IO94RSB1
K14
IO95RSB1
M16
IO96RSB1
M15
IO97RSB1
L15
IO98RSB1
SEC 2/6
BANK1
BANK1
AGLP125-CSG289
GBA2/IO63RSB1
GBB2/IO65RSB1
GBC2/IO67RSB1
GCA0/IO84RSB1
GCA1/IO83RSB1
GCA2/IO85RSB1
GCB0/IO82RSB1
GCB1/IO81RSB1
GCB2/IO86RSB1
GCC0/IO80RSB1
GCC1/IO79RSB1
GCC2/IO87RSB1
GDA0/IO104RSB1
GDA1/IO103RSB1
GDB0/IO102RSB1
GDB1/IO101RSB1
GDC0/IO100RSB1
GDC1/IO99RSB1
E14
E15
F13
H14
J17
H16
J16
J13
J12
H17
H12
K17
M14
M13
N16
L13
N17
L12
AGL_B1_PIN_E14
AGL_B1_PIN_E15
AGL_B1_PIN_F13
AGL_B1_PIN_H14
AGL_B1_PIN_J17
AGL_B1_PIN_H16
AGL_B1_PIN_J16
AGL_B1_PIN_J13
AGL_B1_PIN_J12
AGL_B1_PIN_H17
AGL_B1_PIN_H12
AGL_B1_PIN_K17
AGL_B1_PIN_M14
AGL_B1_PIN_M13
AGL_B1_PIN_N16
AGL_B1_PIN_L13
AGL_B1_PIN_N17
AGL_B1_PIN_L12
TP39TPTP39
TP104TPTP104
TP42TPTP42
TP29TPTP29
TP48TPTP48
TP43TPTP43
TP20TPTP20
TP50TPTP50
TP24TPTP24
TP31TPTP31
TP19TPTP19
TP
TP
TP
TP226TPTP226
TP
TP210TPTP210
TP
TP223TPTP223
TP
TP208TPTP208
TP142TPTP142
TP162TPTP162
TP
TP183TPTP183
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
Figure 2-3 • Bank 1 I/O Signals for AGLP125-CSG289
AGLP125 CSG289
P14
N14
R15
N12
P12
M12
R14
T15
R13
U15
R12
N11
U14
M11
T13
U13
T12
P10
P11
T11
M10
U11
R10
T10
U10
P9
R9
M9
U9
N9
U8
IO108RSB2
IO109RSB2
IO110RSB2
IO111RSB2
IO112RSB2
IO113RSB2
IO114RSB2
IO115RSB2
IO116RSB2
IO117RSB2
IO118RSB2
IO119RSB2
IO120RSB2
IO121RSB2
IO122RSB2
IO123RSB2
IO124RSB2
IO125RSB2
IO126RSB2
IO127RSB2
IO128RSB2
IO129RSB2
IO130RSB2
IO131RSB2
IO132RSB2
IO133RSB2
IO134RSB2
IO135RSB2
IO136RSB2
IO137RSB2
IO138RSB2
[6]
PACER_RES#
[6]
PACER_D2[6]
PACER_D0
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP130TPTP130
TP163TPTP163
TP170TPTP170
TP161TPTP161
TP180TPTP180
TP141TPTP141
TP160TPTP160
TP181TPTP181
TP150TPTP150
TP139TPTP139
TP131TPTP131
TP179TPTP179
TP159TPTP159
TP138TPTP138
TP148TPTP148
TP140TPTP140
TP178TPTP178
TP127TPTP127
TP158TPTP158
TP169TPTP169
TP157TPTP157
TP147TPTP147
TP137TPTP137
TP168TPTP168
TP129TPTP129
TP177TPTP177
TP149TPTP149
TP136TPTP136
AGL_B2_PIN_N12
AGL_B2_PIN_P12
AGL_B2_PIN_M12
AGL_B2_PIN_R14
AGL_B2_PIN_T15
AGL_B2_PIN_R13
AGL_B2_PIN_U15
AGL_B2_PIN_R12
AGL_B2_PIN_N11
AGL_B2_PIN_U14
AGL_B2_PIN_M11
AGL_B2_PIN_T13
AGL_B2_PIN_U13
AGL_B2_PIN_T12
AGL_B2_PIN_P10
AGL_B2_PIN_P11
AGL_B2_PIN_T11
AGL_B2_PIN_M10
AGL_B2_PIN_U11
AGL_B2_PIN_R10
AGL_B2_PIN_T10
AGL_B2_PIN_P9
AGL_B2_PIN_U10
AGL_B2_PIN_R9
AGL_B2_PIN_M9
AGL_B2_PIN_U9
AGL_B2_PIN_N9
AGL_B2_PIN_U8
U5C
U5C
SEC 3/6
SEC 3/6
BANK2
BANK2
AGLP125-CSG289
IO139RSB2
IO140RSB2
IO141RSB2
IO142RSB2
IO143RSB2
IO144RSB2
IO145RSB2
IO146RSB2
IO147RSB2
IO148RSB2
IO149RSB2
IO150RSB2
IO151RSB2
IO152RSB2
IO153RSB2
IO154RSB2
IO155RSB2
IO156RSB2
IO157RSB2
IO158RSB2
IO159RSB2
IO160RSB2
IO161RSB2
GDA2/IO105RSB2
GDB2/IO106RSB2
GDC2/IO107RSB2
GEA2/IO164RSB2
FF/GEB2/IO163RSB2
GEC2/IO162RSB2
T8
T7
R8
U6
T6
N8
R7
U5
T5
N7
U4
R5
U3
P7
T3
P6
R4
N6
P5
R3
M7
P4
M8
P15
N13
P16
R2
U1
T2
AGL_B2_PIN_T8
AGL_B2_PIN_T7
AGL_B2_PIN_R8
AGL_B2_PIN_U6
AGL_B2_PIN_T6
AGL_B2_PIN_N8
AGL_B2_PIN_R7
AGL_B2_PIN_U5
AGL_B2_PIN_T5
AGL_B2_PIN_N7
AGL_B2_PIN_U4
AGL_B2_PIN_R5
AGL_B2_PIN_U3
AGL_B2_PIN_P7
AGL_B2_PIN_T3
AGL_B2_PIN_P6
AGL_B2_PIN_R4
AGL_B2_PIN_N6
AGL_B2_PIN_P5
AGL_B2_PIN_R3
AGL_B2_PIN_M7
AGL_B2_PIN_P4
AGL_B2_PIN_M8
AGL_B2_PIN_P15
AGL_B2_PIN_N13
AGL_B2_PIN_P16
AGL_B2_PIN_R2
AGL_B2_PIN_T2
TP172TPTP172
TP126TPTP126
TP164TPTP164
TP132TPTP132
TP144TPTP144
TP171TPTP171
TP143TPTP143
TP182TPTP182
TP128TPTP128
TP133TPTP133
TP173TPTP173
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP156TPTP156
TP
TP176TPTP176
TP
TP167TPTP167
TP
TP155TPTP155
TP
TP135TPTP135
TP
TP175TPTP175
TP
TP174TPTP174
TP
TP152TPTP152
TP
TP154TPTP154
TP
TP125TPTP125
TP
TP134TPTP134
TP
TP287TPTP287
TP
TP153TPTP153
TP
TP288TPTP288
TP
TP289TPTP289
TP
TP151TPTP151
TP
TP145TPTP145
TP
IGLOO_FF [6]
Figure 2-4 • Bank 2 I/O Signals for AGLP125-CSG289
18 Revision 1
IGLOO PLUS Starter Kit User’s Guide
AGL_B3_PIN_H4
AGL_B3_PIN_G3
AGL_B3_PIN_H5
AGL_B3_PIN_G5
AGL_B3_PIN_G4
AGL_B3_PIN_G6
AGL_B3_PIN_F6
AGL_B3_PIN_J2
AGL_B3_PIN_L1
AGL_B3_PIN_H2
AGL_B3_PIN_H6
AGL_B3_PIN_K2
AGL_B3_PIN_K3
AGL_B3_PIN_F5
AGL_B3_PIN_E3
AGL_B3_PIN_N4
AGL_B3_PIN_T1
AGL_B3_PIN_E4
AGL_B3_PIN_M6
AGL_B3_PIN_N3
AGL_B3_PIN_L6
AGL_B3_PIN_M5
AGL_B3_PIN_N2
AGL_B3_PIN_P1
AGL_B3_PIN_M3
AGL_B3_PIN_M4
AGL_B3_PIN_P2
AGL_B3_PIN_L5
AGL_B3_PIN_K5
AGL_B3_PIN_K6
AGL_B3_PIN_J6
AGL_B3_PIN_L3
AGL_B3_PIN_J5
AGL_B3_PIN_H3
AGL_B3_PIN_J4
AGL_B3_PIN_G1
OSC_CLK [6]
PBRESET_N [6]
TP242TPTP242
TP
TP235TPTP235
TP
TP248TPTP248
TP
TP215TPTP215
TP
TP241TPTP241
TP
IO171RSB3
P2
IO172RSB3
M4
IO173RSB3
L5
IO174RSB3
P1
IO175RSB3
K5
IO176RSB3
M3
IO177RSB3
K6
IO178RSB3
N2
IO179RSB3
K4
IO180RSB3
N1
IO181RSB3
J6
IO182RSB3
L3
IO183RSB3
J5
IO184RSB3
M1
IO185RSB3
J4
IO195RSB3
H3
IO196RSB3
F2
IO197RSB3
H4
IO198RSB3
G3
IO199RSB3
H5
IO200RSB3
E2
IO201RSB3
G5
IO202RSB3
F3
IO203RSB3
G4
IO204RSB3
D1
IO205RSB3
D2
IO206RSB3
G6
IO208RSB3
F6
IO210RSB3
C1
GAA2/IO211RSB3
E4
GAB2/IO209RSB3
F5
GAC2/IO207RSB3
E3
GEA0/IO165RSB3
N4
GEA1/IO166RSB3
T1
GEB0/IO167RSB3
M5
GEB1/IO168RSB3
M6
GEC0/IO169RSB3
N3
GEC1/IO170RSB3
L6
GFA0/IO189RSB3
K2
GFA1/IO190RSB3
J2
GFA2/IO188RSB3
L1
GFB0/IO191RSB3
H2
GFB1/IO192RSB3
H6
GFB2/IO187RSB3
K3
GFC0/IO193RSB3
G1
GFC1/IO194RSB3
F1
GFC2/IO186RSB3
L2
BANK3
AGLP125 CSG289
SEC 4/6
U5D
AGLP125-CSG289
BANK3
SEC 4/6
U5D
TP206TPTP206
TP
TP213TPTP213
TP
TP209TPTP209
TP
TP225TPTP225
TP
TP203TPTP203
TP
TP218TPTP218
TP
TP214TPTP214
TP
TP245TPTP245
TP
TP227TPTP227
TP
TP224TPTP224
TP
TP249TPTP249
TP
Figure 2-5 • Bank 3 I/O Signals for AGLP125-CSG289
Revision 1 19
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