Microsemi IGLOO2 FPGA DSP FIR Filter Demo Manual
IGLOO2 FPGA DSP FIR Filter -
Libero SoC v11.7
DG0504 Demo Guide
Contents
1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 IGLOO2 FPGA DSP FIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3.2 Demo Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2.1 Data Handle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2.2 Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2.3 TPSRAM IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2.4 CoreUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2.5 CoreFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2.6 CoreFFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2.7 SYSRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2.8 OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2.9 CCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Setting Up the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.5 Programming the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Setting Up the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.2 Programming the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3 DSP FIR Demo GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Running the Demo Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3 Appendix: SmartDesign Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4 Appendix: Resource Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 Appendix: Coefficient Text File Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2 Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.3 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4 Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5 Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5.1 Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5.2 My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5.3 Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.6 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Figures
Figure 1. Top-Level Diagram of DSP FIR Filter Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Demo Design Files Top-Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. DSP FIR Filter Demo Design Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. IGLOO2 Evaluation Kit DSP FIR Filter Demo Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. USB to UART Bridge Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. FlashPro - New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. FlashPro Project Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. FlashPro Project RUN Passed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. DSP FIR Demo Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Serial Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Filter Generation - 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Filter Generation - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Filter Response and Filter Coefficient Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 14. Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 15. Input Signal and Input Signal FFT Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. DSP FIR Filter Demo - Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Filtered Signal: Time and Frequency Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. Filtered Signal: GUI Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. Text Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. Text Viewer: Filter Coefficient Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Text Viewer: Coefficients Save Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22. FIR Filter Demo: Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 23. DSP FIR Filter SmartDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 24. Coefficient File Example – 9 Taps, Decimal Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Tables
Table 1. Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. TPSRAM Configuration for Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. IGLOO2 FPGA Evaluation Kit Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. DSP FIR Filter Demo SmartDesign Blocks and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. DSP FIR Filter Demo Resource Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. MACC Blocks Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7. RAM1Kx18 Blocks Usage Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Preface
1Preface
1.1 Purpose
This demo is for IGLOO®2 field programmable gate array (FPGA) devices. It provides instructions on
how to use the corresponding reference design.
1.2 Intended Audience
This demo guide is intended for:
• FPGA designers
• System-level designers
1.3 References
The following documents are referred in this demo guide:
• UG0451: IGLOO2 FPGA and SmartFusion2 SoC FPGA Programming User Guide
• UG0450: SmartFusion2 SoC FPGA and IGLOO2 FPGA System Controller User Guide
• UG0448: IGLOO2 FPGA High Performance Memory Subsystem User Guide
Refer to the following web page for a complete and up-to-date listing of IGLOO2 device documentation: http://www.microsemi.com/products/fpga-soc/fpga/igloo2docs.
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IGLOO2 FPGA DSP FIR Filter
2 IGLOO2 FPGA DSP FIR Filter
2.1 Introduction
The IGLOO2 FPGA devices integrate a fourth generation flash-based FPGA fabric architecture, which
includes embedded mathblocks optimized specifically for digital signal processing (DSP) applications
such as, finite impulse response (FIR) filters, infinite impulse response (IIR) filters, and fast fourier
transform (FFT) functions.
This demo shows a DSP FIR filter application using the IGLOO2 device. In this DSP FIR filter application,
the host interface and the FIR filter are implemented in the fabric for low-pass, high-pass, band-pass, and
band-reject filtering operations. A user-friendly graphical user interface (GUI) generates the filter
coefficients, input signals (pass-band frequency and stop-band frequency), and also plots the input or
output waveforms, and the required spectrum. Microsemi CoreFIR filter IP is used to suppress the
unwanted frequency components, and CoreFFT IP is used to generate the output spectrum to verify the
filtering operation.
Figure 1 shows the top-level diagram for the DSP FIR filter demo.
Figure 1 • Top-Level Diagram of DSP FIR Filter Demo
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IGLOO2 FPGA DSP FIR Filter
'HVLJQ)LOHV
3URJUDPPLQJ)LOHV
,*/B),5B),/7(5B')
GRZQORDGBIROGHU!
*8,
5HDGPHW[W
2.2 Design Requirements
Table 1 lists the hardware and software requirements.
Table 1 • Design Requirements
Design Requirements Description
Hardware Requirements
IGLOO2 Evaluation Kit:
• FlashPro4 programmer
• USB A to Mini-B cable
Host PC or Laptop Windows 7 64-bit Operating System
Software Requirements
®
Libero
FlashPro Programming Software v11.7
Host PC Drivers USB to UART drivers
Framework Microsoft .NET Framework 4 Client for launching demo GUI
system-on-chip (SoC) v11.7
Rev C or later
2.3 Demo Design
2.3.1 Introduction
The design files are available for download from the following path in the Microsemi website:
http://soc.microsemi.com/download/rsc/?f=m2gl_dg0504_dsp_fir_filter_liberov11p7_df
The design files include:
• Design Files
•GUI
• Programming file
• Readme.txt file
Figure 2 shows the top-level structure of the design files. Refer to the Readme.txt file provided in the
demo file folder for the complete directory structure.
Figure 2 • Demo Design Files Top-Level Structure
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IGLOO2 FPGA DSP FIR Filter
'DWD+DQGOH
)LOWHU&RQWURO
)60
),5,1%XIIHU ),5287%XIIHU ),55HDO%XIIHU
))7,PDJLQDU\
%XIIHU
&RUH),5 &RUH))7
&RHI
2.3.2 Demo Design Description
This demo design uses the following blocks:
• Data Handle (user RTL)
• Filter Control (user RTL)
• TPSRAM IP (IPcore)
• CoreUART(IPcore)
• CoreFIR (IPcore)
• CoreFFT (IPcore)
• SYSRESET (IPcore)
• OSC (IPcore)
• CCC (IPcore)
Figure 3 shows the detailed block diagram of the demo design.
Figure 3 • DSP FIR Filter Demo Design Block Diagram
2.3.2.1 Data Handle
Data handle consists of the Core UART IP and the UART interface finite state machine handling the
control operations between the host PC (GUI interface) and the fabric logic. Control operations include
the loading of filter coefficients, filter input data to the corresponding input data buffer, coefficient buffers,
and send and receive data from the Host PC GUI.
2.3.2.2 Filter Control
Controls the FIR filter and the FFT operations. It loads the filtered data to the corresponding output buffer
and moves the FFT output data to the corresponding output data buffer.
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IGLOO2 FPGA DSP FIR Filter
2.3.2.3 TPSRAM IP
TPSRAM IP uses the following configurations:
• Filter coefficient buffer
• Input signal data buffer
• Output signal buffer
• Output signal FFT real data buffer
• Output signal FFT imaginary data buffer
Table 2 • TPSRAM Configuration for Data Buffers
Buffer Write Port Read Port
Depth Width Depth Width
Filter Coefficients 64 8 32 16
FIR Input Signal 2048 8 1024 16
FIR Output Signal 1024 16 1024 16
FFT Output Real Signal 256 16 256 16
FFT Output Imaginary Signal 256 16 256 16
2.3.2.4 CoreUART
The Core UART IP is used to transfer the data between the host PC (GUI) and IGLOO2. The Core UART
configuration is as follows:
• Version: 5.5.101
• TxFIFO: Disable TxFIFO
• RxFIFO: Disable RxFIFO
• RxLegacyMode: Disable
• Baud rate: 115200
• Number of bits: 8
•Stop bits: 1
• Parity: None
2.3.2.5 CoreFIR
The Core FIR IP is used in the Reloadable coefficient mode to support Low-pass, High-pass, Band-pass,
and Band-reject filters. The Core FIR IP configuration is as follows:
• Version: 8.6.101
• Filter Type: Single rate fully enumerated
• Number of Taps: 31
• Coefficients Type: Reloadable
• Coefficients Bit Width: 16 (signed)
• Data Bit Width: 16 (signed)
• Filter Structure: Transposed with symmetry
2.3.2.6 CoreFFT
The Core FFT IP is used for generating the frequency spectrum of the filtered data. Core FFT IP
configuration is as follows:
• Version: 6.4.105
• FFT Architecture: In place
• FFT Type: Forward
• FFT Scaling: Conditional
• FFT Transform Size: 256
• Width: 16
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IGLOO2 FPGA DSP FIR Filter
2.3.2.7 SYSRESET
The SYSRESET IP provides the power on reset signal.
2.3.2.8 OSC
The OSC IP is configured as an RC oscillator to provide the 50 MHz signal to the clock conditioning
circuit (CCC).
2.3.2.9 CCC
The CCC IP is configured to provide a 150 MHz clock signal. For detailed smart design implementation
and resource usage summary, refer to "Appendix: SmartDesign Implementation" on page 30.
2.4 Setting Up the Demo Design
The following steps describe how to setup the hardware demo:
1. Connect the jumpers on the IGLOO2 Evaluation Kit board, as shown in Ta bl e 3 .
Table 3 • IGLOO2 FPGA Evaluation Kit Jumper Settings
Jumper Pin (From) Pin (To) Comments
J22 1 2 Default
J23 1 2 Default
J24 1 2 Default
J8 1 2 Default
J3 1 2 Default
CAUTION: While making the jumper connections, the power supply switch SW7 must be switched
OFF.
2. Connect the Power supply to the J6 connector, switch ON the power supply switch, SW7.
3. Connect the FlashPro4 programmer to the J5 connector of the IGLOO2 Evaluation Kit board.
4. Connect the host PC USB port to the J18 USB connector on the IGLOO2 Evaluation Kit board using
the USB Mini-B cable.
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IGLOO2 FPGA DSP FIR Filter
Figure 4 shows the board setup for running the DSP FIR Filter demo on the IGLOO2 Evaluation Kit.
Figure 4 • IGLOO2 Evaluation Kit DSP FIR Filter Demo Setup
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