Micronas Intermetall SDA9588X, SDA9488X Datasheet

PRELIMINARY DATA SHEET

SDA 9488X PIP IV Basic
SDA 9588X OCTOPUS
Cost-effective
Picture-In-Picture IC s

Edition Feb. 28, 2001
6251-561-1PD

SDA 9488X

Preliminary Data Sheet

SDA 9588X

Cost effective Picture-In-Picture (PIP) ICs

Version 1.3 CMOS

General Description

SDA 9488X ’PIP IV Basic’ and SDA 9588X
’OCTOPUS’ belong to a new generation of cost­effective PiP processors that combine high-quality
digital PIP signal processing, digital multistandard
color decoding and AD/DA conversion on a single chip.
Both devices are equipped with CVBS and Y/C input
interfaces. In addition the SDA 9588X is also able to

P-DSO28-1

process YUV input signals for displaying high-quality
video signals e.g. coming from a DVD source.

Figure 0-1 Picture-In-Picture

The integrated digital color decoder is able to decode all analog TV standards (PAL,
NTSC and SECAM) and detects the standard automatically. Therefore the IC is suited
for world-wide use.

A picture reduction from 1/9 to 1/81 of original size selectable in fine steps is possible.
The transfer functions of the decimation filters are optimally matched to the selected
picture size reduction and can furthermore be adjusted to the viewer’s requirements by
a selectable peaking. A maximum of 216 luminance and 2x54 chrominance pixels per
line are stored in the memory.

Type Package

SDA 9488X P-DSO28-1

SDA 9588X P-DSO28-1

Micronas -2

SDA 9488X

Preliminary Data Sheet

SDA 9588X

1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

4 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.1 Analog Frontend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.1.1 Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.1.2 AD-Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.1.3 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.1.4 Signal Magnitudes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.2 Inset Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.3 Chroma Decoding And Standard Search . . . . . . . . . . . . . . . . . . . . . . . . . .13

4.4 Comb Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.5 Luminance Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.6 Decimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6.1 Single PIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.6.2 Horizontal And Vertical Fine Positioning . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6.3 Multi Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.7 Display Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.7.1 Mixed Standard Applications And (S)VGA Support . . . . . . . . . . . . . . . . .23

4.7.2 Display standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.7.3 Picture Positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.8 Output Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.8.1 Luminance Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.8.2 RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.8.3 Framing And Colored Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.8.4 16:9 Inset Picture Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.8.5 Parent Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.8.6 Select Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.9 DA-Conversion And RGB / YUV Switch . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.9.1 Contrast, Brightness and Peak Level Adjustment . . . . . . . . . . . . . . . . . .32

4.9.2 Pedestal Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.10 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.10.1 Closed Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.10.2 Widescreen Signalling (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.10.3 Indication Of New Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.10.4 Violence Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

6 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.1 I2C Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

6.2 I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Micronas -3

SDA 9488X

SDA 9588X

6.3 I2C bus Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.4 I2C Bus Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

9 Recommended Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

12 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Preliminary Data Sheet

Micronas -4

SDA 9488X

SDA 9588X

Preliminary Data Sheet

Features

1Features

• Single chip solution:
– AD-conversion for CVBS or Y/C or YUV

1)

, multistandard color decoding, PLL for
synchronization of inset channel, decimation filtering, embedded memory, RGB­matrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation
integrated on chip

• Analog inputs:
– 3x CVBS or 1x CVBS and 1x Y/C or 1xYUV (SDA 9588X) alternatively
– Clamping of each input
– All ADCs with 8 bit amplitude resolution
– Automatic Gain Control (AGC) for Y and CVBS

• Inset Synchronization:
– Multiple time constants for reliable synchronization
– Automatic recognition of 625 lines / 525 lines standard

• Color Decoder:
– PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 and SECAM
– Adjustable color saturation
– Hue control for NTSC
– Automatic Chroma Control (-24 dB ... +6 dB)
– Automatic recognition of chroma standards: different search strategies selectable
– Single crystal for all standards
– IF-characteristic compensation filter

• Decimation:
– PIP sizes between 1/81 and 1/9 adjustable with steps of 2 lines and 4 pixel
– Resolution up to 216 luminance and 2x54 chrominance pixels per inset line
– Horizontal and vertical filtering dependent on picture size

• Display Features:
– 7 bit per pixel stored in memory
– Field and joint-line free frame mode display
– Display on VGA and SVGA screen (f

limited to 40kHz)

H

– 8 different read frequencies for 16:9 compatibility
– Line doubling mode for progressive scan applications
– Freeze picture
– Coarse positioning at 4 corners of the parent picture
– Fine positioning at steps of 4 pixels and 2 lines

• Output signal processing:
–7 Bit DAC
– RGB or YUV switch: insertion of an external source without PIP processing
– Digital interpolation for anti-imaging

1)

available with SDA 9588X only

Micronas 1-5

SDA 9488X

SDA 9588X

Preliminary Data Sheet

– Adjustable transient improvement for luma (peaking)
– Contrast, Brightness and Pedestal Level adjustable
– Analog outputs: Y, +(B-Y), +(R-Y), or Y, -(B-Y), -(R-Y) or RGB
– Three RGB matrices available: NTSC(Japan), NTSC(USA) or EBU
– 64 different background colors and 4096 different frame colors
– Plain or 3D frame with variable width and height

• Data Slicing:
– Slicing of closed-caption (CC) or wide-screen-signaling (WSS) data
– Violence blocking capability (V-chip)
– Several filter for XDS data extraction

2

•I

C-Bus control (400 kHz)

• High stability clock generation

• PDSO 28-1 package (SMD)

• Full SDA 9489X and SDA 9589X upward compatibility

• SDA 9388X / SDA 9389X pinout compatibility

• 3.3V supply voltage (5V input capable)

Features

Micronas 1-6

SDA 9488X

SDA 9588X

Preliminary Data Sheet

2 Pin Configuration

XIN

XQ

HSP

VSP

SDA

SCL

VDD

VSS

I2C

INT

IN1

IN2

IN3

FSW

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PDSO 28 -1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

CVBS1

VREFM

CVBS2

VREFL

CVBS3

VSSA1

VDDA1

VREFH

VSSA2

VDDA2

OUT1

OUT2

OUT3

SEL

Figure 2-1 Pinning

Figure 2-2 Package Outlines

Micronas 2-7

SDA 9488X

SDA 9588X

Preliminary Data Sheet

Numb

er

1 XIN I crystal oscillator (input) or external clock input

2 XQ O crystal oscillator (output)

3 HSP I/TTL horizontal sync for parent channel

4 VSP I/TTL vertical sync for parent channel

5SDAI/OI

6SCL II

7 VDD S digital supply voltage

8 VSS S digital ground

9I2C II

10 INT O/TTL interrupt

11 IN1 I/ana V/R input for external YUV/RGB source

Name Type Description

2

C-bus data

2

C-bus clock

2

C Address

Pin Configuration

12 IN2 I/ana Y/G input for external YUV/RGB source

13 IN3 I/ana U/B input for external YUV/RGB source

14 FSW I fast switch input for YUV/RGB switch

15 SEL O fast blanking output for PIP

16 OUT3 O/ana analog output: chrominance signal +(B-Y) or -(B-Y) or B

17 OUT2 O/ana analog output: luminance signal Y or G

18 OUT1 O/ana analog output: chrominance signal +(R-Y) or -(R-Y) or R

19 VDDA2 S analog supply voltage for DAC

20 VSSA2 S analog ground for DAC

21 VREFH I/ana uppper reference voltage for ADC and DAC

22 VDDA1 S analog supply voltage for ADC

23 VSSA1 S analog ground for ADC

24 CVBS3 I/ana CVBS3 or V (SDA 9588X) or C Input

25 VREFL I/O lower reference voltage for ADC

26 CVBS2 I/ana CVBS2 or U (SDA 9588X) or Y (of Y/C) Input

27 VREFM I/O mid-level reference voltage for ADC

28 CVBS1 I/ana CVBS1 or Y (of YUV, SDA 9588X) Input

I= Input / ana=analog / O= Output / TTL=Digital (TTL) / S=Supply voltage

Table 2-1 Pin Description

Micronas 2-8

SDA 9488X

W

3

SDA 9588X

Preliminary Data Sheet

3 Block Diagram

DAC

Triple

VDDA2VSSA2VDD VSS

RGB

8

Over-

Peaking

DEMUX

Block Diagram

IN1

12

11

3x7bit

Matrix

Insertion

sampling

Frame

FS

IN3

IN2

13

Generation

18

14

Fast

RGB/YUV

OUT1OUT2OUT

16

17

Switch

Display

Controller

15

SEL

Parent

Sync

Processing

HSP VSP

MUX

H/V Scaler

Decimation

Skewcomp.

DUV/DCHR

DCVBS/DY

27

ADC

TRIPLE

3x8bit 1)

25

21

22 23 71920

VDDA1 VSSA1

eDRAM

Color

Decoder

Input

28

XTAL

XIN XQI2CSCL SDA

Synthesizer

Acquisition

Controller

1210965 34

20.25 MHz

INTR

1) SDA9588X, SDA 9488X: 2x8bit

512kbit

Memory

Controller

Inset

Sync

Y/C and

Gain

Sync

Processing

Sep.

PAL/ SECAM/ NTSC

Select

Clamp

24

26

Clock

Data Slicer

C

2

I

VREFH

VREFM

VREFL

CVBS1

CVBS2

Figure 3-1 Block Diagram

Micronas 3-9

CVBS3

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

4 System Description

4.1 Analog Frontend

4.1.1 Input Selection

An analog inset CVBS signal can be fed to the inputs CVBS1-3 of SDA 9588X resp. SDA
9488X. Each of these sources is selectable via I

2

C bus (CVBSEL). CVBS2 and CVBS3
can be used as separate Y/C inputs. YUV sources can be connected to CVBS1, CVBS2
and CVBS3 provided YUV operation at the SDA 9588X being enabled (YUVSEL). Using
an external switch the SDA 9588X can operate in applications with both YUV and CVBS
signals.

CVBSEL YUVSEL Input remark

D1 D0

CVBS1 CVBS2 CVBS3

0 0 0 CVBS

0 1 0 CVBS

1 0 0 Y (VBS) C Y/C mode

1 1 0 CVBS

X X 1 Y (VBS) U (CB) V (CR) YUV mode

(SDA 9588X only)

Table 4-1 Input selection

4.1.2 AD-Conversion

All signal are clamped and AD-converted with an amplitude resolution of 8bit. CVBS and
Y signals are clamped to the sync bottom whereas U/V and C signals are clamped to
their mid-level during blanking.

Inset
Video

HD

CLMPIST

CLAMPI

CLMPID

Figure 4-1 Clamping timing

Micronas 4-10

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust
to the specific application. The ADCs are driven by a 20.25 MHz free running crystal
clock which is not related to the incoming CVBS signal.

To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be
bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum (SDA
9588X) should not exceed 5 MHz. The digital filtering suppresses all frequencies above
the useable spectrum.

4.1.3 Automatic Gain Control

To accommodate to different CVBS input voltages an automatic gain control has been
implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5V

pp

For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if
available. The AGC behavior can be chosen out of four possibilities (AGCMDE):

The sync height serves as reference for the gain control in the typical application. When
using overflow detection only, the gain is set to maximum and is reduced whenever an
overflow occurs. This procedure will be executed again when a channel change is
detected or the gain control is manually reset by AGCRES.

.

2

1.5

1

Input Voltage [V]

0.5

0

0 2 4 6 8 10 12 14 16

Automatic Gain Control Characteristic

AGCVAL

Figure 4-2 AGC characteristic

4.1.4 Signal Magnitudes

The nominal CVBS signal with 75% color has a magnitude of 1 V
is left to permit signals with 100% color resulting in 1.23 V

pp

. The upper headroom

pp

. The Y signal must always
contain the sync part. Its levels correspond to the CVBS levels except for the missing
color and burst. After A/D conversion the video part is clamped to its black value and is
amplified to 224 digital steps. The nominal signal levels ensure correct brightness and
saturation. The YUV signal levels conform to the ITU 601 recommendation.

Micronas 4-11

SDA 9488X

SDA 9588X

Preliminary Data Sheet

CRYC = 1.2 Vpp

255

224

128

32

burst

0

255

217

68

upper headroom

white

black

burst

4
0

lower headroom

SRY = 1 Vpp

Figure 4-3 CVBS/Y and chroma ADC input signal range

255
240

212

255
240

212

System Description

upper headroom

75% chroma

lower headroom

upper headroom upper headroom

100% chroma

SRC = 0.89 Vpp

CRYC = 1.2 Vpp

75% U

128

SRUV = 0.7 Vpp

44

16

0

lower headroom

Figure 4-4 UV input signal range

AGCVAL Conversion

D3 D2 D1 D0

Range

CRYC

0000 0.5Vpp0.42V

... ... ...

1000 1.2V

pp

... ... ...

CRUV = 0.8 Vpp

Signal

Range

SRY

1.0V

pp

128

44
16

pp

75% V

CRUV = 0.8 Vpp

SRUV = 0.7 Vpp

0

Signal
Range

SRC

0.89V

lower headroom

pp

Conversion

Range

CRUV

0.8V

pp

Signal
Range

SRUV

0.7V

pp

1111 1.5V

pp

1.25V

pp

Table 4-2 ADC conversion range and required input signal voltage

Micronas 4-12

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

4.2 Inset Synchronization

Horizontal and vertical sync pulses are separated after elimination of the high frequency
components of the CVBS signal by a low pass filter. Horizontal sync pulses are
generated by a digital phase-locked-loop (DPLL). Its time constant is adjustable between
fast and slow behavior in four steps (PLLITC) to consider different input sources (e.g.
VCR). Noisy input signals become more stable when a noise-reduction is enabled
(NSRED). Additionally weak input signals from a satellite dish (’fishes’) become more
stable when SATNR is enabled. Both should be enabled to have best available
performance. When NOSIGB is enabled, a colored background is shown instead of the
picture when PIP is out of synchronization. The detected line standard is indicated by

SYNCSTAT.

4.3 Chroma Decoding And Standard Search

The system is able to decode NTSC and PAL signals with a subcarrier of 3.58MHz and

4.43MHz (PAL B/M/N/60, NTSC M/4.4) as well as SECAM signals with 4.05/4.2MHz
subcarrier. The system may be forced to a certain standard, or an automatic standard
detection can be used (CSTAND). For automatic standard detection, some standards
which are not likely to be received can be ignored to improve the detection process.

Depending on the detected line standard (525 or 625 lines) the color standard detection
circuit searches for 60 Hz signals (NTSC-M / PAL-M / PAL 60 / NTSC44) or 50 Hz signals
(PAL-B / SECAM / PAL-N) respectively. Within each line standard, the standard is
detected by consequently switching from one to another. This standard detection
process can be set to medium or fast behavior (LOCKSP). In medium behavior 30 fields
(in fast 20) are used to detect the standard. If not being successful within this time period
the system tries to detect another one. For SECAM detection, a choice between two
recognition levels is possible (SCMIDL) and the evaluated burstposition is selectable
(BGPOS).

.

CSTANDEX NTSC-

D1 D0

M

PAL60 PAL-N PAL-M PAL-B SECAM NTSC

44

00

0 .

1

10

11

Table 4-3 Considered color standards for automatic standard detection

For getting the chrominance information the digitized video signal is multiplied with the
regenerated color subcarrier once in-phase and once phase-shifted by 90°. After
lowpass filtering digital UV is available for PAL and NTSC. The subcarrier is regenerated

Micronas 4-13

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

by a digital PLL. At SECAM operation the PLL runs free and generates the line-wise
alternating subcarriers. A CORDIC structure demodulates the frequency-modulated UV
signals. The following SECAM de-emphasis filter characteristic is adjustable (DEEMP).

The chroma signal can be filtered before demodulation by means of a selectable IF­prefilter (IFCOMP).

0

5

10

gain [dB]

15

DEEMP = ’00’

DEEMP = ’01’

DEEMP = ’10’

DEEMP = ’11’

5

2.5

IFCOMP = ’00’

0

IFCOMP = ’01’

2.5

gain [dB]

IFCOMP = ’10’

5

7.5

3.58 4.4

20

0 0.5 1 1.5 2 2.5

frequency [MHz]

10

2 3 4 5 6

frequency [MHz]

Figure 4-5 SECAM de-emphasis filter characteristic and IF-compensation filter

characteristic

The Hue Control (HUE) influences the phase of the demodulation subcarrier between

-44.8° and 43.4° in steps of 1.4°. This is provided for NTSC only and adjustment is
ineffective for PAL and SECAM signals.

The reference for the subcarrier generation is a crystal stable clock of 20.25000 MHz. In
order to avoid color standard detection problems, the maximum deviation of this
frequency should not exceed 100ppm. For a good PLL locking behavior a maximum
deviation of 40ppm is recommended. A small frequency adjustment (-150 ... +310 ppm)
is possible for using a crystal with small frequency deviations (SCADJ). For test
purposes, CPLL allows to open the loop of the chroma PLL.

For deviations in the chroma signal up to 30dB, a stable output amplitude after chroma
decoding is achieved due to the ACC (Automatic Chroma Control). If the chroma signal
(color burst) is below a selectable threshold (CKILL), the color will be switched off.
Alternatively the color-killer can be bypassed and the color can be switched on or off
under all conditions (COLON). By setting ACCFIX, the automatic chroma control is
disabled and set to a default value.

Micronas 4-14

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

CKILL COLON color killed at damping of

D1 D0

0 0 0 30 dB

0 1 0 18 dB

1 1 0 24 dB

1 1 0 color always off

X X 1 color always on

Table 4-4 Color-killer adjustment

The bandwidth of the chroma filter is adjustable via CHRBW. The bandwidth depends
on whether the decoder is in SECAM operation or not. A change in CHRBW does not
result in a chrominance position shift on the screen.

CKSTAT can be read out and gives information whether the color is switched on or off.
STDET indicates the detected color standard. Additionally PALID signals whether a PAL

signal or a NTSC signal is applied.

4.4 Comb Filtering

Depending on the selected picture size and color standard, a comb filtering is performed
for luminance and chrominance. A comb filter uses the spectral interleaving of the
encoded luminance and chrominance to separate both without cross artifacts. Thus
cross-color and cross-luminance are suppressed effectively. For NTSC sources, a comb
filtering is performed for all picture sizes. Due to reduced bandwidth in horizontal and
vertical direction a strong reduction of cross artifacts can be achieved for PAL signals.
The same applies for the luminance signal of SECAM signals.

4.5 Luminance Processing

The A/D-converted CVBS (or Y) signal is digitally clamped to back porch. Depending on
the transmitted standard and operational area, an offset between black- and blanking
level can be found in the incoming signal (’7.5 IRE’). As for some applications a black
offset is not desired, controlling may be done using LMOFST. The positive or negative
offset is added to the Y signal before scaling.

Micronas 4-15

SDA 9488X

SDA 9588X

Preliminary Data Sheet

Received signal Processed signal

BLANK value

LMOFST

BLANK value

LMOFST

BLACK value

='00' (no additional offset)

BLACK value

='00' (no additional offset)

BLANK value

LMOFST

BLANK value

LMOFST

BLACK value

='10' (reduction of 16 LSB)

BLACK value

='01' (addition of 16 LSB)

Figure 4-6 Black level correction of luminance signal

System Description

M standard signals

B/G/H/I/N standard signals

The color carrier is removed out of a CVBS signal by means of a notch filter. It is set to
the corresponding color carrier (3.58 or 4.4 MHz) only if the standard is detected
permanently. This prevents the luminance sharpness of being changed within the
standard search process. For Y signals the notch is disabled.

For a fine adjustment of delaycompensation between luminance and chrominance,

YCDEL allows a luminance shifting in 16 steps of 50ns.

4.6 Decimation

4.6.1 Single PIP Mode

Luminance and chrominance signals are filtered in horizontal and vertical direction. The
coarse horizontal and vertical picture size (1/3, 1/4, 1/6) is independently programmable
with SIZEHOR and SIZEVER. A fine adjustment in steps of 4 pixel and 2 lines is possible
by HSHRINK and VSHRINK, which allows correct aspect ratio for multistandard
applications (50/60 Hz mixed mode, (S)VGA).

For main decimation factors, the stored number of pixel and lines are listed in the
following tables.

Micronas 4-16

SDA 9488X

SDA 9588X

Preliminary Data Sheet

SIZEHOR horizontal

scaling

D1 D0

00 3:1

PIP Pixel per line

Y (B-Y) (R-Y)

1)

216 54 54

System Description

0 1 3:1 216 54 54

1 0 4:1 160 40 40

1 1 6:1 108 27 27

1)

only used for compatiblity with other SDA 948xX/958xX types

Table 4-5 Number of stored pixel per line dependent on SIZEHOR

SIZEVER vertical scaling PIP lines

D1 D0

00

1)

3:1 88 72

625 lines source 525 lines source

01 3:1 88 72

10 4:1 66 54

11 6:1 44 36

1)

only used for compatibility with other SDA 948xX/958xX types

Table 4-6 Number of stored lines per field

Micronas 4-17

SDA 9488X

SDA 9588X

Preliminary Data Sheet

0 1 3,00 216 0 3 6,00 108
1 1 3,04 212 1 3 6,23 104
2 1 3,11 208 2 3 6,48 100
3 1 3,17 204 3 3 6,75 96
4 1 3,23 200 4 3 7,04 92
5 1 3,29 196 5 3 7,35 88
6 1 3,37 192 6 3 7,70 84
7 1 3,44 188 7 3 8,10 80
8 1 3,51 184 8 3 8,52 76

9 1 3,60 180 9 3 8,99 72
10 1 3,67 176 10 3 9,51 68
11 1 3,76 172 11 3 10,12 64
12 1 3,84 168 12 3 10,64 60

13 1 3,94 164

0 2 4,05 160

1 2 4,16 156

2 2 4,27 152

3 2 4,38 148

4 2 4,50 144

5 2 4,63 140

6 2 4,77 136

7 2 4,91 132

8 2 5,06 128

9 2 5,22 124
10 2 5,41 120
11 2 5,59 116
12 2 5,78 112

System Description

Table 4-7 Number of stored pixel per line dependent on HSHRNK

Micronas 4-18

SDA 9488X

SDA 9588X

Preliminary Data Sheet

625 lines 525 lines 625 lines 525 lines

0 1 3,00 88 3 72 0 3 6,00 44 6,00 36
1 1 3,07 86 3,09 70 1 3 6,28 42 6,38 34
2 1 3,14 84 3,19 68 2 3 6,61 40 6,75 32
3 1 3,21 82 3,28 66 3 3 6,94 38 7,22 30
4 1 3,30 80 3,38 64 4 3 7,31 36 7,73 28
5 1 3,38 78 3,49 62 5 3 7,78 34 8,30 26
6 1 3,47 76 3,61 60 6 3 8,25 32 9,00 24
7 1 3,56 74 3,73 58 7 3 8,81 30 9,80 22
8 1 3,66 72 3,87 56 8 3 9,42 28 10,78 20

9 1 3,77 70 9 3 10,17 26

10 1 3,89 68 10 3 11,02 24

0 2 4,00 66 4,01 54
1 2 4,13 64 4,15 52
2 2 4,25 62 4,31 50
3 2 4,41 60 4,5 48
4 2 4,56 58 4,69 46
5 2 4,72 56 4,9 44
6 2 4,88 54 5,13 42
7 2 5,06 52 5,39 40
8 2 5,28 50 5,7 38
9 2 5,50 48

10 2 5,75 46

System Description

Table 4-8 Number of stored lines per field dependent on VSHRNK

4.6.2 Horizontal And Vertical Fine Positioning

All picture sizes are pre-centered inside the frame. In addition, if necessary the vertical
and horizontal acquisition area can be shifted by VFP for vertical and HFP for horizontal
direction.

4.6.3 Multi Display Mode

SDA 9488X and SDA 9588X offer the feature to display a sub-picture more than once.
The picture size and arrangement depends on the display mode (DISPMOD) and not on
SIZEHOR or SIZEVER. Hence variable scaling is not possible in these modes.

Micronas 4-19

SDA 9488X

SDA 9588X

Preliminary Data Sheet

Display

Mode

DISPMOD Size Picture

D1 D0 625 525

100SIZEHOR/

configuration

single PIP mode, 216
SIZEVER
HSRHNK/

System Description

Pixel Lines

88

-

60

-

24

72

-

20

VSHRNK

2 0 1 3 X1/9 one upon another

216 264 216

(same content)

3 1 0 4 X 1/16 one upon another

156 264 216

(same content)

Table 4-9 Multi-display modes

The display modes are shown in the appendix. The sizes of the partial pictures are listed
in table 4-9.

4.7 Display Control

The on-chip memory capacity is 512 kbits. Provided that the same standard (50 or 60

video sources are applied to inset and parent channel, jointline-free frame mode

Hz)
display is possible. This means that every incoming field is processed and displayed by
the SDA 9488X/SDA 9588X processor. The result is a high vertical and time resolution.
For this purpose the standard is analyzed internally and frame mode display is blocked
automatically, if the described restrictions are not fulfilled. Then only every second
incoming field is shown (field mode). Field mode normally shows jointlines. This is
caused by an update of the memory during read out. The result is that one part of the
picture contains new picture information and the other part contains one earlier written
field. The switching from or to frame mode is free of artifacts.

Activation of frame-mode display is blocked automatically if at least one of the following
conditions is not fulfilled:

• Inset and parent channel have the same field repetition frequency. This means that
frame mode is possible only for 50Hz inset and parent sources or 60Hz inset and
parent sources.

• Interlace signal is detected for inset and parent channel. For progressive scan or
(S)VGA display therefore only field mode is possible. For some VCRs in trick mode,
often no interlace is detected also.

• The number of lines is within a predefined range for inset (FMACTI) or parent
(FMACTP) channel (assuming standard signals according to ITU)

Micronas 4-20

SDA 9488X

SDA 9588X

Preliminary Data Sheet

FMACTP parent

standard

number of

lines per field

FMACTI inset

standard

System Description

number of

lines per field

0 50 Hz 310...315 0 50 Hz 310...315

1 50 Hz 290...325 1 50 Hz 290...325

0 60 Hz 260...265 0 60 Hz 260...265

1 60 Hz 250...275 1 60 Hz 250...275

Table 4-10 Required number of lines for frame mode display

The system may be forced to field mode by means of FIESEL. Either first or second field
is selectable. ’One of both’ takes every second field independent of the field number.
This is meant for sources generating only one field (e.g. video-games).

For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling
mode is available (PROGEN). Every line of the inset picture is read twice.

Memory writing is stopped by FREEZE bit. The field stored in the memory is then
continuously read. As the picture decimation is done before storing, the picture size of a
frozen picture can not be changed.

Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed. Synchronization of memory reading with the
parent channel is achieved by processing the parent horizontal and vertical
synchronization signals. Horizontal and vertical pulses may be provided. The signals are
fed to the IC at pin HSP for horizontal synchronization and pin VSP for vertical
synchronization. HSPINV or VSPINV respectively allow an inversion of the expected
signal polarity.

HSP

VSP

VSPD

(internal)

VSPDEL VSPDEL

field 0 window field 1 window

←

tH/2 = 32 (16)

s

tH = 64 (32) ←s

=151 (75) ←s

max

values in brackets () apply for 100Hz systems

Figure 4-7 Field detection and phase adjustment of vertical pulse (VSP)

Micronas 4-21

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

As the external VSP and HSP signals may come from different devices with different
delay paths, the phase between V-sync and H-sync is adjustable (VSPDEL). An
incorrect setting of VSPDEL may result in wrong or unreliable field detection of parent
channel.

Normally a noise reduction of the incoming parent vertical pulse is performed. With this
function missing vertical pulses are compensated. The circuit works for 50/60 Hz
applications as well as progressive and 100/120Hz application. (S)VGA signals are
supposed to be very stable and therefore not supported by the noise suppression. By
means of VSPNSRQ, vertical noise suppression is switched off.

A great variety of combinations of inset and parent frequencies are possible. The
following table shows some constellations:

Inset

Frequency

Parent

1)

Frequency

(HSP/VSP)

1)

frame
mode

correct aspect

ratio

(single pip)

correct aspect

ratio

(multi display)

vertical

noise

suppression

selectable

50 50i
50 60i
60 50i
60 60i
50 50p
50 60p
60 50p
60 60p
50 100i
50 120i
60 100i
60 120i
50 (S)VGA
60 (S)VGA

1)

standard signals supposed

2)

valid for some parent frequencies. Please refer to Chapter 4.7.1

2)

2)

Table 4-11 Available Features with varying inset and parent standards

Micronas 4-22

SDA 9488X

SDA 9588X

Preliminary Data Sheet

4.7.1 Mixed Standard Applications And (S)VGA Support

remark

(N

apel

X N

aline

@ fV)

720X576@50Hz

(TV)

702X488@60Hz

(TV)

720X576@100Hz

(TV 100 Hz)

702X488@120Hz

(TV 120 Hz)

720X576@50Hz
(TV progressive)

fH

(kHz)

TH

←s)

(

T

Hact

←s)

15.6 64.0 52.0 625/

15.7 63.6 52.7 525/

31.2 32.0 26.0 625/

31.2 31.8 26.4 525/

31.2 32.0 26.0 625/

(

lines/

active

576

488

576

488

576

f

dot

(MHz)

13.5 interlace

13.5 interlace

27 interlace

27 interlace

27 prog-

System Description

scan correct

aspect

ratio

ressive

702X488@60Hz
(TV progressive)

640X480@60Hz

(VGA)

640X480@72Hz

(VGA)

640X480@75Hz

(VGA)

800X600@56Hz

(SVGA)

800X600@60Hz

(SVGA)

800X600@72Hz

(SVGA)

800X600@75Hz

(SVGA)

31.2 31.8 26.4 525/
488

31.5 31.8 25.4 525/
480

37.9 26.4 20.3 520/
480

37.5 26.7 20.3 500/
480

35.2 28.4 22.2 625/
600

37.9 26.4 20.0 625/
600

48.1 20.8 16.0 666/
600

46.9 21.3 16.2 625/
600

27 prog-

ressive

25.2 prog­ressive

31.5 prog­ressive

31.5 prog­ressive

36.0 prog­ressive

40.0 prog­ressive

50.0 prog­ressive

49.5 prog­ressive

800X600@85Hz

(SVGA)

1024X768@43Hz

(SVGA)

53.7 18.6 14.2 631/
600

35.5 28.2 22.8 817/
768

Table 4-12 Examples of supported parent signals

Micronas 4-23

56.3 prog­ressive

44.9 interlace

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

The SDA 9488X resp. SDA 9588X allow multiple scan rates for the use in desktop video
applications, VGA compatible or 100Hz TV sets. All features are provided in ’normal’
operating modes at auto detected 50Hz and 60 Hz parent and inset standards. 2f
modes (100/120Hz and progressive) are supported by line frequency- and pixel clock
doubling and are not detected automatically. Even on a 16:9 picture tube correct aspect
ratio can be displayed by selecting the approbiate parent clock. The video synthesizer
generates also a special pixel clock for VGA display (see chapter 5.5.9 for details). As
(S)VGA consists of a variety of scan rates the correct aspect ratio is not adjustable for
all modes with the parent clock (HZOOM) because of the limited count of frequencies.
For single PIP only, correct aspect ratio is maintained by the vertical and horizontal
scaler (HSHRINK and VSHRINK).

It is possible to display (S)VGA sources for parent display, as long as the horizontal
frequency is lower than 40 kHz and the signal does not contain more than 1023 lines.
For progressive scan mode, PROGEN must be set. Additionally field-mode should be
forced to prevent unallowed frame-mode displaying (FIESEL). As the (S)VGA normally
does not fit to the display raster generated in the vertical noise suppression, VSPNSRQ
should be disabled. (S)VGA signals for inset channel are not supported.

H

PROGEN READD Expected input signal

0 0 50 or 60 Hz signal interlace

0 1 100 or 120 Hz signals interlace

1 0 (reserved)

1 1 50 or 60 Hz or (S)VGA signal progressive

Table 4-13 Selection of display field repetition

4.7.2 Display standard

For a single-PiP, the number of displayed lines depends on the selected picture size and
on the signal standard. For multi picture display, the number of displayed lines depends
on the selected picture size and on the signal standard of the parent signal. Additionally,
a standard can be forced by DISPSTD.

Micronas 4-24

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

DISPSTD DISPMOD Display Standard

D1 D0

0 0 0 PIP depends on detected inset standard (single pip)

0 0 >0 PIP depends on detected parent standard (multi display)

0 1 x PIP display is always in 625 lines mode

1 0 x PIP display is always in 525 lines mode

1 1 x freeze last detected display standard and size

Table 4-14 Display standard selection

If a 625 lines picture is shown with a 525 lines parent signal, some lines are missing on
top and bottom of picture. If a 525 lines picture is shown with a 625 lines display
standard, missing lines at top and bottom are filled with background color.

4.7.3 Picture Positioning

The display position of the inset picture is programmable to the 4 corners of the parent
picture (CPOS). From there PIP can be moved to the middle of the TV Picture with
POSHOR and POSVER. The corner positions can be centered coarsely on the screen
with POSOFH and POSOFV. Depending on coarse position, one PIP corner remains
stable when changing the picture size.

CPOS Coarse

D1 D0

Position

Reference

corner of PiP

increasing

POSVER

increasing

POSHOR

0 0 upper left upper left down right

0 1 upper right upper right down left

1 0 lower left lower left up right

1 1 lower right lower right up left

Table 4-15 Coarse Positioning

Starting at every coarse position, the picture is movable to 256 horizontal locations (4
pixel increments) and 256 vertical locations (2 line increments). The pixel width on the
screen depends on the selected HZOOM factor. Even POP-positions (Picture Outside
Picture) in 16:9 applications are possible.

Micronas 4-25

SDA 9488X

y

SDA 9588X

Preliminary Data Sheet

POSHOR

System Description

CPOS='01'

CPOS='00'

POSVER

CPOS='10'

CPOS='11'

POSHOR

POSVER

Figure 4-8 Coarse Positioning

4.8 Output Signal Processing

4.8.1 Luminance Peaking

To improve picture sharpness, a peaking filter which amplifies higher frequencies of the
input signal is implemented. The amount of peaking can be varied in seven steps by
YPEAK. The setting ’000’ switches off the peaking. The value ’011’ is recommended.
This provides a good compromise between sharpness impression and annoying
aliasing. The characteristic for all possible settings is shown in fig. (4-9)

10

9

8

7

6

5

gain [dB]

4

3

2

1

0

0 0.1 0.2 0.3 0.4 0.5

normed frequenc

YPEAK = ’111’

YPEAK = ’110’
YPEAK = ’101’

YPEAK = ’100’

YPEAK = ’011’

YPEAK = ’010’

YPEAK = ’001’

YPEAK = ’000’

Figure 4-9 Characteristics of selectable peaking factors

Micronas 4-26

SDA 9488X

SDA 9588X

Preliminary Data Sheet

System Description

Coring should be switched on by YCOR to reduce noise, which is also amplified when
peaking is enabled. As the coring stage is in front of the peaking filter, 1 LSB noise will
not be peaked.

4.8.2 RGB Matrix

The chip contains three different matrices, one suited for EBU standards, one suited for
NTSC-Japan and one suited for NTSC-USA, which are selected via MAT. The signal
OUTFOR switches between YUV output or RGB output. The signal UVPOLAR inverts
the U and V channels and results in Y-U-V output. The standard magnitudes and angles
of the color-difference signals in the UV-plane are defined as follows:

MAT Magnitudes Angles Standard

D1 D0

(B-Y) (R-Y) (G-Y) (B-Y) (R-Y) (G-Y)

0 0 2.028 1.14 0.7 0 90 236 EBU

0 1 2.028 1.582 0.608 0 95 240 NTSC (Japan)

1 0 2.028 2.028 0.608 0 105 250 NTSC (USA)

1 1 (reserved)

Table 4-16 RGB matrices characteristics

The color saturation can be adjusted with SATADJ register in 16 steps between 0 and

1.875. Values above 1.0 may clip the chrominance signals.

4.8.3 Framing And Colored Background

Figure 4-10 Normal frame and 3D frame

Micronas 4-27