Micronas Intermetall MAS3507D Datasheet

PRELIMINARY DATA SHEET

MICRONAS

MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder

Edition Oct. 21, 1998 6251-459-2PD

MICRONAS

MAS 3507D PRELIMINARY DATA SHEET

Contents

Page Section Title

4 1. Introduction

4 1.1. Features 5 1.2. Application Overview 5 1.2.1. Multimedia Mode 5 1.2.2. Broadcast Mode

6 2. Functional Description of the MAS 3507D

6 2.1. DSP Core 6 2.2. Firmware (Internal Program ROM) 7 2.3. Program Download Feature 7 2.4. Baseband Processing 7 2.4.1. Volume Control / Channel Mixer 7 2.4.2. Mute / Bypass Tone Control 7 2.4.3. Bass / Treble Control 8 2.5. Clock Management 8 2.6. Power Supply Concept 8 2.6.1. Voltage Monitor 9 2.6.2. DC/DC Converter 9 2.6.3. Stand-by Functions 9 2.6.4. Start-up Sequence 10 2.7. Interfaces 10 2.7.1. MPEG Bit Stream Interface 10 2.7.2. Audio Output Interface

10 2.7.2.1. Mode 1:16 Bits/Sample (I 10 2.7.2.2. Mode 2:32 Bit/Sample (Inverted SOI) 11 2.7.2.3. Other Output Modes 11 2.7.3. Start-up Configuration 11 2.7.4. Parallel Input Output Interface (PIO)

S Compatible Data Format)

13 3. Control Interfaces

13 3.1. I

C Bus Interface 13 3.1.1. General 13 3.1.2. Subaddresses

14 3.1.3. I 14 3.1.3.1. I 14 3.1.3.2. I

C Registers

C Control Register

C Data Register 14 3.2. Command Structure 14 3.2.1. The Internal Fixed Point Number Format 14 3.2.2. Conventions for the Command Description 15 3.3. Detailed MAS 3507D Command Syntax 15 3.3.1. Run 15 3.3.2. Read Control Interface Data 16 3.3.3. Write Register 16 3.3.4. Write D0 Memory 16 3.3.5. Write D1 Memory 16 3.3.6. Read Register 17 3.3.7. Read D0 Memory 17 3.3.8. Read D1 Memory

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PRELIMINARY DATA SHEET

Contents, continued

Page Section Title

17 3.3.9. Default Read 18 3.4. Register Table 18 3.4.1. DC/DC Converter 20 3.4.2. Muting / Bypass Tone Control 20 3.4.3. Bass and Treble Control 22 3.5. Memory Area 22 3.5.1. Status Memory 22 3.5.1.1. MPEG Frame Counter 22 3.5.1.2. MPEG Status 1 23 3.5.1.3. MPEG Status 2 26 3.5.1.4. CRC Error Counter 26 3.5.1.5. Number Of Ancillary Bits 26 3.5.1.6. Ancillary Data 28 3.5.2. Configuration Memory 29 3.5.2.1. PLL Offset for 44/48 kHz Sampling Frequency 30 3.5.2.2. Output Configuration 31 3.5.3. Baseband Volume Matrix

MAS 3507D

33 4. Specifications

33 4.1. Outline Dimensions 34 4.2. Pin Connections and Short Descriptions 36 4.3. Pin Descriptions 36 4.3.1. Power Supply Pins 36 4.3.2. DC/DC Converter Pins 36 4.3.3. Control Lines 36 4.3.4. Parallel Interface Lines 36 4.3.4.1. PIO Handshake Lines 36 4.3.4.2. PIO Data Lines 37 4.3.5. Voltage Supervision And Other Functions 37 4.3.6. Serial Input Interface 37 4.3.7. Serial Output Interface 37 4.3.8. Miscellaneous 38 4.4. Pin Configurations 39 4.5. Internal Pin Circuits 40 4.6. Electrical Characteristics 40 4.6.1. Absolute Maximum Ratings 40 4.6.2. Recommended Operating Conditions 41 4.6.3. Characteristics

42 4.6.3.1. I 43 4.6.3.2. I 44 4.6.3.3. I 44 4.6.4. Firmware Characteristics 45 4.6.4.1. Timing Parameters of the Demand Mode 46 4.6.5. DC/DC Converter Characteristics 48 4.6.6. Typical Performance Characteristics

C Characteristics

S Bus Characteristics – SDI

S Characteristics – SDO

50 5. Data Sheet History

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MAS 3507D PRELIMINARY DATA SHEET

MPEG 1/2 Layer 2/3 Audio Decoder

Release Note: Revision bars indicate significant changes to the previous edition.

1. Introduction

The MAS 3507D is a single-chip MPEG layer 2/3 audio decoder for use in audio broadcast or memory-based playback applications. Due to embedded memories, the embedded DC/DC up-converter, and the very low power consumption, the MAS 3507D is ideally suited for portable electronics.

In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used in DVB, ADR, and DAB) achieves a compression of 8:1 providing CD quality.

In order to achieve better audio quality at low bit rates (<64 kbit/s per audio channel), three additional sampling frequencies are provided by MPEG 2 (ISO 13818-3). The MAS 3507D decodes both layer 2 and layer 3 bit streams as defined in MPEG 1 and 2. The multichannel/multilingual capabilities defined by MPEG 2 are not supported by the MAS 3507D. An extension to the MPEG 2 layer 3 standard developed by FhG Erlangen, Germany sometimes referenced as MPEG 2.5, for extremely low bit rates at sampling frequencies of 12, 11.025, or 8 kHz is also supported by the MAS 3507D.

1.1. Features

– Single-chip MPEG 1/2 layer 2 and 3 decoder – ISO compliance tests passed

– Bit streams with adaptive bit rates (bit-rate switch-

ing) are supported.

– Serial asynchronous MPEG bit stream input – Broadcast and multimedia operation mode – Automatic locking to given data rate in broadcast

mode

– Data request triggered by ’demand signal’ in multi-

media mode

– Output audio data delivered via an I

S bus (in vari-

ous formats)

– Digital volume / stereo channel mixer / Bass / Treble – Output sampling clocks are generated and con-

trolled internal ly.

– Ancillary data provided via I – Status information accessible via PIO pins or I

C interface

–“CRC Error” and “MPEG Frame Synchronization”

Indicators

– Pow er management for reduced power consumption

at lower sampling frequencies

– Low power dissipation (53 mW @ f

90 mW @ f

≤ 24 kHz, 165 mW @ fs > 24 kHz @

≤ 12 kHz,

3V)

– Supply voltage range: 1.6 V to 3.6 V due to built-in

DC/DC converter (2-cell battery operation)

– Adjustable power supply supervision – Power-off function – Data processing by a high-performance RISC DSP

core (MASC)

– Additional functiona lity ach ievable via download

software (CELP voice Decoder, ADPCM encoder / decoder)

– Extension to MPEG 2 / layer 3 for low bit rates

(MPEG 2.5)

14.725 MHz or

14.592 MHz CLKI

CLKO

decoded output

/3/

MPEG 1/2 audio bit stream

/2/

Clock

Synthesizer

Serial Out

Serial In

MPEG frame sync CRC error

MAS

3507D

RISC DSP Core

DC/DC

Converter

PIO

/3/

/8+5/

serial control

/2/

Fig. 1–1: MAS 3507D block diagram

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PRELIMINARY DATA SHEET MAS 3507D

1.2. Application Overview

The MAS 3507D can be ap plied in two major environments: in multimedia m ode or in broadc ast mode. For both modes, the DAC 3550A fits perfectly to the requirements of the MAS 3507D. It is a high-quality multi sample rate DAC (8 kHz ... 50 kHz) with in ternal crystal oscillator and integrated stereo headphone amplifier.

1.2.1. Multimedia Mode

In a memor y-based mult imedia environm ent, the eas iest way to incorporate a MAS 3507D decoder is to use its data-demand pi n. This pin can be used direct ly to request input bit strea m data from the hos t or me mory system.

While the demand pin is active, the data stream shall be transmitted to the MAS 3507D. The bit stream clock should be higher than the actual data rate of the MPEG bit stream (1 MHz bi t stream clock works with all MPEG bit rates). T he demand signal will be active until the input buffer of the MAS 3507D is filled.

A delayed response of the host to the demand sign al (by several milliseconds) or an interrupted resp onse of the host will be tolerated by the MAS 3507D as long as the input buffer does not run empty. A PC might use its DMA capabilities to transfer the data in the background to the MAS 3507D without interfering with its foreground processes.

The source of the bit stream may be a memory ( e.g. ROM, Flash) or PC peripherals, such as CD-ROM drive, an ISDN card, a hard disk or a floppy disk drive.

1.2.2. Broadcast Mode

In environments where th e bi t str eam is del ivered fr om an independent transmitter to one or more receivers, the MAS 3507D cannot act as master for the bit stream clock. In this mode, it synchr onizes itsel f to the inc oming bit stream dat a rate by a d igital P LL and gen erate s a synchronized digital audio sample clock for the required output sample rates.

Host

(PC, Controller)

ROM, CD-ROM, RAM, Flash Mem. ..

I2C

demand signal

demand clock

MPEG bit stream

MAS

3507D

CLKI

I2S

DAC

3550A

CLKOUT

14.725 MHz

line out

Fig. 1–2: Block diagram of a MAS 3507D, decoding a stored bit stream in multimedia mode

Receiver

Front-end

control I2C

L3 bit stream

(fixed rate)

clock

MAS

3507D

CLKI

I2S

DAC

3550A

CLKOUT

14.725 MHz

line out

Fig. 1–3: Block diagram of a MAS3507D in a broadcast environment

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MAS 3507D PRELIMINARY DATA SHEET

2. Functional Description of the MAS 3507D

2.1. DSP Core

The hardware of the MAS 3507D consists of a high performance RISC Digital Signal Processor (DSP) and appropriate in ter faces (see Fig. 2–1) . Th e i nte rnal processor works wit h a me mory wo rd le ngt h of 20 bi ts a nd an extended range of 32 bits in i ts accumulators. The instruction set of the DSP i s highl y opti mized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All data input and output actions are based on a ‘non cycle stealing’ background DMA that does not cause any computational overhead.

2.2. Firmware (Internal Program ROM)

A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as input. The signal lines are a clock line SIC and the data line SID. The MPEG decoder performs the audio decoding. The steps for decoding are

– synchronization, – side information extraction, – Huffman decoding, – ancillary data extraction, and – volume and tone control.

For the supported bit rates and sample rates, see Ta bl e 3 –11 on page 25. Frame Synchronization and CRC-error signals are provided at the output pins of the MAS 3507D.

MPEG Bit Stream

Digital Audio Output

Volume

Tone

Control

Sync

MPEG

Decoder

Status Start-up Config.

Fig. 2–1: Block diagram of the MPEG Decoder

PIO

Ancillary Data

Decoder Status

Config. Reg.

to µC

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PRELIMINARY DATA SHEET MAS 3507D

2.3. Program Download Feature

This is an addi tional feature t hat is not r equi red for the MPEG decoding function.

The overall function of the MAS 3507 D can be alte red by downloading up to 1 kWord program code into the internal RAM and executing this code instead of the ROM code. During this time, MPEG decoding is not possible.

The code must be downloaded by the ‘write to memory’ command (see Sectio n 3.3.) into an are a of RAM that is switchable from data mem or y to program m emory. A ‘run’ command (see Section 3.3.1.) star ts the operation.

Micronas provides modules for voice-decoding using the CELP algorithm (performing good sp eech quality at very low bit rates) and for encoding and de coding audio data with ADPCM.

Otherwise, the customer can write its own modules (knowledge in DSP programming is necessary).

Detailed information ab out downloading is provided in combination with the MAS 3507D software development package from Micronas.

2.4. Baseband Processing

2.4.1. Volume Control / Channel Mixer

A digital volume control ma trix is applied to th e digital stereo audio data. This performs additional balance control and a simple kind of stereo basewidth enhancement. The 4 factors LL, LR, RL , and RR are adjustable via the c ontro ller wi th 20- bit re solu tion . See Fig. 3–2 and Section 3.5.3. for details.

2.4.2. Mute / Bypass Tone Control

A special bit enables a fast and simple mute functionality without changing the current volume setting. Another bit allows to bypass the complete bass / treble / volume control. See for details Section 3.4.2..

2.4.3. Bass / Treble Control

Tone control is implemented in the MAS 3507D. It allows the control of bass and treble in a range up to ±15 dB, as Table 3–8 shows. To prevent overflow or clipping effects, the prescaler is built-in. The pr escaler decreases the overall gain of the tone fi lter, so the full range up to +15 dB is usable without clipping.

For commercial issues and detailed information please contact our sales department.

Due to the different frequency ranges in MPEG 1, MPEG 2, or MPEG 2.5, the bass cutoff frequencies differ.

Ta ble 2–1: Settings for the digital volume matrix

Cutoff

Bass Treble

MPEG1 100 Hz 10 kHz MPEG2 200 Hz 10 kHz MPEG2.5 400 Hz 10 kHz

For details see Section 3.4.3..

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MAS 3507D PRELIMINARY DATA SHEET

2.5. Clock Management

The MAS 3507D is driven by a single clock at a frequency of 14.592 MHz or, alternatively, 14.725 MHz. It is possible to drive the MAS 3507D with other reference clocks (see Section 3.5.2.1. on page 29).

The CLKI signal acts as a reference for the embedded clock synthesizer that generates the internal system clock. Based on the reference input clock CLKI, a synchronized output clock CLKO that depends on the audio sample frequency of the decompressed bit stream is generated a nd provided as ‘mast er clock’ to external D/A converters. Some DACs need master clocks that have a fixed relation to the sampling frequencies. A scaler can be switched on duri ng start-up, optionally, by activating the PI8 pin. Th en, the cloc k -out will automatically b e div ided by 1, 2, o r 4 a s define d in Table 2–2.

Table 2–2: CLKO Frequencies

fs/kHz CLKO/MHz

scaler on

CLKO/MHz scaler off

48, 32 24.576 24.576

2.6. Power Supply Concept

The MAS 3507D offers an embedded controlled DC/ DC converter for battery based power supply concepts. It works as an up-converter.

2.6.1. Voltage Monitor

A voltage monitor compares the input voltage at the VSENS pin with an internal reference value that is adjustable via I

C bus. The PUP output pin becomes inactive when the voltage at the VSENS pin drops below the reference voltage. The voltage monitor function can be activated independently of the DC/DC converter operation (see Fig. 2–2 for application circuit without DC/DC converter functionality).

The PUP signal can be read out by the system controller. The controller again may be connected with the corresponding in put line WSEN of the MAS 3507D to activate MPEG decoding. It is important that the WSEN must not be activated before the PUP is gene rated. In applications without controller, it is recommended to connect PUP with WSEN. The PUP signal thresholds are listed in Table 3–7.

44.1 22.5792 22.5792 24, 16 12.288 24.576

22.05 11.2896 22.5792 12, 8 6.144 24.576

11.025 5.6448 22.5792

Note: Be careful in case of direct connection of PUP and WSEN. Do not set the PUP voltage to high, otherwise PUP and WSEN goes down and it is n ot p os si ble to set the old PUP level by I

DCCF $8e

voltage monitor

VSS AVSS

C command.

AVDDVDD

DCSG DCSO

DCEN

PUP

WSEN

VSENSE

−

Fig. 2–2: Voltage monitor connections, DC/DC converter not used

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PRELIMINARY DATA SHEET MAS 3507D

2.6.2. DC/DC Converter

The DC/DC converter of the MAS 3507D is used to generate a fixed power supply voltage even if the chip set is powered by battery cells in portable applications. The DC/DC converter is designed for the application of 2 batteries or NiCd cells as shown in Fig. 2–3 which shows the standard application circuit. The DC/DC converter is switched on by activating the DCEN pin. Its output power is sufficient for other ICs as well.

Note: Connecting DCEN directly to VDD leads to unexpected states.

The PUP signal can be read out by the system controller. The controller again may be connected with the corresponding in put line WSEN of the MAS 3507D to activate MPEG decoding. It is important that the WSEN signal must not be activated before the PUP signal is high. In applications without controller it is recommended to connect PUP with WSEN. The PUP signal thresholds are listed in Table 3–7.

Note: Be careful in ca se of direct connection of PUP and WSEN. Do not set the PUP voltage to high, othe rwise PUP and WSEN goes down and it is n ot p os sible to set the old PUP level by I

C command.

is important for efficiency. The primary criterion for selecting the output filter capacitor is low equivalent series resis tance ( E SR), as the product of the indu ctor current variation and the ES R de termines the high -fre quency amplitude seen on the output voltage. The Schottky diode should have a low voltage drop U

for a

high overall efficiency of the DC/DC converter. The current rating of the d iode sho uld also be greater th an

2.5 times the DC output current. The VSENS pin is always connected to the output voltage at low ESR capacitance.

2.6.3. St and-by Functions

Both the digital part of the MAS 3507D and the DC/DC converter have their own power-up pins (WSEN, DCEN). Thus, the DC/DC converter can rem ain active to supply other parts of the application even if the audio decoding part of the MAS 3507D is not being used. The WSEN power-up pin of the digital par t may be handled by the controller.

Please pay attention to the fact, that I

C protocol is working only if the proc essor and its interfaces works (DCEN=1 & WSEN=1)

µH inductor is required for the application. The

A 22 import ant specification item is the inductor saturation current rating, which s hould be greater t han 2.5 times the DC load current. The DC resistance of the inductor

AVDDVDDCLKI 14.725 MHz

Start-up

oscillator

Frequency

divider

64...94

32...47

+32

0...15

DCCF

$8e

10 16

DC/DC

converter

voltage monitor

VSS AVSS

DCSO

DCSG

DCEN

PUP

WSEN

VSENSE

2.6.4. Start-up Sequence

The DC/DC converter is switched on by activating the DCEN pin. After PUP and WRDY are high set WSEN.

optional

filter

22 µH

out

330 µF Low ESR

330 µF

− +

−

≥1.6 V

10 k

10 nF

−

Ω

Fig. 2–3: DC/DC converter connections

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MAS 3507D PRELIMINARY DATA SHEET

2.7. Interfaces

The MAS 3507D uses an I input interface for MPEG bit stream, and a digital audio output interface for the decoded audio data (I

C control interface, a serial

S or similar). Additionally, a parallel I/O interface (PIO) may be used for monitoring and mode selection tasks. The PIO lines are defined by the internal firmware.

2.7.1. MPEG Bit Stream Interface

The MPEG bit stream input interface consists of the three pins: SIC, SII, and SID. For MPEG decoding operation, the SII pin must always be connected to VSS. The MPEG input signal format is shown in Fig. 2–4. The data values are latche d with the falling edge of the SIC signal.

The MPEG bit stream generated by an encoder is unformatted. It will be formatted (e.g. 8 bit or 16 bit) by storing at a media (PC, EEPROM). The serial data required from the MPEG bit stream in terface must be in the same bit order as produced by the encoder.

2.7.2. Audio Output Interface

The audio output interface of the MAS 3507D is a standard I

S interface. It is possible to choose between two standard interfaces (16 bit with del ay or 32 bit with inverted SOI) via start-up configuration. These setup modes meet the performance of the most common DACs. It is also possible to select other interface modes via I

2.7.2.1. Mode 1:16 Bits/Sample (I

C commands (see Section 2.7.2.3.).

S Compatible

Data Format)

A schematic timing di agram of t he S DO interface in 16 bit/sample mode is shown in Fig. 2–5.

2.7.2.2. Mode 2:32 Bit/Sample (Inverted SOI)

If the serial output generates 32 bits per audio sample, only the first 20 bits wi ll carr y valid audi o data. The 12 trailing bits are set to zero by default (see Fig. 2–6).

SIC

data valid

latch data at falling edge of clock

SII

SID

Fig. 2–4: Schematic timing of the SDI (MPEG) input

SOC

SOD

13 12 11 1098

76543210

1514131211109876543210

SOI

left 16-bit audio sample

right 16-bit audio sample

Fig. 2–5: Schematic timing of the SDO interface in 16 bit/sample mode

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PRELIMINARY DATA SHEET MAS 3507D

SOC

SOD

SOI

31302928272625 76543210

left 32-bit audio sample

...

302928272625...76543210

right 32-bit audio sample

Fig. 2–6: Schematic timing of the SDO interface in 32 bit/sample mode

2.7.2.3. Other Output Modes

The interface is also config urable by software to work in different modes. It is possible to choose:

– 16 or 32 bit/sample modes, – inverted or not inverted word strobe (SOI), – no delay or delay of data related to word strobe.

For further details see Section 3.5.2.2.

2.7.3. Start-up Configuration

Basic operation of the MAS 3507D is possible without controller interaction. Configuration and the most importan t status information ar e available by the PIO interface. The start-up configuration is selected according to the levels of several PIO pins. The levels should be set via hig h impedance resi stors (for example 10 k

Ω) to VSS or VDD and will be copied into the

StartupCo nfig register directly after power up / reset. After start-up, the PIO will be reconfigured as output.

To enable greater flexibility, it is possible to configure the MAS 3507D without using the PIO pins or to reconfigure the IC after star t-up. The procedure for this is to send two I

C commands to the MAS 3507D:

– Writing the StartupConfig register (see Section 3.4.

on page 18)

– Execute a ‘run $0fcd’ command (see Section

3.3.1.).

2.7.4. Parallel Input Output Interface (PIO)

The parallel interface of the MAS 3507D consists of the lines PI0...PI4, PI8, PI12...PI19, and several con- trol lines. During start-up, the PIO will read the start-up configuration. This is to defi ne the environment for the MAS 3507D. The following pins must be connected via resistors to VSS or VDD:

Ta ble 2–3: Start-up configuration

PIO

“0” “1”

PI8 divide CLKO by 1,

2, or 4 (according to MPEG 1, 2, or

CLKO fixed at

24.576 or 22.5792 MHz

2.5)

PI4 14.725 MHz input

clock

14.592 MHz input

clock PI3 Enable layer 3 Disable layer 3 PI2 Enable layer 2 Disable layer 2 PI1 SDO output: 32 bit SDO output: 16 bit PI0 input: Multimedia

mode (PLL off)

input: Broadcast

mode (PLL on)

1) Start-up setting can be overruled by I2C commands after reset.

The configuration will be active up to a reset. Then, the new configuration will be loaded again via PIO.

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MAS 3507D PRELIMINARY DATA SHEET

After having read the start-up configuration, the PIO will be switched to ‘ tional PIO con trol lines (PR, PCS

µP-mode’. In µP-mode, the addi-

) are evaluated. The

MPEG decoder firmware expects PR = ‘1’ and the

PCS

= ‘0’. Then, all P IO interface lines ar e configured

as output and display some status information of the MPEG decoder. The PIO lines can be read by an external controller or di rectly used by dedicated hardware blocks (e.g. for sample rate indication or display units). The inter nal MPEG decoder firmware attaches specific functions to the following pins:

Table 2–4: PIO output signals during MPEG decoding

PIO

Name Comment

PI19 Demand PIN

PI18, PI17

%0 %1

MPEG INDEX %00

%01 %10 %11

no input data exp. input data request

MPEG 2.5 reserved MPEG 2 MPEG 1

The MPEG-FRAME-SYNC signal is set to ‘1’ after the internal decod ing for the MPEG header has been finished for one frame. The rising edge of this signal could be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 35 07D has recognized the corresponding read com mand (‘read control interface data’ (see Section 3.3.2. on page 15), the MPEG-FRAME-SYNC is reset. This behavior reduces the possibility of missing the MPEG-FRAME-SYNC active state.

=24 ... 72ms

frame

read

MPEG-FRAME-SYNC Fig. 2–7: Schematic timing of MPEG-FRAME-Sync

The time t

depends on the response time of the

read

controller. This time must not exceed 1/2 of the MPEGframe length t

. The MPEG frame lengths are given

frame

in Table 2–5.

PI13, PI12

MPEG Layer ID %00

%01 %10 %11

PI8 MPEG CRC-ERROR

%0 %1

PI4 MPEG-FRAME-

SYNC see following text

PI3, PI2

Sampling frequency %00

%01 %10 %11

PI1, PI0

Deemphasis %00

%01 %10 %11

reserved Layer 3 Layer 2 Layer 1

no error CRC-error, MPEG decoding not successful

in kHz

44.1 / 22.1 / 11.0 48 / 24 / 12 32 / 16 / 8 reserved

none 50/15

µs

reserved CCITT J.17

Table 2–5: Frame length in MPEG layer 2 / 3

fs in kHz

Frame Length Layer 2

Frame Length Layer 3

48 24 ms 24 ms

44.1 26.12 ms 26.12 ms 32 36 ms 36 ms 24 48 ms 24 ms

22.05 52.24 ms 26.12 ms 16 72 ms 32 ms 12 not available 48 ms

11.025 not available 52.24 ms 8 not available 72 ms

Layer 1 bit streams will not be decoded

Sampling frequency also defined by MPEG index

(see Table 3–11 for additional information)

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PRELIMINARY DATA SHEET MAS 3507D

3. Control Interfaces

C Bus Interface

3.1. I

3.1.1. General

Communication between the MAS 3507D and the external controller is done via I

C bus. An I2C slave interface with a minimum transfer data word l ength of 16 bits is provided. The interface uses one level of subaddresses. The device addresses are shown in Table 3–1. I

C clock synchronization is used to slow

down the interface if required.

Table 3–1: I

C device address

A7 A6 A5 A4 A3 A2 A1 W/R 00111010/1

The I

C data and control regi sters of the MAS 3507D have 16-bit data size. They are acce ssed by reading/ writing two 8-bit data words.

Fig. 3–1 shows I

C bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set.

3.1.2. Su baddresses

The I

C control interface of the MAS 3507D is designed as a slave interface. A system controll er may send configuration comma nds or read status information via the I

C interface. The I2C interface has 3 sub-

addresses allocated.

Ta ble 3–2: Subaddresses

Sub-

Comment

addresses

$68 /write controller writes to MAS 3507D data

$69 /read controller reads from MAS 3507D

data register

$6A/ write controller writes to MAS 3507D con-

trol regist er

The address ($6a) is use d for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 3507D.

Please pay attention to the fact that I

C protocol works

only if the processor is working (DCEN=1 & WSEN=1)

Example:

S dev_write ($3A) Ack

Example:

S dev_write ($3A)

SDA

SCL

C write access

data_write ($68)

C read access

data_read ($69) Ack

Ack

1 0

Ack Ack

high byte data

dev_read ($3b)

SAckhigh byte data

low byte data PAck

low byte data

W R

Ack Nak S P

Start

Stop

Ack Nak P

Fig. 3–1: I

C bus protocol for the MAS 3507D

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MAS 3507D PRELIMINARY DATA SHEET

3.1.3. I2C Registers

3.1.3.1. I

The I

C Control Register

C control register is a write-only register and its

main purpose is the software reset of the MAS 3507D.

Table 3–3: Control register bit assignm ent

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

xxxxxxxR0000T3T2T1T0

x = don’t care, R = reset, T3...T0 = task selection

The software reset is done by wr iting a 16-bit word to the MAS 3507D with ‘bi t 8’ set. The 4 lea st significant bits are reser ved for task selecti on. The task selec tion is only useful in combina tion with download software. In standard MPEG decoding, these bits must always be set to ‘0’.

3.1.3.2. I

The I

C Data Register

C data register is readable (subaddress data_read), wr itable (sub address d ata_ write ), a nd has a length of 16 bits. The data transfer is done with the most significant bit (m) first.

transmission. The data information is performed by sending a ‘read memory’ command to the MAS 3507D and by reading the memory block that temporarily contains the required information. The synchronization between the controller and the MAS 3507D is done via a MPEG-FRAME-SYNC signal or by monitoring the MPEGFrameCount register (at the cost of a higher work load for the controller).

The MAS 3507D firmware scans the I

C interface periodically and checks for pending or new commands. However, due to some time critical firmware parts, a certain latency time for the response has to be expected. The theoretical worst case response time does not exceed 4 ms. However, the typical response time is less than 0.5 ms. Table3–5 shows the basic controller commands that are available by the MAS 3507D

3.2.1. The Internal Fixed Point Number Format

Internal register or memory values can easily be accessed via the I

C interface. In this document, two number representations ar e u se d: th e fi xed point notation ‘v’ and the 2’s complement number notation ‘r’.

The conversion between the two forms of n otation is easily done (see the following equations).

r = v*524288.0+0.5; ( v = r/524288.0; (

−1.0 ≤ v < 1.0) (EQ 1)

−524288 < r < 524287) (EQ 2)

Table 3–4: Data register bit assignment

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

m l

3.2. Command Structure

The I

C control of the MAS 3507D is done completely

via the I

C data register by using a special command syntax. The commands are executed by the MAS 3507D during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. These I

C commands allow the controller to access internal states, RAM contents, internal hardware control registers, and even a download of an alternative software module. The command structure allows sophisticated control of the MAS 3507D. The registers of the MAS 3507D are either general purpose, e.g. for program flow control, or specialized registers that directly affect hardware blocks. The unrestricted access to these registers allows the system controller to overrule the firmware configuration of the serial interfaces or the default input line selection.

The control interface is also used for low bit rate data transmission, e.g. MPEG-embedded ancillary data

3.2.2. Conventions for the Command Description

The description of the various controller commands uses the following formalism:

– A data value is split into 4-bit nibbles which are num-

bered beginning with 0 for the least significant nibble.

– Data values in nibbles are always shown in hexa-

decimal notation indicated by a preceding $.

– A hexadecimal 20-b it number d is written, e.g. as

d = $17C63, its five nibbles are d0 = $3, d1 = $6, d2 = $C, d3 = $7, and d4 = $1.

– Abbreviations used in the following descriptions:

a address d data value n count value o offset value r register number x don’t care

– Variables used in the following descriptions:

dev_write $3a dev_read $3b data_write $68 data_read $69 control $6a

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PRELIMINARY DATA SHEET MAS 3507D

Table 3–5: Basic controller commands

Code Command Comment

$0 $1

$3 read Control Informa-

run Start execution of an internal program. (Run 0 means freeze operating sys-

tem.) fast read of a block of information organized in 16-bit words (see Section

tion and Ancillary Data

3.5.1. on page 22)

$9 write register An internal register of the MAS 3507D can be written directly to by the con-

troller.

$A $B

write to memory A block of the DSP memory can be written to by the controller. This feature

may be used to download alternate programs. $D read register The controller can read an internal register of the MAS 3507D. $E

read memory A block of the DSP memory can be read by the controller.

3.3. Detailed MAS 3507D Command Syntax

3.3.1. Run

dev_write

data_write

a3,a2

a1,a0

A P

3.3.2. Read Control Interface Data

1) send command

dev_write

data_write

$3, x2

x1,x0

A P

The ‘run’ command causes the start of a program part at address a = (a3,a2,a1,a0). The nibble a3 is restricted to $0 or $1 which also acts as command selector. Run with address a=$0 wil l suspend nor mal MPEG decoding and only I

C commands are evaluated. This freezin g will be required if alter native software is downloaded into the internal RAM of the MAS 3507D. Detailed information about downloading is provided in combination with a MAS 3507D software development package or together with MAS 3507D software modules available from Micronas.

If the address $1400

≤ a < $1800, the MAS 3507D

continues execution of the program with the downloaded code. For detailed informatio n, please refer to the MASC software development kit. This is for starting the downloaded program code.

Example 1: ‘run’ at address $fcd (override start-up configuration) has the following I

<$3a><$68><$0f><$cd>

C protoco l:

Example 2: ‘run’ at address $fcb (activate PLLOffset and OutputConfig after change by write command) has the following I

C protocol:

2) get ancillary data values

dev_write

x2...x0: combined count, offset value d3...d0: 16-bit data values

data_read

(ancillary word 0)

A S

dev_read

d3, d2

....repeat for n data values....

d3, d2

d1,d0

Nak

An internal m emor y array keeps the status inform ation of the MAS 3507D (see Table 3–9). The ‘read control interface data’ command can be us ed for quick access to this memor y array. A suc cessive range of memory locations may be read by passing a 6-bit offset value “o” and a 6-bit count value “n” as parameter.

Both values are combined in a 12-bit = 4 nibble field x2, x1, x0. If, for example, 4 words (n = 4) star tin g wi th one word offset (o = 2), i.e. the MPEGStatus2, the CRCErrorCount, and Num berOfAncillaryBits are re ad from the control memory array , the 3 nibbles x2, x1 and x0 are evaluated as shown in the following table.

11 10 9 8 7 6 5 4 3 2 1 0

6-bit values offset: 2 number of words: 3

<$3a><$68><$0f><$cb>

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MAS 3507D PRELIMINARY DATA SHEET

dev_write

data_write

$9, r1

r0, d0

d4, d3

d2, d1

dev_write

data_write $A, $0

$0,$0

n3,n2

n1,n0

a3,a2 a1,a0

n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value

n3,n2

d1,d0

$0,$0 $0,d4

d3,d2

....repeat for n data values....

n3,n2

d1,d0

$0,$0 $0,d4

d3,d2

A P

11 10 9 8 7 6 5 4 3 2 1 0

bit 000010000011

nibble 0 8 3

The complete I2C protocol reads as:

<$3a><$68><$30><$83> <$3a><$69><$3b><receive 3 16-bit data values>

The ‘read control interface data’ comm and resets the MPEG-FRAME-SYNC at PI4 pin (see Section 2.7.4. on page 11).

3.3.3. Write Register

The controller writes the 20-bit value (d = d4,d3,d2,d1,d0) into the MAS 3507D register (r = r1,r0). In contrast to memory cells, registers are always addressed individually, and they may also interact with built-in hardware blocks. A list of useful registers is given in the next section.

Example: reconfiguration of the output to 16 bit without delay has the following I

C protocol:

<$3a><$68><$a0><$00> (write D0 memory) <$00><$01> (1 word to write) <$03><$2f> (start address) <$00><$10> (value = $00010) <$00><$00> <$3a><$68><$0f><$cd> (run command)

3.3.5. Write D1 Memory

dev_write

n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value

data_write

$B, $0

n3,n2

a3,a2 a1,a0

n3,n2

d3,d2

$0,$0 $0,d4

....repeat for n data values....

n3,n2

d3,d2

$0,$0 $0,d4

$0,$0

n1,n0

A A

d1,d0

A A

d1,d0

A A

A P

For further details, see ‘write D0 memory’ command.

Example: Muting can be realized by writing the value 1

3.3.6. Read Register

into the register with the number $aa:

<$3a><$68><$9a><$a1><$00><$00>

3.3.4. Write D0 Memory

1) send command

dev_write

2) get register value

dev_write

r1, r0: register r d3...d0: data value in r X: don’t care

d3, d2

A A

data_write

data_read

d1,d0

A S

$D, r1

dev_read

X,X

r0,$0

The MAS 3507D has an address spa ce of 256 registers. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others do control the interna l program flow. In the next section, those registers that are of any interest with respect to the MPEG de coding are described in detail.

Example:

The MAS 3507D has 2 memory areas of 2048 words each called D0 and D1 memory. For both memory areas, read and write commands are provided.

16 Micronas

Read the content of the PIO data register ($c8):

<$3a><$68><$dc><$80> <$3a><$69><$3b> now read: <d3,d2><d1,d0><x,x><x,d4>

X, d4

Nak

PRELIMINARY DATA SHEET MAS 3507D

3.3.7. Read D0 Memory

1) send command

dev_write

2) get memory value

dev_write

n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value

data_write

data_read

d3, d2

A A

d3, d2

$E, $0

n3,n2 n1,n0

a3,a2

dev_read

$0,$0

A S

d1,d0

....repeat for n data values....

d1,d0

$0,$0

A A

a1,a0

A P

$0, d4

A P

The ‘read D0 memory’ command is provided to get information from memory cells of the MAS 3507D. It gives the controlle r access to all memor y cells of the internal D0 memory. Direct access to memory cells is an advanced feature of the DSP. It is intended for users of the MASC software development kit.

3.3.9. Default Read

dev_write

data_read

A S

device_read

d3,d2

d1,d0

Nak

The ‘default read’ command immediately returns the content of the MPEGFrameCount (D0:$300) of the MAS 3507D in the variable (d = d3,d2,d1,d0). The ‘default read’ command is the fastest way to get information from the MAS 3507D. Executing the ‘default read’ command in a po ll ing loop can be used to d ete ct the availability of new ancillary data.

3.3.8. Read D1 Memory

1) send command

dev_write

2) get memory value

dev_write

n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value

data_write

data_read

d3, d2

A A

d3, d2

$F, $0

n3,n2 n1,n0

a3,a2

dev_read

$0,$0

A S

d1,d0

....repeat for n data values....

d1,d0

$0,$0

A A

a1,a0

A P

$0, d4

A P

The ‘read D1 memory’ command is provided to get information from memory cells of the MAS 3507D. It gives the controlle r access to all memor y cells of the internal D1 memory.

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MAS 3507D PRELIMINARY DATA SHEET

3.4. Register Table

In Table 3–6, the internal reg isters that are useful for controlling the MAS 3507D are listed. Th ey are acce ssible by ‘register read/write’ I tion 3.3. on page 15).

Table 3–6: Command Register Table

Address R/W Name Comment Default

$8e w DCCF Set DC/DC converter mode

$aa r/w Mute / Bypass

$c8 r PIOData Read back the PIO pin levels. The PI0 pin corresponds to bit

$e6 r/w StartupConfig Shadows the start-up configuration set via PIO pins or I

C commands (see Sec-

Tone Control

(see Table 3–7 on page 19) Forces a mute of the digital output

bypass Bass / Treble / Volume matrix

0 in the PIOData register. This register can be used to detect the actual state of the PIO pins, regardless of the PIO configuration.

command (valid are bits 8, 4...0 as described in Table 2–3.

Important note! Writing into undocum ented registers or read-only registers is always possible, but it is highly recommended not to do so. It may damage the function of the firmware and may even lead to a comple te system crash of the dec oder operatio n which can o nly be restored by a reset.

$08000

$e7 r/w KPrescale responsible for prescale of the tone filter (prevent overflows)

(see Section 3.4.3. on page 20)

$6b r/w KBass responsible for increase / decrease of low frequencies

(see Section 3.4.3. on page 20)

$6f r/w KTreble responsible for increase / decrease of high frequencies

(see Section 3.4.3. on page 20)

3.4.1. DC/DC Converter

Address R/W Name Function Default

$8e w DCCF Controls DC/DC operation $08000

The DCCF Register is controls both the voltage monitor and DC/DC converter. Between output voltage of the DC/DC converter and the voltage monitor thresho ld an offset exists which is shown in the following table. Please pay attention to the fact, that I for the DCCF register will remain active if the DCEN and WSEN lines are deasserted.

C protocol is working only if the processor works (DCEN=1 & WSEN=1).However, the setting

$80000

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PRELIMINARY DATA SHEET MAS 3507D

Table 3–7: Bit Assignment of the DCCF register

Bits Signal Function

16...14 PUPLIMIT (3 bits)

0 1 2 (reset) 3 4 5 6 7

13...10 DCFR (4 bits)

0 (reset) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DC/DC converter output

Voltage monitor (PUP signal becomes inactive when output below)

2.8 V

2.9 V

3.0 V

3.1 V

3.2 V

3.3 V

3.4 V

3.5 V

2.59 V

2.69 V

2.78 V

2.85 V

2.95 V

3.03 V

3.13 V

3.20 V

Sets the clock frequency of the DC/DC converter to:

230 kHz 223 kHz 216 kHz 210 kHz 204 kHz 199 kHz 194 kHz 188 kHz 184 kHz 179 kHz 175 kHz 171 kHz 167 kHz 163 kHz 160 kHz 156 kHz

The DC/DC converter may generate interference noise that could be unacceptable for some applications. Thus the oscillator frequency may be adjusted in 16 steps in order to allow the sys tem con tr oll er to se lec t a base frequency that does not interfere with an other application.

The CLKI input provides t he bas e clock f

for the fre-

clki

quency divider whose output is made symmetrical with an additional divider by two. The divider quotient is determined by the con tent of the DCCF register. This register may have values between 0 and 15 generating a DC/DC converter clock frequency f

---------------------------= 232n+()⋅

lki

∈

n 015{, }

between:

(EQ 3)

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MAS 3507D PRELIMINARY DATA SHEET

3.4.2. Muting / Bypass Tone Control

Address R/W Name Comment Default

$aa r/w Mute / Bypass

Tone Control 0

1 2

To enable fast and simple mute functionality , set bit 0 in register $aa to ‘1’. Writing a ‘0’ deactivates mute.

It is possible to bypass the complete bass / treble / volume control by setting bit 1 in reg ister $aa (w r ite a ‘2’). Resetting bit 1 to ‘0’ enables tone control again.

3.4.3. Bass and Treble Control

Address R/W Name Comment Default

$e7 r/w KPrescale responsible for prescale of the tone filter (prevent overflows)

$6b r/w KBass responsible for increase / decrease of low frequencies

Forces a mute of the digital output

no mute, Tone control active mute output, but continue decoding bypass Bass / Treble / Volume matrix

(see Section 2.4.3. on page 7)

$80000

$6f r/w KTreble responsible for increase / decrease of high frequencies

(see Section 2.4.3. on page 7)

Tone control is implemented in the MAS 3507D. It allows the control of b ass and treble in a range u p to ±15 dB, as Table 3–8 shows. To prevent overflow or clipping effects, the prescaler is built-in. The pre scaler decreases the overall gain of the tone filter, so the full range up to +15 dB is usable without clipping.

To se lect a specia l setting, max. 3 co efficients have to be written into registers of the MAS 3507D. This has to be done via the ‘write register’ I tion 3.3.3.).

C command (see Sec-

20 Micronas

PRELIMINARY DATA SHEET MAS 3507D

Table 3–8: Tone control registers

Boost in dB Bass (Reg. $6b) Treble (Reg. $6f) Prefactor (Reg $e7)

+15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1

0 0 0 $80000

−1

$61800 $5d400 $58800 $53800 $4e400 $48800 $42800 $3c000 $35800 $2e400 $27000 $1f800 $17c00 $10000 $800

$f7c00

$5f800 $58400 $51800 $49c00 $42c00 $3c000 $35400 $2ec00 $28400 $22000 $1c000 $16000 $10400 $ac00 $5400

$fac00

$e9400 $e6800 $e3400 $dfc00 $dc000 $d7800 $d25c0 $cd000 $c6c00 $bfc00 $b8000 $af400 $a5800 $9a400 $8e000

$80000

−2

−3

−4

−5

−6

−7

−8

−9

−10

−11

−12

−13

−14

−15

$efc00 $e8000 $e0400 $d8c00 $d1800 $ca400 $c3c00 $bd400 $b7400 $b1800 $ac400 $a7400 $a2800 $9e400

$f5c00 $f0c00 $ec000 $e7e00 $e2800 $de000 $d9800 $d5000 $d0400 $cbc00 $c6c00 $c1800 $bb400 $b2c00

$80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000

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MAS 3507D PRELIMINARY DATA SHEET

3.5. Memory Area

3.5.1. Status Memory

The memory cells given in the following table should be accessed by the ‘read control interface data’ I command (see Section 3.3.2. on page 15) because only the 16 LSBs of these memory blocks are used. The memory area table is a consecutive memory block in the D0 memor y that keeps all important status information that monitors the MPEG decoding process. The ‘read control interface data’ comm and resets the MPEG-FRAME-SYNC at PI4 as described in Section 2.7.4.

Table 3–9: Status Memory Area

Address Offset

D0:$300 0 r MPEGFrameCount counts the MPEG frames D0:$301 1 r MPEGStatus1 MPEG header / status information D0:$302 2 r MPEGStatus2 MPEG header D0:$303 3 r CRCErrorCount counts CRC errors during MPEG decoding D0:$304 4 r NumberOfAncillaryBits number of bits in ancillary data

R/W Name Function

D0:$305

... $321

Offset applies to the ‘read control interface data’ command

3.5.1.1. MPEG Frame Counter

Address Offset R/W Name Function

D0:$300 0 r MPEGFrameCount counts the MPEG frames

The counter will be incremented w ith each new frame that is decoded. With an invalid MPEG bit stream as its input (e.g. if an invalid header is detected), the

3.5.1.2. MPEG Status 1

Address Offset R/W Name Function

D0:$301 1 r MPEGStatus1 MPEG header / status information

5 r AncillaryData organized in words a 16 bit (MSB first)

MAS 3507D resets the MPEGFrameCount cell to ‘0’. The MPEGFrameCount is also retur n ed by the ‘default read’ command as described in Section 3.3.9.

The MPEGStatus1 contains the bits 15...11 of the MPEG header and so me s ta tus bi ts. It will b e s et e ac h frame, directly after the header has been decoded from the bit stream.

22 Micronas

PRELIMINARY DATA SHEET MAS 3507D

Table 3–10: MPEG Status 1

Bits Name/Value Comment

19, 15 %xxxx.x don’t care 14, 13 MPEG ID

%00 %01 %10 %11

12, 11 Layer

%00 %01 %10 %11

Bits 11, 12 of the MPEG-header MPEG 2.5

reserved MPEG 2 MPEG 1

Bits 13, 14 of the MPEG-header reserved

Layer 3 Layer 2 Layer 1

10 %1 not protected by CRC

9...2 private bits

1 %1 CRC Error 0 %1 invalid frame

3.5.1.3. MPEG Status 2

Address Offset R/W Name Function

D0:$302 2 r MPEGStatus2 MPEG header

The MPEGStatus2 co ntains the 16 LS Bs of the MP EG header. It will be set direc tly after synchr onizing to the bit stream.

Table 3–11: MPEG Status 2

Bits Value/Name Comment

19, 16 don’t care

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MAS 3507D PRELIMINARY DATA SHEET

Table 3–11: MPEG Status 2

Bits Value/Name Comment

15...12 Bit rate index MPEG 1

%0000 %0001 %0010 %0011 %0100 %0101 %0110 %0111 %1000 %1001 %1010 %1011 %1100 %1101 %1110 %1111

11, 10 Sampling frequency MPEG 1 MPEG 2 MPEG 2.5

%00 %01 %10 %11

9 Padding bit

(Layer 2) in kbit/s

free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden

44.1 kHz 48 kHz 32 kHz reserved

MPEG 1 (Layer 3) in kbit/s

free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden

22.05 kHz 24 kHz 16 kHz reserved

MPEG 2 in kbit/s (Layer 2 & 3) MPEG 2.5 in kbit/s

free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden

11.025 kHz 12 kHz 8kHz reserved

8Private bit 7, 6 Mode

%00 %01 %10 %11

5, 4 Mode extension

(if joint stereo only) %00

%01 %10

%11 3 %0 / 1 copyright not protected / copyright protected 2 %0 / 1 copy / original 1, 0 Emphasis indicates the type of emphasis

%00

%01

%10

%11

stereo joint_stereo (intensity stereo / ms_stereo) dual channel single_channel

intensity stereo ms_stereo

off on off on

none 50/15 µs reserved CCITT J.17

off off on on

24 Micronas

+ 55 hidden pages

Micronas Intermetall MAS3507D Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1. Features

1.2. Application Overview

1.2.1. Multimedia Mode

1.2.2. Broadcast Mode

2.1. DSP Core

2.2. Firmware (Internal Program ROM)

2.3. Program Download Feature

2.4. Baseband Processing

2.4.1. Volume Control / Channel Mixer

2.4.2. Mute / Bypass Tone Control

2.4.3. Bass / Treble Control

2.5. Clock Management

2.6. Power Supply Concept

2.6.1. Voltage Monitor

2.6.2. DC/DC Converter

2.6.3. St and-by Functions

2.6.4. Start-up Sequence

2.7. Interfaces

2.7.1. MPEG Bit Stream Interface

2.7.2. Audio Output Interface

2.7.2.2. Mode 2:32 Bit/Sample (Inverted SOI)

2.7.2.3. Other Output Modes

2.7.3. Start-up Configuration

2.7.4. Parallel Input Output Interface (PIO)

3. Control Interfaces

3.1.1. General

3.1.2. Su baddresses

3.1.3. I2C Registers

3.2.1. The Internal Fixed Point Number Format

3.2. Command Structure

3.2.2. Conventions for the Command Description

3.3.1. Run

3.3.2. Read Control Interface Data

3.3.3. Write Register

3.3.5. Write D1 Memory

3.3.6. Read Register

3.3.4. Write D0 Memory

3.3.7. Read D0 Memory

3.3.9. Default Read

3.3.8. Read D1 Memory

3.4. Register Table

3.4.1. DC/DC Converter

3.4.2. Muting / Bypass Tone Control

3.4.3. Bass and Treble Control

3.5. Memory Area

3.5.1. Status Memory

3.5.1.1. MPEG Frame Counter

3.5.1.2. MPEG Status 1

3.5.1.3. MPEG Status 2