Micronas Intermetall DAC3550A Datasheet

DAC 3550A Stereo Audio DAC

6251-109-4E

Edition July 23, 1999 6251-467-1DS

MICRONASMICRONASMICRONASMICRONAS

MICRONAS

DAC 3550A

Contents

Page Section Title

3 1. Introduction

3 1.1. Main Features

5 2. Functional Description

52.1.I 6 2.2. Interpolation Filter 6 2.3. Variable Sample and Hold 6 2.4. 3rd-order Noise Shaper and Multibit DAC 6 2.5. Analog Low-pass 6 2.6. Input Select and Mixing Matrix 6 2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out 7 2.8. Analog Volume 7 2.9. Headphone Amplifier 8 2.10. Clock System 8 2.10.1. Standard Mode 8 2.10.2. MPEG Mode

92.11.I 9 2.12. Registers 9 2.13. Chip Select 9 2.14. Reduced Feature Mode

SInterface

C Bus Interface

10 3. Specifications

10 3.1. Outline Dimensions 10 3.2. Pin Connections and Short Descriptions 12 3.3. Pin Descriptions 12 3.3.1. Power Supply Pins 12 3.3.2. Analog Audio Pins 12 3.3.3. Oscillator and Clock Pins 13 3.3.4. Other Pins 13 3.4. Pin Configuration 14 3.5. Pin Circuits 15 3.6. Control Registers 17 3.7. Electrical Characteristics 17 3.7.1. Absolute Maximum Ratings 18 3.7.2. Recommended Operating Conditions 20 3.7.3. Characteristics

25 4. Applications

25 4.1. Line Output Details 25 4.2. Recommended Low-Pass Filters for Analog Outputs 26 4.3. Recommendations for Filters and Deemphasis 26 4.4. Recommendations for MegaBass Filter without Deemphasis plus 1st-order low-pass 27 4.5. Power-up/down Sequence 27 4.5.1. Power-up Sequence 27 4.5.2. Power-down Sequence 28 4.6. Typical Applications

32 5. Data Sheet History

2 Micronas

DAC 3550A

Stereo Audio DAC

1. Introduction

The DAC 3550A is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas’ unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio has been achieved. The DAC 3550A is controlled via I

Digital audio input data is received by a versatile I

C bus.

interface. The analog back-end consists of internal analog filters and op amps for cost-effective additional external sound processing. The DAC 3550A provides line-out, headphone/speaker amplifiers, and volume control. Moreover, mixing additional analog audio sources to the D/A-converted signal is supported.

The DAC 3550A is designed for all kinds of applications in the audio and multimedia field, such as: MPEG players, CD players, DVD players, CD-ROM players, etc. The DAC 3550A ideally complements the MPEG 1/2 layer 2/3 audio decoder MAS 3507D.

No crystal required for standard applications with sample rates from 32 to 48 kHz. Crystal required

only for automatic sample rate detection below 32 kHz, MPEG mode (refer to Section 2.10), and use of clock output CLKOUT.

1.1. Main Features

– no master main input clock required – integrated stereo headphone amplifier and mono

speaker amplifier

–SNR of 103dBA

C bus, I2S bus

–I – internal clock oscillator – full-feature mode by I

C control (three selectable

subaddresses)

– reduced feature mode for non-I

C applications – continuous sample rates from 8 kHz to 50 kHz – analog deemphasis for 44.1 kHz – analog volume and balance: +18…

−75 dB and mute

– oversampling and multibit noise-shaping technique – THD better than 0.01 % – two additional analog stereo inputs (AUX) with

source selection and mixing – supply range: 2.7 V…5.5 V – low-power mode – additional line-out – on-chip op amps for cost-effective external analog

sound processing

WSI

CLI

DRI

I2S

Interpolation Filter

Fig. 1–1: Block diagram of the DAC 3550A

demand signal

Host

(PC, Controller)

ROM, CD-ROM,

RAM, Flash Mem. ..

MPEG clock

MPEG bit stream

3507D

MAS

CLKOUT

DAC

I2S

Analog Inputs

DAC

3550A

14.725 MHz

Input Select and Mixing

line out

Volu me and Headphone Amplifier

OUTL

OUTR

Fig. 1–2: Typical application: MPEG Layer 3 Player

Micronas 3

DAC 3550A

CLI DAI WSI

23 24 25

I2S

Digital Supply

Vdd

Vss

CLKOUT

XTO

XTI

AUX2L

AUX1L

Sample Rate

Detection

Osc.

PLL

Interpolation Filter

Variable S & H

3rd-order Noise Shaper

Multibit DAC

Analog Low-pass Filter

Input Select

Switch Matrix

Analog Supply

I2C

Control

AVDD0 AVDD1

AVS S0

AVS S1 VREF

AGNDC

SDA

SCL

TESTEN

PORQ

DEECTRL

MCS1

MCS2

AUX1R

AUX2R

FOPL

FINL

DEEML

FOUTL

Fig. 1–3: Block diagram of the DAC 3550A

Postfilter Op Amps

Deemphasis Op Amps

Line-Out

Analog Volume

Headphone Amplifier

OUTROUTL

42 41

DEEMR

FOPR FOUTR

FINR

4 Micronas

DAC 3550A

2. Functional Description

S Interface

2.1. I

The I

S interface is the digital audio interface between the DAC 3550A and external digital audio sources such as CD/DAT players, MPEG decoders etc. It covers most of the I

S-compatible formats.

All modes have two common features:

1. The MSB is left justified to an I

S frame identifica-

tion (WSI) transition.

2. Data is valid on the rising edge of the bit clock CLI.

16-bit mode

In this case, the bit clock is 32

× fs

. Maximum word

audio

length is 16 bit. 32-bit mode

In this case, the bit clock is 64

× fs

. Maximum word

audio

length is 32 bit.

Automatic Detection

C control is required to switch between 16- and

No I 32-bit mode. It is recommended to switch the DAC 3550A into mute position during changing between 16- and 32-bit mode.

For high-quality audio, it is recommended to use the 32-bit mode of the I

S interface to make use of the full

dynamic range (if more than 16 bits are available).

Left-Right Selection

Standard I starting with left channel and low-state of WSI. However, I

Delay Bit

Standard I

S format defines an audio frame always

C control allows changing the polarity of WSI.

S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched off and on by I

Ccontrol.

CLI

DAI

WSI

Fig. 2–1: I

CLI

DAI

13 12 11 1098

programmable delay bit

left 16-bit audio sample

S 16-bit mode (LR_SEL=0)

29 28 27 26 25 24

76543210

1514131211109876543210

right 16-bit audio sample

29 28 27 26 25 24

76543210

WSI

Fig. 2–2: I

programmable delay bit

left 32-bit audio sample

S 32-bit mode (LR_SEL=0) Note: Volume mute should be applied before changing

right 32-bit audio sample

S mode in order to avoid audible clicks.

Micronas 5

DAC 3550A

f/Hz

2.2. Interpolation Filter

The interpolation filter increases the sampling rate by a factor of 8. The characteristic for fs

= 48 kHz is

audio

shown in Fig. 2–3.

-0.02

-0.04

-0.06

-0.08

-0.1

-0.12

-0.14 0 5000 10000 15000 20000

Fig. 2–3: 1

→8 Interpolation filter; frequency range:

0...22 kHz

2.3. Variable Sample and Hold

The advantage of this system is that even at low sample frequencies the out-of-band noise is not scaled down to audible frequencies.

2.4. 3rd-order Noise Shaper and Multibit DAC

The 3rd-order no ise shaper conver ts the oversampled audio signal into a 5-bit n oise-shap ing signal at a hig h sampling rate. This tec hnique results in extremely low quantization noise in the audio band.

2.6. Input Select and Mixing Matrix

This block is used to switch between or mix the au xiliary inputs and the signals coming from the DAC. A switch matrix allows to select b etween mono and stereo mode as shown in Fig. 2–4.

FOUTL

FOUTR

INSEL_AUX2 INSEL_AUX1 INSEL_DAC

AUX1L AUX1R AUX2L AUX2R

DAD DAI WSI

D/A

24.576 MHz

AUX_MS

Fig. 2–4: Switch matrix Mono mode is realized by adding left and right

channel.

2.7. Postfilter Op Amps, Deemphasis Op Amps, and Line-Out

This block contains the active components for the analog postfilters and the deemphasis network. The op amps and all I/O-pins for this block are shown in Fig. 2–5.

2.5. Analog Low-pass

The analog low-pass is a first or der filter with a cut -off frequency of approximately 1.4 MHz which removes the high-frequency components of the noise-shaping signal.

6 Micronas

optional line-out

DAC 3550A

AVSS

from switch matrix

AGNDC

µF/100 nF

3.3

VREF

FOUTL

FOUTR

For external components, see section “Applications”

DEEML

DEEMR

For external components see section “Applications”

FOPL

FOPR

FINL

FINR

Fig. 2–5: Postfilter op amps, deemphasis op amps, and line-out

2.8. Analog Volume

Ta ble 2–1: Volume Control

AVOL_R

AVOL_L

OUTL

150

47 Ω

OUTR

1.5 kΩ

Ω

1.5 k

Ω

to µC (HP-switch)

Speaker

32 Ω

16-32 Ω

Headphones

AVDD

IRPA

The analog volume control covers a range from +18 dB to

−75 dB. The lowest step is the mute posi-

tion. Step size is split into a 3-dB and a 1.5-dB range:

−75 dB...−54 dB: 3 dB step size

−54 dB...+18 dB: 1.5 dB step size

2.9. Headphone Amplifier

The headphone amplifier output is provided at the OUTL and OUTR pins connected either to stereo headphones or a mono loudspeaker. The stereo headphones require external 47-

Ω serial resistors in both

channels. If a loudspeaker is co nnected to these outputs, the power amplifier for the r ight ch annel must be switched to inverse polarity. In order to optimize the available power, the source of the two output amplifiers should be identical, i.e. a monaural signal.

Please note, that if a speaker is connec ted, it should strictly be connected as shown in Fig. 2–5. Never use a separate connector for the speaker, because electrostatic discharge could damage the output transistors.

Volume/dB AVOL

18.0 111000

16.5 110111

15.0 110110

13.5 110101

−−

0.0 101100 (default)

−1.5 101011

−−

−

54.0 001000

−57.0 000111

−−

−

75 000001

Mute 000000

Micronas 7

DAC 3550A

2.10. Clock System

The advantage of the DAC 3550A clock syste m is that no external master clock is neede d. Most DACs need 256

× fs

audio

, 384 × fs

, or at least an asynchro-

audio

nous clock. All internal clocks are generated by a PLL circuit,

which locks to the I

S bit clock (CLI). If no I2Sclock is present, the PLL runs free, and it is guaranteed that there is always a clock to keep the IC controllable by

The device can be set to two different modes:

– Standard mode – MPEG mode

In the standard mode, I

C subaddressing is possible (ADR0, ADR1, ADR2). MPEG mode always uses ADR3.

To select the modes, the MCS1/MCS2 pins must be set according to Table 2–2.

2.10.1. Standard Mode

– without I

In standard mode, sample rates from 48 kHz to 32 kHz are handled without I

C control automati-

cally . T he setting for this range is the default setting.

– with I

Sample rates below 32 kHz require an I

C control to set the PLL divider. This ensures that even at low sample rates, the DAC 3550A ru ns at a high clock rate. This avoids audible effects due to the noiseshaping technique of the DAC 3550A. Sample rate range is continuous fro m 8 to 50 kHz . The I

ting of low sample rates must follow according to Section 3.6. “Control Registers” on page 15.

An additional mode allows automatic sample rate detection. In this case, the clock oscillator is required and must run at frequencies between

13.3 MHz to 17 MHz. This mode, however, does not suppor t con t inuo us s am ple rates. Only the following sample rates are allowed:

8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz

C set-

Table 2–2: Operation Modes

MCS1 MCS2 Mode Sub-

address

00Stan-

dard

01Stan-

dard

10Stan-

dard

1 1 MPEG ADR3 Automatic

ADR0 32–48 kHz

ADR1 32–48 kHz

ADR2 32–48 kHz

Default Sample Rate

The sample rate detection allows a tolerance of

±200 ppm at WSI.

If the oscillator is not used for automatic sample rate detection, it can be used as a gene ral-purpose clock for the application. The freq uency range in this cas e is 10 MHz to 25 MHz.

2.10.2. MPEG Mode

This mode should be used in conjunction with MAS 350 7D in MPEG player applications. In this case a 14.725 M Hz signal is needed to provide a clock for the MAS 3507D and to allow an automatic sample rate detection in the DAC 3550A. All MPEG sample rates from 8 to 48 kHz can be detected. The internal processing and the DAC itself are automatically adjusted to keep constant performance throughout the entire range. I

C control for sample rate adjustment is not needed in this case. Regi ster SR_REG[0:2] is locked to SRC_A; see Section 3.6. “Control Registers” on page 15.

The MPEG sample rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,

24 kHz, 32 kHz, 44.1 kHz, 48 kHz As in standard mo de, the s amp le rat e d etec ti on allows

a tolerance of

±200 ppm at WSI.

Subaddressing is not possible in MPEG mode; this means, in multi-DAC systems, only one DAC 3550A can run in MPEG mode.

8 Micronas

DAC 3550A

2.11. I2C Bus Interface

The DAC 3550A is equipped with an I interface. The I addressing: The I

C bus interface uses one level of sub-

C bus address is used to address

Cbus slave

the IC. The subaddr ess allows chip select in multi DAC applications and selects one of the three internal registers. The registers are write-only. The I

Cbus chip

The registers of the DAC 3550A have 8- or 16-bit data size; 16-bit registers a re accessed by wr iting two 8-b it data words.

A6 A5 A4 A3 A2 A1 A0 R/W 10011010

address is given below. dev_write = $9A.

1 byte dataS dev_write Ack sub_adr Ack Ack P

8-bit I2C wr i te ac ce ss

S dev_write Ack sub_adr Ack 1 byte data Ack 1 byte data Ack P

SDA

SCL

W R Ack Nak S

= =

= = =

16-bit I2C write acces

0 1 0

1 Start

Stop

Fig. 2–6: I

C bus protocols for write operatio ns

2.12. Registers

In Section 3.6. “Control Registers” on p age 15, a de finition of the DAC 3550A control registe rs is shown. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in the table.

All registers are write-only. The register address is coded by 3 bits (RA1, RA0)

according to Table 2–3.

Table 2–3: I2C Register Address

RA1 RA0 Mnemonics

01SR_REG 10AVOL

2.13. Chip Select

Chip select all ows to c onn ec t u p to four DAC 3550A to

C control bus. The chip subaddresses are defined

an I by the MCS1/MCS2 (Mode and Chip Select) pins. Only in standard mode, chip select is possible. MPEG mode always uses chip subaddress 3.

2.14. Reduced Feature Mode

C control i s not us ed, the I C is in t he default mo de

If I (see Section 3.6. “Contro l Regi s ters ” on page 15) after start-up. Default Volume setting is 0 dB and digital audio input is set to standard I

S. Sample rates from 32 kHz to 48 kHz are suppo rted in this mode. App lica tions with no nee d for volume control or analog input could use this mode.

11GCFG

Ta ble 2–4: I2C Subaddress

The mnemonics used in the DAC 3550A demo software of Micronas are given in the last column.

7 6 5 4 3 2 1 0

MCS2 MCS1 RA1 RA0

Micronas 9

DAC 3550A

3. Specifications

3.1. Outline Dimensions

2333

0.17

10 x 0.8 = 8

0.8

13.2

1.75

1.3

13.2

0.375

2.0

2.15

0.1

Fig. 3–1:

44-Pin Plastic Metric Quad Flat Package

(PMQFP44)

Weight approximately 0.4 g Dimensions in mm

3.2. Pin Connections and Short Descriptions

NC = not connected, leave vacant LV = if not used, leave vacant VSS = if not used, connect to VSS

Pin No.

Pin Name Type Connection

(if not used)

0.8

10 x 0.8 = 8

D0024/2E

X = obligatory; connect as described in application

diagram

VDD = connect to VDD

Short Description

1 AGNDC IN/OUT X Analog reference Vol tage 2 AVSS1 IN X VSS 1 for audio back-end 3 AVSS0 IN X VSS 0 for audio output amplifiers 4 NC LV Not connected 5 OUTL OUT LV Audio Output: Headphone left or Speaker + 6 NC LV Not connected 7 OUTR OUT LV Audio Output: Headphone right or Speaker 8 NC LV Not connected 9 AVDD0 IN X VDD 0 for audio output amplifiers 10 AVDD1 IN X VDD 1 for audio back-end 11 NC LV Not connected 12 XTI IN X Quartz oscillator pin 1 13 XTO IN/OUT X Quartz oscillator pin 2 14 CLKOUT OUT LV Clock Output 15 SCL IN/OUT LV I

C clock

−

10 Micronas

DAC 3550A

Pin No.

Pin Name Type Connection

(if not used)

Short Description

16 SDA IN/OUT LV I2C data 17 VSS IN X Digital VSS 18 VDD IN X Digital VDD 19 MCS1 IN X I 20 MCS2 IN X I

C Chip Select 1

C Chip Select 2 21 DEECTRL IN VSS Deemphasis on/off Control 22 NC LV Not connected 23 CLI VSS I 24 DAI IN VSS I 25 WSI IN VSS I

S Bit Clock

S Data

S Frame Identification 26 PORQ IN VDD Power-On Reset, active-low 27 TESTEN IN X Test Enable 28 NC LV Not connected 29 AUX2L IN LV AUX2 left input for external analog signals (e.g. tape) 30 AUX2R IN LV AUX2 right input for external analog signals (e.g. tape) 31 AUX1L IN LV AUX1 left input for external analog signals (e.g. FM) 32 AUX1R IN LV AUX1 right input for external analog signals (e.g. FM) 33 NC LV Not connected 34 DEEML OUT LV Deemphasis Network Left 35 DEEMR OUT LV Deemphasis Network Right 36 NC LV Not connected 37 FOUTL OUT X Output to left external filter 38 FOPL IN/OUT X Filter op amp inverting input, left 39 FINL IN/OUT X Input for FOUTL or

filter op amp output (line out) 40 NC LV Not connected 41 FOUTR OUT X Output to right external filter 42 FOPR IN/OUT X Right Filter op amp inverting input 43 FINR IN/OUT X Input for FOUTR or

filter op amp output (line out) 44 VREF IN X Analog reference Ground

Micronas 11

+ 24 hidden pages

Micronas Intermetall DAC3550A Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1. Introduction

1.1. Main Features

2. Functional Description

2.2. Interpolation Filter

2.3. Variable Sample and Hold

2.4. 3rd-order Noise Shaper and Multibit DAC

2.6. Input Select and Mixing Matrix

2.5. Analog Low-pass

2.8. Analog Volume

2.9. Headphone Amplifier

2.10. Clock System

2.10.1. Standard Mode

2.10.2. MPEG Mode

2.12. Registers

2.13. Chip Select

2.14. Reduced Feature Mode

3. Specifications

3.1. Outline Dimensions

3.2. Pin Connections and Short Descriptions