Micronas VPX3226E, VPX3225E, VPX3224E Datasheet

VPX 3226E,
VPX 3225E,
VPX 3224E
Video Pixel Decoders

Edition Oct. 13, 1999
6251-483-1AI

ADVANCE INFORMATION

MICRONAS

MICRONAS

VPX 322xE

Contents

Page Section Title

6 1. Introduction

7 1.1. System Architecture

8 2. Functional Description

8 2.1. Analog Front-End
8 2.1.1. Input Selector
8 2.1.2. Clamping
8 2.1.3. Automatic Gain Control
8 2.1.4. Analog-to-Digital Converters
8 2.1.5. ADC Range
8 2.1.6. Digitally Controlled Clock Oscillator
10 2.2. Adaptive Comb Filter (VPX 3226E only)
11 2.3. Color Decoder
11 2.3.1. IF-Compensation
11 2.3.2. Demodulator
12 2.3.3. Chrominance Filter
12 2.3.4. Frequency Demodulator
12 2.3.5. Burst Detection / Saturation Control
12 2.3.6. Color Killer Operation
13 2.3.7. Automatic Standard Recognition
13 2.3.8. PAL Compensation/1H Comb Filter
14 2.3.9. Luminance Notch
14 2.4. Video Sync Processing
15 2.5. Macrovision Detection
15 2.6. Component Processing
16 2.6.1. Horizontal Resizer
17 2.6.2. Skew Correction
17 2.6.3. Peaking and Coring
17 2.6.4. YC
17 2.6.5. Video Adjustments
18 2.7. Video Output Interface
18 2.7.1. Output Formats
18 2.7.1.1. YC
19 2.7.1.2. Embedded Reference Headers/ITU-R656
21 2.7.1.3. Embedded Timing Codes (BStream)
21 2.7.2. Bus Shuffler
21 2.7.3. Output Multiplexer
21 2.7.4. Output Ports
22 2.8. Video Data Transfer
22 2.8.1. Single and Double Clock Mode
22 2.8.2. Clock Gating
23 2.8.3. Half Clock Mode
24 2.9. Video Reference Signals
24 2.9.1. HREF
24 2.9.2. VREF
24 2.9.3. Odd/Even Information (FIELD)
26 2.9.4. VACT

Color Space

bCr

4:2:2 with Separate Syncs/ITU-R601

bCr

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Contents, continued

Page Section Title

27 2.10. Operational Modes
27 2.10.1. Open Mode
27 2.10.2. Scan Mode
29 2.11. Windowing the Video Field
30 2.12. Temporal Decimation
31 2.13. Data Slicer
31 2.13.1. Slicer Features
31 2.13.2. Data Broadcast Systems
32 2.13.3. Slicer Functions
32 2.13.3.1. Input
32 2.13.3.2. Automatic Adaptation
32 2.13.3.3. Standard Selection
32 2.13.3.4. Output
34 2.14. VBI Data Acquisition
34 2.14.1. Raw VBI Data
35 2.14.2. Sliced VBI Data
36 2.15. Control Interface
36 2.15.1. Overview
36 2.15.2. I
36 2.15.3. Reset and I
36 2.15.4. Protocol Description
37 2.15.5. FP Control and Status Registers
38 2.16. Initialization of the VPX
38 2.16.1. Power-on-Reset
38 2.16.2. Software Reset
38 2.16.3. Low Power Mode
39 2.17. JTAG Boundary-Scan, Test Access Port (TAP)
39 2.17.1. General Description
39 2.17.2. TAP Architecture
39 2.17.2.1. TAP Controller
39 2.17.2.2. Instruction Register
39 2.17.2.3. Boundary Scan Register
40 2.17.2.4. Bypass Register
40 2.17.2.5. Device Identification Register
40 2.17.2.6. Master Mode Data Register
40 2.17.3. Exception to IEEE 1149.1
40 2.17.4. IEEE 1149.1–1990 Spec Adherence
40 2.17.4.1. Instruction Register
40 2.17.4.2. Public Instructions
41 2.17.4.3. Self-Test Operation
41 2.17.4.4. Test Data Registers
41 2.17.4.5. Boundary-Scan Register
41 2.17.4.6. Device Identification Register
41 2.17.4.7. Performance
45 2.18. Enable/Disable of Output Signals

2

C-Bus Interface

2

C Device Address Selection

VPX 322xE

3Micronas

VPX 322xE

Contents, continued

Page Section Title

46 3. Specifications

46 3.1. Outline Dimensions
47 3.2. Pin Connections and Short Descriptions
49 3.3. Pin Descriptions
50 3.4. Pin Configuration
51 3.5. Pin Circuits

53 4. Electrical Characteristics

53 4.1. Absolute Maximum Ratings
54 4.2. Recommended Operating Conditions
54 4.2.1. Recommended Analog Video Input Conditions
55 4.2.2. Recommended I
55 4.2.3. Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
56 4.2.4. Recommended Crystal Characteristics
57 4.3. Characteristics
57 4.3.1. Current Consumption
57 4.3.2. Characteristics, Reset
57 4.3.3. XTAL Input Characteristics
58 4.3.4. Characteristics, Analog Front-End and ADCs
59 4.3.5. Characteristics, Control Bus Interface
59 4.3.6. Characteristics, JTAG Interface (Test Access Port TAP)
60 4.3.7. Characteristics, Digital Inputs/Outputs
60 4.3.8. Clock Signals PIXCLK, LLC, and LLC2
61 4.3.9. Digital Video Interface
61 4.3.10. Characteristics, TTL Output Driver
62 4.3.10.1. TTL Output Driver Description

2

C Conditions for Low Power Mode

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63 5. Timing Diagrams

63 5.1. Power-up Sequence
63 5.2. Default Wake-up Selection
64 5.3. Control Bus Timing Diagram
65 5.4. Output Enable by Pin OE
66 5.5. Timing of the Test Access Port TAP
66 5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain
67 5.7. Timing Diagram of the Digital Video Interface
67 5.7.1. Characteristics, Clock Signals

68 6. Control and Status Registers

68 6.1. Overview
71 6.1.1. Description of I
75 6.1.2. Description of FP Control and Status Registers

2

C Control and Status Registers

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Contents, continued

Page Section Title

87 7. Application Notes

87 7.1. Differences between VPX 322xE and VPX 322xD-C3
87 7.2. Differences between VPX 322xE and VPX 3220A
88 7.3. Control Interface
88 7.3.1. Symbols

2

88 7.3.2. Write Data into I
88 7.3.3. Read Data from I
88 7.3.4. Write Data into FP Register
88 7.3.5. Read Data from FP Register
88 7.3.6. Sample Control Code
89 7.4. Xtal Supplier
90 7.5. Typical Application

92 8. Data Sheet History

C Register

2

C Register

VPX 322xE

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VPX 322xE

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Video Pixel Decoders

Note: This data sheet describes functions and char­acteristics of VPX 322xE-A1.

1. Introduction

The Video Pixel Decoders VPX 322xE are the third gen­eration of full feature video acquisition ICs for consumer
video and multimedia applications. All of the processing
necessary to convert an analog video signal into a digital
component stream have been integrated onto a single
44-pin IC. Moreover, the VPX 3225E and VPX 3226E
provide text slicing for intercast, teletext, and closed
caption. For improved Y/C separation, the VPX 3226E
includes an adaptive 4H comb filter. All chips are pin
compatible to VPX 3220A, VPX 3214C, and VPX 322xD.
Their notable features include:

Video Decoding

– high-performance adaptive 4H comb filter Y/C separa-

tor with adjustable vertical peaking (VPX 3226E only)

– multistandard color decoding:

• NTSC-M, NTSC-443

• PAL-BDGHI, PAL-M, PAL-N, PAL-60

• SECAM

• S-VHS

– two 8-bit video A/D converters with clamping and auto-

matic gain control (AGC)

Video Interfacing

– YC
– ITU-R 601 compliant output format
– ITU-R 656 compliant output format
– BStream compliant output format
– square pixel format (640 or 768 pixel/line)
– 8-bit or 16-bit synchronous output mode
– 13.5 MHz/16-bit and 27 MHz/8-bit output rate
– VBI bypass and raw ADC data output

Data Broadcast Support (VPX 3225/6E only)

– high-performance data slicing in hardware
– multistandard data slicer

– full support for

– programmable to new standards via I
– VBI and Full-Field mode
– data insertion into video stream
– simultaneous acquisition of Teletext, VPS, WSS, and

Miscellaneous

4:2:2 format

bCr

• NABTS, WST

• CAPTION (1x, 2x), VPS, WSS, Antiope

• Teletext, Intercast, Wavetop,

• WebTV for Windows, EPG services

2

C

Caption

– four analog inputs with integrated selector for:

• 3 composite video sources (CVBS), or

• 2 Y/C sources (S-VHS), or

• 2 composite video sources and one Y/C source.

– horizontal and vertical sync detection for all standards
– decodes and detects Macrovision 7.1 protected video

Video Processing

– hue, brightness, contrast, and saturation control
– dual window cropping and scaling
– horizontal resizing between 32 and 864 pixels/line
– vertical resizing by line dropping
– high-quality anti-aliasing filter
– scaling controlled peaking and coring

– 44-pin PLCC and PMQFP packages
– reduced power consumption of below 500 mW

2

C serial control, 2 different device addresses

– I
– on-chip clock generation, only one crystal needed for

all standards
– user programmable output pins
– power-down mode
– IEEE 1149.1 (JTAG) boundary scan interface

– 8 input or user programmable output pins

Software Support

– MediaCVR Software Suite

• Video for Windows driver

• TV viewer applet, Teletext browser

• Intercast/Wavetop browser

– WebTV for Windows

• Video capture and VBI services

6 Micronas

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Q

K

1.1. System Architecture

The block diagram (Fig. 1–1) illustrates the signal flow
through the VPX. A sampling stage performs 8-bit A/D
conversion, clamping, and AGC. The color decoder sep­arates the luma and chroma signals, demodulates the
chroma, and filters the luminance. A sync slicer detects
the sync edge and computes the skew relative to the
sample clock. The video processing stage resizes the
YC

samples, adjusts the contrast and brightness,

bCr

and interpolates the chroma. The text slicer extracts
lines with text information and delivers decoded data
bytes to the video interface.

Note: The VPX 322xE is register compatible with the
VPX 322xD family, but not with VPX 3220A, VPX 3216B,
and VPX 3214C family.

VPX 322xE

CVBS/Y

Chroma

SDA

SCL

RES

Clock Gen.

DCO

MUX

ADC

MUX

ADC

I2C JTAG

(VPX 3226E only)

Adaptive 4H CombFilter

MUX

Sync Processing

Text Slicer

(not VPX 3224E)

Luma Filter

Video Decoder

Chroma
Demodulator

Line Store

YY

C

bCr

CbC

Video Processing

Video Interface

r

PortPort

HREF
VREF
FIELD

A[7:0]

OEQ

B[7:0]

PIXCL
LLC
VACT

TDI

TCK

TMS

Fig. 1–1: Block diagram of the VPX 322xE

TDO

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VPX 322xE

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2. Functional Description

The following sections provide an overview of the differ­ent functional blocks within the VPX. Most of them are
controlled by the Fast Processor (‘FP’) embedded in the
decoder. For controlling, there are two classes of regis-

2

ters: I

C registers (directly addressable via I2C bus) and
FP-RAM registers (RAM memory of the FP; indirectly
addressable via I

2

C bus). For further information, see

section 2.15.1.

2.1. Analog Front-End

This block provides the analog interfaces to all video in­puts and mainly carries out analog-to-digital conversion
for the following digital video processing. A block dia­gram is given in Fig. 2–1.

Clamping, AGC, and clock DCO are digitally controlled.
The control loops are closed by the embedded proces­sor.

2.1.1. Input Selector

Up to four analog inputs can be connected. Three inputs
(VIN1–3) are for input of composite video or S-VHS luma
signal. These inputs are clamped to the sync back porch
and are amplified by a variable gain amplifier. Two in­puts, one dedicated (CIN) and one shared (VIN1), are
for connection of S-VHS carrier-chrominance signal.
The chrominance input is internally biased and has a
fixed gain amplifier.

pacitors and is generated by digitally controlled current
sources. The clamping level is the back porch of the vid­eo signal. S-VHS chroma is AC coupled. The input pin
is internally biased to the center of the ADC input range.

2.1.3. Automatic Gain Control

A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC.

2.1.4. Analog-to-Digital Converters

Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8-bit reso­lution. An integrated bandgap circuit generates the re­quired reference voltages for the converters. The two
ADCs are of a 2-stage subranging type.

2.1.5. ADC Range

The ADC input range for the various input signals and
the digital representation is given in Table 2–1 and Fig.
2–2. The corresponding output signal levels of the
VPX 32xx are also shown.

2.1.6. Digitally Controlled Clock Oscillator

2.1.2. Clamping

The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling ca-

CVBS/Y

CVBS/Y

CVBS/Y/C

Chroma

VIN3

VIN2

clamp

VIN1

CIN

bias

input mux

reference

generation

AGC
+6/–4.5 dB

gain

The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
FP; the clock frequency can be adjusted within
±150 ppm.

digital CVBS or Luma

digital Chroma

system clocks

frequency

ADC

ADC

DCVO
±150
ppm

20.25 MHz

Fig. 2–1: Analog front-end

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Table 2–1: ADC input range for PAL input signal and corresponding output signal ranges

VPX 322xE

Signal Input Level [mVpp] ADC

Range

–6 dB 0 dB +4.5 dB [steps] [steps]

CVBS 100% CVBS 667 1333 2238 252 –

75% CVBS 500 1000 1679 213 –

video (luma) 350 700 1175 149 224

sync height 150 300 504 64 –

clamp level 68 16

Chroma burst 300 64 –

100% Chroma 890 190 128$112

75% Chroma 670 143 128$84

bias level 128 128

YCrC

b

Output
Range

CVBS/Y Chroma

upper headroom = 38 steps = 1.4 dB = 25 IRE

255

217
192

128

68

32

0

lower headroom = 4 steps = 0.2 dB

white

black
= clamp

level

video = 100 IRE

sync = 41 IRE

headroom = 56 steps = 2.1 dB

228

192

128

80

32

burst

Fig. 2–2: ADC ranges for CVBS/Luma and Chroma, PAL input signal

100% Chroma

75% Chroma

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VPX 322xE

ADVANCE INFORMATION

2.2. Adaptive Comb Filter (VPX 3226E only)

The 4H adaptive comb filter is used for high-quality lumi­nance/chrominance separation for PAL or NTSC com­posite video signals. The comb filter improves the lumi­nance resolution (bandwidth) and reduces interferences
such as cross-luminance and cross-color. The adaptive
algorithm eliminates most of the mentioned errors with­out introducing new artifacts or noise.

A block diagram of the comb filter is shown in Fig. 2–3.
The filter uses four line delays to process the information
of three video lines. To have a fixed phase relationship
of the color subcarrier in the three channels, the system
clock (20.25 MHz) is fractionally locked to the color sub­carrier. This allows the processing of all color standards
and substandards using a single crystal frequency.

The CVBS signal in the three channels is filtered at the
subcarrier frequency by a set of bandpass/notch filters.
The output of the three channels is used by the adaption
logic to select the weighting that is used to reconstruct
the luminance/chrominance signal from the 4 bandpass/
notch filter signals. By using soft mixing of the 4 signals,
switching artifacts of the adaption algorithm are com­pletely suppressed.

The comb filter uses the middle line as reference, there­fore, the comb filter delay is two lines. If the comb filter
is switched off, the delay lines are used to pass the luma/
chroma signals from the A/D converters to the luma/
chroma outputs. Thus, the processing delay is always
two lines.

In order to obtain the best-suited picture quality, it is pos­sible for the user to influence the behavior of the adap­tion algorithm going from moderate combing to strong
combing. The following three parameters may be ad­justed:

– HDG (horizontal difference gain)
– VDG (vertical difference gain)
– DDR (diagonal dot reducer)

HDG typically defines the comb strength on horizontal
edges. It determines the amount of the remaining cross­luminance and the sharpness on edges respectively. As
HDG increases, the comb strength, e.g. cross lumi­nance reduction and sharpness, increases.

VDG typically determines the comb filter behavior on
vertical edges. As VDG increases, the comb strength,
e.g. the amount of hanging dots, decreases.

After selecting the comb filter performance in horizontal
and vertical direction, the diagonal picture performance
may further be optimized by adjusting DDR. As DDR in­creases, the dot crawl on diagonal colored edges is re­duced.

To enhance the vertical resolution of the the picture, the
VPX 3226E provides a vertical peaking circuitry. The fil­ter gain is adjustable between 0 and +6 dB, and a coring
filter suppresses small amplitudes to reduce noise arti­facts. In relation to the comb filter, this vertical peaking
contributes greatly to an optimal two-dimensional reso­lution homogeneity.

Bandpass
Filter

CVBS Input

Chroma Input

2H Delay Line

2H Delay Line

Bandpass/
Notch
Filter

Bandpass
Filter

Luma / Chroma Mixers

Adaption Logic

Luma Output

Chroma Output

Fig. 2–3: Block diagram of the adaptive comb filter (PAL mode)

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–

–

–

VPX 322xE

2.3. Color Decoder

In this block, the standard luma/chroma separation and

multi-standard color demodulation is carried out. The

color demodulation uses an asynchronous clock, thus

allowing a unified architecture for all color standards.

A block diagram of the color decoder is shown in Fig.

2–5. The luma, as well as the chroma processing, is

shown here. The color decoder also provides several

special modes; for example, wide band chroma format

which is intended for S-VHS wide bandwidth chroma.

The output of the color decoder is YC

in a 4:2:2 for-

rCb

mat.

2.3.1. IF-Compensation

With off-air or mistuned reception, any attenuation at

higher frequencies or asymmetry around the color sub-

carrier is compensated. Four different settings of the IF-

compensation are possible:

– flat (no compensation)

– 6 dB/octave

– 12 dB/octave

– 10 dB/MHz

dB

10

5

0

–5

10

15

20

3.5 3.75 4 4.25 4.5 5

4.75

MHz

Fig. 2–4: Freq. response of chroma IF-compensation

2.3.2. Demodulator

The entire signal (which might still contain luma) is now
quadrature-mixed to the baseband. The mixing frequen­cy is equal to the subcarrier for PAL and NTSC, thus
achieving the chroma demodulation. For SECAM, the
mixing frequency is 4.286 MHz giving the quadrature
baseband components of the FM modulated chroma.
After the mixer, a lowpass filter selects the chroma com­ponents; a downsampling stage converts the color dif­ference signals to a multiplexed half rate data stream.

The last setting gives a very large boost to high frequen-

cies. It is provided for SECAM signals that are decoded

using a SAW filter specified originally for the PAL stan-

dard.

Luma / CVBS

MUXMUX

Chroma

1 H Delay

IF Compensation
DC-Reject

The subcarrier frequency in the demodulator is gener­ated by direct digital synthesis; therefore, substandards
such as PAL 3.58 or NTSC 4.43 can also be demodu­lated.

Notch
Filter

Cross­Switch

MIXER

ACC
Lowpass Filter
Phase/Freq.
Demodulator

Luma

Chroma

Fig. 2–5: Color decoder

Color-PLL/Color-ACC

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VPX 322xE

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2.3.3. Chrominance Filter

The demodulation is followed by a lowpass filter for the
color difference signals for PAL/NTSC. SECAM requires
a modified lowpass function with bell-filter characteristic.
At the output of the lowpass filter, all luma information is
eliminated.

The lowpass filters are calculated in time multiplex for
the two color signals. Four bandwidth settings (narrow,
normal, broad, wide) are available for each standard.
The filter passband can be shaped with an extra peaking
term at 1.25 MHz. For PAL/NTSC, a wide band chroma
filter can be selected. This filter is intended for high
bandwidth chroma signals; for example, a nonstandard
wide bandwidth S-VHS signal.

dB

0

–10

–20

–30

–40

2.3.4. Frequency Demodulator

The frequency demodulator for demodulating the SE­CAM signal is implemented as a CORDIC-structure. It
calculates the phase and magnitude of the quadrature
components by coordinate rotation.

The phase output of the CORDIC processor is differen­tiated to obtain the demodulated frequency. After a pro­grammable deemphasis filter, the Dr and Db signals are
scaled to standard C

amplitudes and fed to the cross-

rCb

over-switch.

2.3.5. Burst Detection / Saturation Control

In the PAL/NTSC-system, the burst is the reference for
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-lock-loop (APC) of the demodula­tor and the automatic color control (ACC) in PAL/NTSC.
The ACC has a control range of +30...–6 dB.

Color saturation can be selected once for all color stan­dards. In PAL/NTSC, it is used as reference for the ACC.
In SECAM, the necessary gains are calculated automat­ically.

–50

012345

PAL/NTSC

dB

0

–10

–20

–30

–40

–50

012345

SECAM

MHz

MHz

Fig. 2–6: Frequency response of chroma filters

For SECAM decoding, the frequency of the burst is mea­sured. Thus, the current chroma carrier frequency can
be identified and is used to control the SECAM proces­sing. The burst measurements also control the color kill­er operation; they can be used for automatic standard
detection as well.

2.3.6. Color Killer Operation

The color killer uses the burst-phase/burst-frequency
measurement to identify a PAL/NTSC or SECAM color
signal. For PAL/NTSC, the color is switched off (killed)
as long as the color subcarrier PLL is not locked. For SE­CAM, the killer is controlled by the toggle of the burst fre­quency. The burst amplitude measurement is used to
switch off the color if the burst amplitude is below a pro­grammable threshold. Thus, color will be killed for very
noisy signals. The color amplitude killer has a program­mable hysteresis.

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VPX 322xE

2.3.7. Automatic Standard Recognition

The burst frequency measurement is also used for auto­matic standard recognition (together with the status of
horizontal and vertical locking) thus allowing a com­pletely independent search of the line and color stan­dard of the input signal. The following standards can be
distinguished:

PAL B, G, H, I; NTSC M; SECAM; NTSC 44; PAL M;
PAL N; PAL 60

For a preselection of allowed standards, the recognition
can be enabled/disabled via I

2

C bus for each standard

separately.

If at least one standard is enabled, the VPX 322xE
checks the horizontal and vertical locking of the input
signal and the state of the color killer regularly. If an error
exists for several adjacent fields, a new standard search
is started. Depending on the measured number of lines
per field and burst frequency, the current standard is se­lected.

For error handling, the recognition algorithm delivers the
following status information:

– search active (busy)

CVBS

8

Notch

filter

Chroma

Process.

Y

C C

r b

Luma

8

Chroma

8

Chroma

Process.

a) conventional b) S-VHS

CVBS

8

Notch

filter

Chroma

Process.

1 H

Delay

c) compensated

Notch

CVBS

8

1 H

Delay

filter

Chroma

Process.

d) comb filter

Fig. 2–7: NTSC color decoding options

Y

Y

CrC

Y

CrC

CrC

b

b

b

– search terminated, but failed
– found standard is disabled
– vertical standard invalid
– no color found

Please refer to Table 6–4 for details.

2.3.8. PAL Compensation/1H Comb Filter

The color decoder uses one fully integrated delay line.
Only active video is stored.

The delay line application depends on the color stan­dard:

– NTSC: 1H comb filter or color compensation
– PAL: color compensation
– SECAM: crossover-switch

In the NTSC compensated mode, Fig. 2–7 c), the color
signal is averaged for two adjacent lines. Thus, cross­color distortion and chroma noise is reduced. In the
NTSC combfilter mode, Fig. 2–7 d), the delay line is in
the composite signal path, thus allowing reduction of
cross-color components, as well as cross-luminance.
The loss of vertical resolution in the luminance channel
is compensated by adding the vertical detail signal with
removed color information.

CVBS

8

Notch

filter

Chroma
Process.

1 H

Delay

a) conventional

Luma

8

Chroma

Chroma

8

Process.

1 H

Delay

b) S-VHS

Fig. 2–8: PAL color decoding options

CVBS

8

Notch

filter

Chroma
Process.

1 H

Delay

MUX

Y

Y

Y

CrC

CrC

CrC

b

b

b

Fig. 2–9: SECAM color decoding

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VPX 322xE

ADVANCE INFORMATION

2.3.9. Luminance Notch

If a composite video signal is applied, the color informa­tion is suppressed by a programmable notch filter. The
position of the filter center frequency depends on the
subcarrier frequency for PAL/NTSC. For SECAM, the
notch is directly controlled by the chroma carrier fre­quency. This considerably reduces the cross-lumi­nance. The frequency responses for all three systems
are shown in Fig. 2–11. In S-VHS mode, this filter is by­passed.

2.4. Video Sync Processing

Fig. 2–10 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is sep­arated by a slicer; the sync phase is measured. The in­ternal controller can select variable windows to improve
the noise immunity of the slicer. The phase comparator
measures the falling edge of sync, as well as the inte­grated sync pulse.

dB

10

0

–10

–20

–30

–40

02 4 68 10

PAL/NTSC notch filter

dB

10

0

–10

–20

MHz

The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.

A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.

For vertical sync separation, the sliced video signal is in­tegrated. The FP uses the integrator value to derive ver­tical sync and field information.

Frequency and phase characteristics of the analog vid­eo signal are derived from PLL1. The results are fed to

video
input

lowpass
1 MHz &

sync
slicer

horizontal
sync
separation

–30

–40

02 4 68 10

SECAM notch filter

Fig. 2–11: Frequency responses of the luma
notch filter for PAL, NTSC, SECAM

the rest of the video processing system in the backend.
The resizer unit uses them for data interpolation and
orthogonalization. A separate timing block derives the
timing reference signals HREF and VREF from the hori­zontal sync.

PLL1

phase
comparator
& lowpass

counter

front
sync
generator

MHz

front sync
skew
vblank
field

clamp &
signal
measurement

Fig. 2–10: Sync separation block diagram

clamping

front-end
timing

color key FIFO_write

clock
synthesizer
syncs

clock
H/V syncs

14 Micronas

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2.5. Macrovision Detection

Video signals from Macrovision encoded VCR tapes are
decoded without loss of picture quality. However it might
be necessary in some applications to detect the pres­ence of Macrovision encoded video signals. This is pos­sible by reading a status register (FP-RAM 0x170).

Macrovision encoded video signals typically have AGC
pulses and pseudo sync pulses added during VBI. The
amplitude of the AGC pulses is modulated in time. The
Macrovision detection logic measures the VBI lines and
compares the signal against programmable thresholds.

The window in which the video lines are checked for Ma­crovision pulses can be defined in terms of start and stop
line (e.g. 6–15 for NTSC).

2.6. Component Processing

Recovery of the YC

components by the decoder is

bCr

followed by horizontal resizing and skew compensation.
Contrast enhancement with noise shaping can also be
applied to the luminance signal. Vertical resizing is sup­ported via line dropping.

Fig. 2–12 illustrates the signal flow through the compo­nent processing stage. The YC

4:2:2 samples are

bCr

separated into a luminance path and a chrominance
path. The Luma Filtering block applies anti-aliasing low­pass filters with cutoff frequencies adapted to the num­ber of samples after scaling, as well as peaking and cor­ing. The Resize and Skew blocks alter the effective
sampling rate and compensate for horizontal line skew.
The YC

samples are buffered in a FIFO for continu-

bCr

ous burst at a fixed clock rate. For luminance samples,
the contrast and brightness can be adjusted and noise
shaping applied. In the chrominance path, C

and C

b

samples can be swapped. Without swapping, the first
valid video sample is a C

sample. Chrominance gain

b

can be adjusted in the color decoder.

r

Y

in

Active Video
Reference

CbC

rin

Luma Filter
with peaking
& coring

Resize

Luma
Phase Shift

Sequence

Control

Chroma
Phase Shift

Resize

Skew

Skew

Latch

F

I

F

O

16 bit

Fig. 2–12: Component processing stage

Table 2–2: Several rasters supported by the resizer

NTSC PAL/SECAM Format Name

640 x 480 768 x 576 Square pixels for broadcast TV (4:3)

704 x 480 704 x 576 Input Raster for MPEG-2

Contrast,

Brightness &

Noise shaping

Cb/Cr-

swapping

Y

out

C

rout

320 x 240 384 x 288 Square pixels for TV (quarter resolution)

352 x 240 352 x 288 CIF – Input raster for MPEG-1, H.261

160 x 120 192 x 144 Square pixels for TV (1/16 resolution), H.324, H.323

176 x 120 176 x 144 QCIF – Input raster for H.261

32 x 24 32 x 24 Video icons for graphical interfaces (square)

15Micronas

VPX 322xE

ADVANCE INFORMATION

2.6.1. Horizontal Resizer

The operating range of the horizontal resizer was cho­sen to serve the widest possible range of applications
and source formats (number of lines, aspect ratio, etc...).
Table 2–2 lists several examples for video sourced from
525/625 line TV systems.

The horizontal resizer alters the sampling raster of the
video signal, thereby varying the number of pixels (NPix)
in the active portion of the video line. The number of pix­els per line is selectable within a range from 32 to 864
in increments of 2 pixels (see section 2.11.: Windowing
the video field). Table 2–2 gives an overview of several
supported video rasters. The visual quality of a sampling
rate conversion operation depends on two factors:

– the frequency response of the individual filters, and
– the number of available filters from which to choose.

The VPX is equipped with a battery of FIR filters to cover
the five octave operating range of the resizer. Fig. 2–13
shows the magnitude response of five example filters
corresponding to 1054, 526, 262, 130, and 32 pixels.

The density of the filter array can be seen in Fig. 2–14.
The magnitude response of 50 filters lying next to each
other are shown. Nevertheless, these are only 10% of all
filters shown. As a whole, the VPX comes with a battery
of 512 FIR filters. Showing these 512 Filters in Fig. 2–13
would result in a large black area. This dense array of fil­ters is necessary in order to maintain constant visual
quality over the range of allowable picture sizes. The al­ternative would be to use a small number of filters whose
cutoff frequencies are regularly spaced over the spec­trum. However, it has been found that using few filters
leads to visually annoying threshold behavior. These ef­fects occur when the filters are changed in response to
variations in the picture size.

dB

0

10

20

30

40

010203040

MHz

Fig. 2–13: Freq. response of 5 widely spaced filters

dB

0

–2

–4

–6

–8

10

Filter selection is performed automatically by the internal
processor based on the selected resizing factor (NPix).
This automated selection is optimized for best visual
performance.

12

0 0.5 1.5 2 3

1 2.5

Fig. 2–14: Freq. response of 50 adjacent filters

MHz

16 Micronas

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VPX 322xE

2.6.2. Skew Correction

The VPX delivers orthogonal pixels with a fixed clock
even in the case of non-broadcast signals with substan­tial horizontal jitter (VCRs, laser disks, certain portions
of the 6 o’clock news...).

This is achieved by highly accurate sync slicing com­bined with post correction. Immediately after the analog
input is sampled, a horizontal sync slicer tracks the posi­tion of sync. This slicer evaluates, to within 1.6 ns, the
skew between the sync edge and the edge of the pixel­clock. This value is passed as a skew on to the phase
shift filter in the resizer. The skew is then treated as a
fixed initial offset during the resizing operation.

The skew block in the resizer performs programmable
phase shifting with subpixel accuracy. In the luminance
path, a linear interpolation filter provides a phase shift
between 0 and 31/32 in steps of 1/32. This corresponds
to an accuracy of 1.6 ns. The chrominance signal can be
shifted between 0 and 7/8 in steps of 1/8.

2.6.3. Peaking and Coring

The horizontal resizer comes with an extra peaking filter
for sharpness control. The center frequency of the peak­ing filter is automatically adjusted to the image size in
512 steps. However, for each size, the user can select
between a low, middle (default), or high center frequen­cy for peaking. The peaking amplitude can be controlled
by the user in 8 steps via FP-RAM 0x126/130. Fig. 2–15
shows the magnitude response of the eight steps of the
peaking filter corresponding to an image size of 320 pix­els.

After the peaking filter, an additional coring filter is imple­mented to the horizontal resizer. The coring filter sub­tracts 0, 1/2, 1, or 2 LSBs of the higher frequency part of
the signal. Note, that coring can be performed indepen­dently of the peaking value adjustment.

dB

10

2.6.4. YCbCr Color Space

The color decoder outputs luminance and one multi­plexed chrominance signal at a sample clock of

20.25 MHz. Active video samples are flagged by a sepa­rate reference signal. Internally, the number of active
samples is 1080 for all standards (525 lines and 625
lines). The representation of the chroma signals is the
ITU-R 601 digital studio standard.

In the color decoder, the weighting for both color differ­ence signals is adjusted individually. The default format
has the following specification:

– Y = 224*Y + 16 (pure binary),
– Cr = 224*(0.713*(R–Y)) + 128 (offset binary),
– Cb = 224*(0.564*(B–Y)) + 128 (offset binary).

2.6.5. Video Adjustments

The VPX provides a selectable gain (contrast) and offset
(brightness) for the luminance samples, as well as addi­tional noise shaping. Both the contrast and brightness
factors can be set externally via I

2

C serial control of FP­RAM 0x127,128,131, and 132. Fig. 2–16 gives a func­tional description of this circuit. First, a gain is applied,
yielding a 10-bit luminance value. The conversion back
to 8-bit is done using one of four selectable techniques:
simple rounding, truncation,1-bit error diffusion, or 2-bit
error diffusion. Bit[8] in the ‘contrast’-register selects be­tween the clamping levels 16 and 32.

I

out

= c * I

+ b c = 0...63/32 in 64 steps

in

b = –127...128 in 256 steps

In the chrominance path, C

and Cr samples can be

b

swapped with bit[8] in FP-RAM 0x126 or 130. Adjust­ment of color saturation and gain is provided via FP­RAM 0x30–33 (see section 2.3.5.).

0

–10

–20

–30

01 34 6

25

MHz

Fig. 2–15: Frequency response of peaking filter

Rounding

Truncation

1 bit

Err. Diff.

2 bit

Err. Diff.

Contrast Select Brightness

FP-RAM
Registers

Fig. 2–16: Contrast and brightness adjustment

17Micronas

VPX 322xE

ADVANCE INFORMATION

2.7. Video Output Interface

Contrary to the component processing stage running at
a clock rate of 20.25 MHz, the output formatting stage
(Fig. 2–17) receives the video samples at a pixel trans­port rate of 13.5 MHz. It supports 8 or 16-bit video for­mats with separate or embedded reference signals, pro­vides bus shuffling, and channels the output via one or
both 8-bit ports. Data transfer is synchronous to the in­ternally generated 13.5 MHz pixel clock.

The format of the output data depends on three parame­ters:

– the selected output format

S YC
S YC
S YC

4:2:2, separate syncs

bCr

4:2:2, ITU-R656

bCr

4:2:2, embedded reference codes (BStream)

bCr

– the number of active ports (A only, or both A and B)

– clock speed (single, double, half).

In 8-bit modes using only Port A for video data, Port B
can be used as programmable output.

2.7.1. Output Formats

The VPX supports the YC

4:2:2 video format only.

bCr

During normal operation, all reference signals are output
separately. To provide a reduced video interface, the
VPX offers two possibilities for encoding timing refer­ences into the video data stream: an ITU-R656 com­pliant output format with embedded timing reference
headers and a second format with single timing control
codes in the video stream. The active output format can
be selected via FP-RAM 0x150 [format].

2.7.1.1. YC

4:2:2 with Separate Syncs/ITU-R601

bCr

The default output format of the VPX is a synchronous
16-bit YC

4:2:2 data stream with separate reference

bCr

signals. Port A is used for luminance and Port B for chro­minance-information. Video data is compliant to ITU­R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig­ure 2–18 shows the timing of the data ports and the
reference signals in this mode.

Video
Samples

Reference
Signals

16 8

Output Formats

Fig. 2–17: Output format stage

Luminance
(Port A)

Chrominance
(Port B)

VACT

8

8

Bus Shuffler

8

Clock

Generation

Output Multiplex

Y

1

C

1

8

8

Y

n–1

C

n–1

8

8

Y

n

C

n

Port A

OE

Port B

PIXCLK
LLC
LLC2

HREF
VREF
VACT

PIXCLK

LLC

Fig. 2–18: Detailed data output (single clock mode)

18 Micronas

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VPX 322xE

2.7.1.2. Embedded Reference Headers/ITU-R656

The VPX supports an output format which is designed to
be compliant with the ITU-R656 recommendation. It is
activated by setting bit[1:0] of FP-RAM 0x150 to 01. The
16-bit video data must be multiplexed to 8 bit at the
double clock frequency (27 MHz) via FP-RAM 0x154,
bit[9] set to 1 (see also Section 2.7.3.: Output Multiplex­er).

In this mode, video samples are in the following order:

C

, Y, Cr, Y, ... The data words 0 and 255 are protected

b

since they are used for identification of reference head­ers. This is assured by limitation of the video data. Tim­ing reference codes are inserted into the data stream at
the beginning and the end of each video line in the fol­lowing way: A ‘Start of active video’-Header (SAV) is in­serted before the first active video sample. The ‘end of
active video’-code (EAV) is inserted after the last active
video sample. They both contain information about the
field type and field blanking. The data words occurring
during the horizontal blanking interval between EAV and
SAV are filled with 0x10 for luminance and 0x80 for chro­minance information. Table 2–3 shows the format of the
SAV and EAV header. Fig. 2–19 and 2–20 show stan­dard ITU-R656 output waveforms.

– For data within the VBI-window (e.g. sliced or raw tele-

text data), the user can select between limitation or re­duction to 7-bit resolution with an additional LSB as­suring odd parity (0 and 255 never occur). This option
can be selected via FP-RAM 0x150 [range].

– The task bit can be used as a qualifier for VBI data. It

is set to zero during the programmed VBI window if
bit[11] in 0x150 is set.

– Ancillary data blocks may be longer than 255 bytes (for

raw data) and are transmitted without checksum. The
secondary data ID is used as high byte of the data
count (DC1; see Table 2–4).

– Ancillary data packets must not follow immediately af-

ter EAV or SAV.

– The total number of clock cycles per line, as well as

valid cycles between EAV and SAV may vary.

Table 2–3: Coding of the SAV/EAV-header

Bit No.

Word MSB LSB

7 6 5 4 3 2 1 0

First 1 1 1 1 1 1 1 1

Note that the following changes and extensions to the
ITU-R656 standard have been included to support hori­zontal and vertical scaling, transmission of VBI-data,
etc.:

– Both the length and the number of active video lines

varies with the selected window parameters. For com­pliance with the ITU-R656 recommendation, a size of
720 samples per line must be selected for each win­dow. To enable a constant line length even in the case
of different scaling values for the video windows, the
VPX provides a programmable ‘active video’ signal
(see section 2.9.4.).

– During blanked lines, the VACT signal is suppressed.

VBI-lines can be marked as blanked or active, thus al­lowing the choice of enabled or suppressed VACT dur­ing the VBI-window. The vertical field blanking flag (V)
in the SAV/EAV header is set to zero in any line with
enabled VACT signal (valid VBI or video lines).

– During blanked lines SAV/EAV headers can be sup-

pressed in pairs with FP-RAM 0x150, bit[9]. To assure
vertical sync detection, some SAV/EAV headers are
inserted during field blanking.

– The flags F,V and H encoded in the SAV/EAV headers

change on SAV. With FP-RAM 0x150, bit[10] set to 1
they change on EAV. The programmed windows how­ever are delayed by one line. Header suppression is
always applied for SAV/EAV pairs.

Second 0 0 0 0 0 0 0 0

Third 0 0 0 0 0 0 0 0

Fourth T F V H P3 P2 P1 P0

T= 0 during VBI data (if enabled), else T = 1
F = 0 during field 1, F = 1 during field 2
V = 0 during active lines V = 1 during vertical field blanking
H = 0 in SAV, H = 1 in EAV

The bits P0, P1, P2, and P3 are protection bits. Their
states are dependent on the states of F, V, and H. They
can be calculated using the following equations:

P

= H xor V xor T

3

P2 = H xor F xor T
P1 = V xor F xor T
P0 = H xor V xor F

The VPX also supports the transmission of VBI-data as
vertical ancillary data during blanked lines in the interval
starting with the end of the SAV and terminating with the
beginning of EAV. In this case, an additional header is in­serted directly before the valid active data; thus, the
position of SAV and EAV depends on the settings for the
programmable VACT signal (see Fig. 2–21). These pa­rameters will be checked and corrected if necessary to
assure an appropriate size of VACT for both data and an­cillary header.

19Micronas

VPX 322xE

ADVANCE INFORMATION

Table 2–4 shows the coding of the ancillary header in­formation. The word I[2:0] contains a value for data type
identification (1 for sliced and 3 for raw data during odd
fields, 5 for sliced and 7 for raw data during even fields).
M[5:0] contains the MSBs and L[5:0] the LSBs of the
number of following D–words (32 for sliced data, 285 for
raw data). DC1 is normally used as secondary data ID.
The value 0 for M[5:0] in the case of sliced data marks
an undefined format. Bit[6](P) is even parity for bit[5] to
bit[0]. Bit[7] is the inverted parity flag. Note that the fol­lowing user data words (video data) are either limited or
have odd parity to assure that 0 and 255 will not occur.
Bit[3] in FP-RAM 0x150 selects between these two op­tions.

current line length

dependent on window size

Digital
Video Output

VACT

EAV

constant during

horizontal blanking

Y = 10

hex

; C

r

= C

b

= 80

SAV

hex

Cb Y Cr Y ...

Table 2–4: Coding of the ancillary header information

Bit No.

Word MSB LSB

7 6 5 4 3 2 1 0

Pream1 0 0 0 0 0 0 0 0

Pream2 1 1 1 1 1 1 1 1

Pream3 1 1 1 1 1 1 1 1

DID NP P 0 1 0 I2 I1 I0

DC1 NP P M5 M4 M3 M2 M1 M0

DC2 NP P L5 L4 L3 L2 L1 L0

Cb Y Cr Y ...

EAV

SAV: “start of active video” header
EAV: “end of active video” header

SAV

Fig. 2–19: Output of video or VBI data with embedded reference headers (according to ITU-R656)

DATA
(Port A)

VACT

PIXCLK

LLC

SAV1SAV2SAV3SAV

10h80h 80h 10hEAV1EAV2EAV3EAV

4

C

b1Y1

Cr1Y2C

bn–1Yn–1

C

rn–1Yn

Fig. 2–20: Detailed data output (double clock mode)

current line length

size of programmable VACT

dependent on VBI-window size

Digital
Video Output

EAV

SAV

D1 D2 D3 D4 ...

ANC

Cb Y Cr Y ...

EAV

SAV

4

constant during

horizontal blanking

Y = 10

hex

; C

r

= C

b

= 80

hex

SAV: “start of active video” header
EAV: “end of active video” header

VACT

Fig. 2–21: Output of VBI-data as ancillary data

20 Micronas

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VPX 322xE

2.7.1.3. Embedded Timing Codes (BStream)

In this mode, several event words are inserted into the
pixel stream for timing information. It is activated by set­ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word
consists of a chrominance code value containing the
phase of the color-multiplex followed by a luminance
code value signalling a specific event. The allowed con­trol codes are listed in Table 2–5 and 2–6.

At the beginning and the end of each active video line,
timing reference codes (start of active video: SAV; end
of active video: EAV) are inserted with the beginning and
the end of VACT (see Fig. 2–23). Since VACT is sup­pressed during blanked lines, video data and SAV/EAV
codes are present during active lines only. If raw/sliced
data should be output, VACT has to be enabled during
the VBI window with bit[2] of FP-RAM 0x138! In the case
of several windows per field, the length of the active data
stream per line can vary. Since the qualifiers for active
video (SAV/EAV) are independent of the other reference
codes, there is no influence on horizontal or vertical
syncs, and sync generation can be performed even with
several different windows. For full compliance with ap­plications requiring data streams of a constant size, the
VPX provides a mode with programmable ‘video active’
signal VACT which can be selected via bit[2] of FP-RAM
0x140. The start and end positions of VACT relative to
HREF is determined by FP-RAM 0x151 and 0x152. The
delay of valid data relative to the leading edge of HREF
is calculated with the formulas given in Table 2–7 and
2–8. The result can be read in FP-RAM 0x10f (for win­dow 1) and 0x11f (for window 2). Be aware that the larg­est window defines the size of the needed memory. In
the case of 1140 raw VBI-samples and only 32 scaled
video samples, the graphics controller needs 570 words
for each line (the VBI-samples are multiplexed to lumi­nance and chrominance paths).

The leading edge of HREF indicates the beginning of a
new video line. Depending on the type of the current line
(active or blanked), the corresponding horizontal refer­ence code is inserted. For big window sizes, the leading
edge of HREF can arrive before the end of the active
data. In this case, hardware assures that the control
code for HREF is delayed and inserted after EAV only.
The VREF control code is inserted at the falling edge of
VREF. The state of HREF at this moment indicates the
current field type (HREF = 0: odd field; HREF = 1: even
field).

In this mode, the words 0, 1, 254, and 255 are reserved
for data identifications. This is assured by limitation of
the video data.

bus shuffler, luminance can be switched to port B and
chrominance to port A. In 8-bit double clock mode, shuf­fling can be used to swap the Y and C components. It is
selected with FP-RAM 0x150.

Table 2–5: Chrominance control codes

Chroma Value Phase Information

FE Cr pixel

FF Cb pixel

2.7.3. Output Multiplexer

During normal operation, a 16-bit YCbCr 4:2:2 data
stream is transferred synchronous to an internally gen­erated PIXCLK at a rate of 13.5 MHz. Data can be
latched onto the falling edge of PIXCLK or onto the rising
edge of LLC during high PIXCLK. In the double clock
mode, luminance and chrominance data are multi­plexed to 8 bit and transferred at the double clock fre­quency of 27 MHz in the order C
chrominance value being a C

, Y, Cr, Y...; the first valid

b

sample. With shuffling

b

switched on, Y and C components are swapped. Data
can be latched with the rising edge of LLC or alternating
edges of PIXCLK. This mode is selected with bit[9] of
FP-RAM 0x154. All 8-bit modes use Port A only. In this
case, Port B can be used as input or activated as pro­grammable output with bit[8] of FP-RAM 0x154. Bit[0–7]
determine the state of Port B (see Fig. 2–22).

to
controller

from
controller

I2C 0xAB

video data

8

8

FP-RAM 0x154 [outmux]

7:0

=0

=1

7:0 8

ben

8

Port
B[7:0]

Fig. 2–22: Port B as input or programmable output port

2.7.4. Output Ports

2.7.2. Bus Shuffler

In the YC

4:2:2 mode, the output of luminance data

bCr

is on port A and chrominance data on port B. With the

The two 8-bit ports produce TTL level signals coded in
binary offset. The Ports can be tristated either via the
output enable pin (OE

) or via I2C register 0xF2. For more
information, see section 2.18. “Enable/Disable of Output
Signals”.

21Micronas

VPX 322xE

ADVANCE INFORMATION

Table 2–6: Luminance control codes

Luma Value Video Event Video Event Phase Information

01 VACT end last pixel was the last active pixel refers to the last pixel

02 VACT begin next pixel is the first active pixel refers to the next pixel

03 HREF active line begin of an active video line refers to the current pixel

04 HREF blank line begin of a blank line refers to the current pixel

05 VREF even begin of an even field refers to the current pixel

06 VREF odd begin of an odd field refers to the current pixel

DATA
(Port A)

VACT

HREF

PIXCLK

LLC

FFh 02h03hFFh FEh 01h

C

b1Y1

Cr1Y2C

bn–1Yn–1

Fig. 2–23: Detailed data output with timing event codes (double clock mode)

2.8. Video Data Transfer

The VPX supports a synchronous video interface. Video
data arrives to each line at the output in an uninterrupted
burst with a fixed transport rate of 13.5 MHz. The dura­tion of the burst is measured in clock periods of the trans­port clock and is equal to the number of pixels per output
line.

The data transfer is controlled via the signals PIXCLK,
VACT, and LLC. An additional clock signal LLC2 can be
switched to the TDO output pin to support different tim­ings.

The VACT signal flags the presence of valid output data.
Fig. 2–24, 2–25, and 2–26 illustrate the relationship be-

2.8.1. Single and Double Clock Mode

Data is transferred synchronous to the internally gener­ated PIXCLK. The frequency of PIXCLK is 13.5 MHz.
The LLC signal is provided as an additional support for
both the 13.5 MHz and the 27 MHz double clock mode.
The LLC consists of a doubled PIXCLK signal (27 MHz)
for interface to external components which rely on the
Philips transfer protocols. In the single clock mode, data
can be latched onto the falling edge of PIXCLK or at the
rising edge of LLC during high PIXCLK. In double clock
mode, output data can be latched onto both clock edges
of PIXCLK or onto every rising edge of LLC. Combined
with the half-clock mode, the available transfer band­widths at the ports are therefore 6.75 MHz, 13.5 MHz,
and 27.0 MHz.

tween the video port data, VACT, PIXCLK, and LLC.
Whenever a line of video data should be suppressed

2.8.2. Clock Gating

(line dropping, switching between analog inputs), it is
done by suppression of VACT.

To assure a fixed number of clock cycles per line, LLC
and LLC2 can be gated during horizontal blanking. This
mode is enabled when bit[7] of FP-RAM 0x153[refsig] is
set to 1. The start and stop timing is defined by
‘pval_start’ and ‘pval_stop’. Note that four additional
LLC cycles are inserted before and after to allow trans­mission of SAV/EAV headers in ITU-R656 mode.

C

rn–1Yn

22 Micronas

ADVANCE INFORMATION

2.8.3. Half Clock Mode

For applications demanding a low bandwidth for the
transmission between video decoder and graphics con­troller, the clock signal qualifying the output pixels
(PIXCLK) can be divided by 2. This mode is enabled by
setting bit[5] of the FP-RAM 0x150 [halfclk]. Note that
the output format ITU-R601 must be selected. The tim­ing of the data and clock signals in this case is described
in Figure 2–26.

If the half-clock mode is enabled, each second pulse of
PIXCLK is gated. PIXCLK can be used as a qualifier for
valid data. To ensure that the video data stream can be
spread, the selected number of valid output samples
should not exceed 400.

VPX 322xE

Luminance
(Port A)

Chrominance
(Port B)

VACT

PIXCLK

LLC

Fig. 2–24: Output timing in single clock mode

Video
(Port A)

VACT

PIXCLK

LLC

Y

1

C

1

C

Y

1

1

Y

n–1

C

n–1

C

n–1

Y

n–1

Y

n

C

n

C

Y

n

n

Fig. 2–25: Output timing in double clock mode

Luminance
(Port A)

Chrominance
(Port B)

VACT

PIXCLK

LLC

Fig. 2–26: Output timing in half clock mode

Y

1

C

1

Y

n

C

n

23Micronas

VPX 322xE

ADVANCE INFORMATION

2.9. Video Reference Signals

The complete video interface of the VPX runs at a clock
rate of 13.5 MHz. It mainly generates two reference sig­nals for the video timing: a horizontal reference (HREF)
and a vertical reference (VREF). These two signals are
generated by programmable hardware and can be ei­ther free running or synchronous to the analog input vid­eo. The video line standard (625/50 or 525/60) depends
on the TV-standard selected with FP-RAM 0x20 [sdt].
The polarity of both signals is individually selectable via
FP-RAM 0x153.

The circuitry which produces the VREF and HREF sig­nals has been designed to provide a stable, robust set
of timing signals, even in the case of erratic behavior at
the analog video input. Depending on the selected oper­ating mode given in FP-RAM 0x140 [settm], the period
of the HREF and VREF signals are guaranteed to re­main within a fixed range. These video reference signals
can therefore be used to synchronize the external com­ponents of a video subsystem (for example the ICs of a
PC add-in card).

In addition to the timing references, valid video samples
are marked with the ‘video active’ qualifier (VACT). In or­der to reduce the signal number of the video interface,
several 8-bit modes have been implemented, where the
reference signals are multiplexed into the data stream
(see section 2.7.1.).

2.9.2. VREF

Figs. 2–28 and 2–29 illustrate the timing of the VREF
signal relative to field boundaries of the two TV stan­dards. The start of the VREF pulse is fixed, while the
length is programmable in the range between 2 and 9
video lines via FP-RAM 0x153 [vlen].

2.9.3. Odd/Even Information (FIELD)

Information on whether the current field is odd or even
is supplied through the relationship between the edge
(either leading or trailing) of VREF and level of HREF.
This relationship is fixed and shown in Figs. 2–28 and
2–29. The same information can be supplied to the
FIELD pin, which can be enabled/disabled as output in
FP-RAM 0x153 [enfieldq]. FP-RAM 0x153 [oepol] pro­grams the polarity of this signal.

During normal operation the FIELD flag is filtered since
most applications need interlaced signals. After filtering,
the field type is synchronized to the input signal only if
the last 8 fields have been alternating; otherwise, it al­ways toggles. This filtering can be disabled with FP­RAM 0x140 [disoef]. In this case, the field information
follows the odd/even property of the input video signal.

2.9.1. HREF

Fig. 2–27 illustrates the timing of the HREF signal rela­tive to the analog input. The inactive period of HREF has
a fixed length of 64 periods of the 13.5 MHz output clock
rate. The total period of the HREF signal is expressed as

F

Analog
Video
Input

HREF

and depends on the video line standard.

nominal

VPX
Delay

4.7 µs (64 cycles)

F

nominal

Fig. 2–27: HREF relative to input video

24 Micronas

ADVANCE INFORMATION

VPX 322xE

625

1234567

Input CVBS
(50 Hz), PAL

34567 8 910

Input CVBS
(60 Hz), NTSC

HREF

361 t

CLK13.5

VREF

2 .. 9 H

FIELD

Fig. 2–28: VREF timing for ODD fields for VPX 3224E and VPX 3225E;
for VPX 3226E: 2 lines additional delay due to 4H comb filter

> 1 t

CLK13.5

361 t

CLK13.5

Input CVBS
(50 Hz), PAL

Input CVBS
(60 Hz), NTSC

HREF

VREF

FIELD

313 314 315 316 317 318 319312 320

265 266 267 268 269 270 271 272 273

46 t

CLK13.5

2 .. 9 H

46 t

> 1 t

CLK13.5

CLK13.5

Fig. 2–29: VREF timing for EVEN fields for VPX 3224E and VPX 3225E;
for VPX 3226E: 2 lines additional delay due to 4H comb filter

25Micronas

VPX 322xE

ADVANCE INFORMATION

2.9.4. VACT

supported [FP-RAM 0x140, vactmode]. The start and

end position for the VACT signal relative to the trailing
The ‘video active’ signal is a qualifier for valid video sam­ples. Since scaled video data is stored internally, there
are no invalid pixel within the VACT interval. VACT has

edge of HREF can be programmed within a range of 0

to 864 [FP-RAM 0x151, 0x152]. In this case, VACT no

longer marks valid samples only.
a defined position relative to HREF depending on the
window settings (see section 2.11.). The maximal win­dow length depends on the minimal line length of the in­put signal. It is recommended to choose window sizes of
less than 800 pixels. Sizes up to 864 are possible, but for
non-standard input lines, VACT is forced inactive 4
PIXCLK cycles before the next trailing edge of HREF.

The position of the valid data depends on the window

definitions. It is calculated from the internal processor.

The calculated delay of VACT relative to the trailing edge

of HREF can be read via FP–RAM 0x10f (window 1) or

0x11f (window 2). Tables 2–7 and 2–8 show the formulas

for the position of valid data samples relative to the trail-

ing edge of HREF.
During the VBI-window, VACT can be enabled or sup­pressed with FP-RAM 0x138. Within this window, the
VPX can deliver either sliced text data with a constant
length of 64 samples or 1140 raw input samples. For ap­plications that request a uniform window size over the
whole field, a mode with a free programmable VACT is

Fig. 2–30 illustrates the temporal relationship between

the VACT and the HREF signals as a function of the

number of pixels per output line and the horizontal di-

mensions of the window. The duration of the inactive pe-

riod of the HREF is fixed to 64 clock cycles.

Table 2–7: Delay of valid output data relative to the trailing edge of HREF (single clock mode)

Mode Data Delay Data End

Video data (HBeg+HLen)*(720/NPix)–Hlen for NPix < 720

DataDelay + HLen

HBeg*(720/NPix) for NPix ≥ 720

Raw VBI data 150 720

Sliced VBI data 726 790

Table 2–8: Delay of valid output data relative to the trailing edge of HREF (half clock mode)

Mode Data Delay Data End

Video data (HBeg+HLen)*(720/NPix)–2*Hlen for NPix < 360

DataDelay + 2*HLen

HBeg*(720/NPix) for NPix ≥ 360

Raw VBI data not possible! not possible!

Sliced VBI data 662 790

DATA
(Port A or B)

VACT

data delay

64 cycles

HREF

D

1

D

n–1

D

n

data end

PIXCLK

LLC

Fig. 2–30: Relationship between HREF and VACT signals (single clock mode)

26 Micronas

ADVANCE INFORMATION

VPX 322xE

2.10. Operational Modes

The relationship between the video timing signals
(HREF and VREF) and the analog input video is deter­mined by the selected operational mode. Two such
modes are available: the Open Mode, and the Scan
Mode. These modes are selected via I

2

C commands

[FP-RAM 0x140, settm, lattm].

2.10.1. Open Mode

In the Open Mode, both the HREF and the VREF signal
track the analog video input. In the case of a change in
the line standard (i.e. switching between the video input
ports), HREF and VREF automatically synchronize to
the new input. When no video is present, both HREF and
VREF float to the idling frequency of their respective
PLLs. During changes in the video input (drop-out,
switching between inputs), the performance of the
HREF and VREF signals is not guaranteed.

2.10.2. Scan Mode

In the Scan Mode, the HREF and VREF signals are al­ways generated by free running hardware. They are
therefore completely decoupled from the analog input.
The output video data is always suppressed.

The purpose of the Scan Mode is to allow the external
controller to freely switch between the analog inputs
while searching for the presence of a video signal. In­formation regarding the video (standard, source, etc...)
can be queried via I

2

C read.

In the Scan Mode, the video line standard of the VREF
and HREF signals can be changed via I

2

C command.
The transition always occurs at the first frame boundary
after the I

2

C command is received. Fig. 2–31, below,
demonstrates the behavior of the VREF signal during
the transition from the 525/60 system to the 625/50 sys­tem (the width of the vertical reference pulse is exagger­ated for illustration).

I2C Command to
switch video timing standard

Selected timing standard
becomes active

VREF

f

odd

16.683 ms

33.367 ms 40.0 ms

f

even

(525/60) (625/50)

Fig. 2–31: Transition between timing standards

f

odd

20.0 ms

f

even

time

f

odd

27Micronas

VPX 322xE

Table 2–9: Transition Behavior as a Function of Operating Mode

Transition Behavior as a Function of Operating Mode

Transition Mode Behavior

ADVANCE INFORMATION

Power up/Reset
(no video)

no video → video Open VREF, HREF: track the input signal

video → no video Open VREF, HREF: floats to steady state frequency of internal PLL

video → video Open VREF, HREF: track the input video immediately

Open VREF, HREF: floats to steady state frequency of internal PLL

Scan no visible effect on any data or control signals

– timing signals continue unchanged in free running mode
– VACT signal is suppressed

Scan no visible effect on any data or control signals

– timing signals continue unchanged in free running mode
– VACT signal is suppressed

Data: available immediately after color decoder locks to input.

Scan no outwardly visible effect on any data or control signals.

– timing signals continue unchanged in free running mode
– VACT signal is suppressed

28 Micronas