Micron MTA8ATF1G64HZ – 8GB User Manual
DDR4 SDRAM SODIMM
Module Height: 30mm (1.181in)
MTA8ATF1G64HZ – 8GB
8GB (x64, SR) 260-Pin DDR4 SODIMM
Features
Features
• DDR4 functionality and operations supported as
defined in the component data sheet
• 260-pin, small-outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC4-2666, PC4-2400, or
PC4-2133
• 8GB (1 Gig x 64)
• VDD = 1.20V (NOM)
• VPP = 2.5V (NOM)
• V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die V
• Single-rank
• On-board I2C serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control command and address bus
= 2.5V (NOM)
DDSPD
generation and calibration
REFDQ
Figure 1: 260-Pin SODIMM (MO-310 R/C A1)
Options Marking
• Operating temperature
– Commercial (0°C ≤ T
• Package
– 260-pin DIMM (halogen-free) Z
• Frequency/CAS latency
– 0.75ns @ CL = 19 (DDR4-2666) -2G6
– 0.83ns @ CL = 17 (DDR4-2400) -2G3
– 0.93ns @ CL = 15 (DDR4-2133) -2G1
≤ 95°C) None
OPER
Table 1: Key Timing Parameters
Industry
Speed
Grade
-2G6 PC4-2666 2666 2666 2400 2133 2133 1866 1866 1600 – 1333 – 14.16 14.16 46.16
-2G4 PC4-2400 – 2400 2400 2400 2133 1866 1866 1600 1600 – 1333 13.32 13.32 45.32
-2G3 PC4-2400 – 2400 2400 2133 2133 1866 1866 1600 1600 1333 – 14.16 14.16 46.16
-2G1 PC4-2133 – – – 2133 2133 1866 1866 1600 1600 – 1333 13.5 13.5 46.5
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atf8c1gx64hz.pdf – Rev. E 4/16 EN
Nomen-
clature
Products and specifications discussed herein are subject to change by Micron without notice.
Data Rate (MT/s)
CL =
20,
CL =19CL =18CL =17CL =16CL =15CL =14CL =13CL =12CL =11CL =
10 CL = 9
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RCD
(ns)
© 2015 Micron Technology, Inc. All rights reserved.
t
RP
(ns)
t
RC
(ns)
8GB (x64, SR) 260-Pin DDR4 SODIMM
Table 2: Addressing
Parameter 8GB
Row address 64K A[15:0]
Column address 1K A[9:0]
Device bank group address 4 BG[1:0]
Device bank address per group 4 BA[1:0]
Device configuration 8Gb (1 Gig x 8), 16 banks
Module rank address CS0_n
Table 3: Part Numbers and Timing Parameters – 8GB Modules
Base device: MT40A1G8,1 8Gb DDR4 SDRAM
Part Number
2
Density Configuration
MTA8ATF1G64HZ-2G6__ 8GB 1 Gig x 64 21.3 GB/s 0.75ns/2666 MT/s 19-19-19
MTA8ATF1G64HZ-2G3__ 8GB 1 Gig x 64 19.2 GB/s 0.83ns/2400 MT/s 17-17-17
MTA8ATF1G64HZ-2G1__ 8GB 1 Gig x 64 17.0 GB/s 0.93ns/2133 MT/s 15-15-15
Module
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Features
Notes:
1. The data sheet for the base device can be found on micron.com.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MTA8ATF1G64HZ-2G3B1.
PDF: 09005aef8621b8d2
atf8c1gx64hz.pdf – Rev. E 4/16 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8GB (x64, SR) 260-Pin DDR4 SODIMM
Pin Assignments
Pin Assignments
The pin assignment table below is a comprehensive list of all possible pin assignments
for DDR4 SODIMM modules. See Functional Block Diagram for pins specific to this
module.
Table 4: Pin Assignments
260-Pin DDR4 SODIMM Front 260-Pin DDR4 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 V
3 DQ5 69 V
5 V
7 DQ1 73 V
9 V
11 DQS0_c 77 V
13 DQS0_t 79 DQ30 145 BA1 211 DQ52 14 V
15 V
17 DQ7 83 DQ26 149 CS0_n 215 DQ49 18 V
19 V
21 DQ3 87 CB5/NC 153 V
23 V
25 DQ13 91 CB1/NC 157 CS1_n/NC223 V
67 DQ29 133 A1 199 DM5_n/
SS
DBI5_n
135 V
SS
71 DQ25 137 CK0_t 203 DQ46 6 V
SS
139 CK0_c 205 V
SS
SS
75 DM3_n/
141 V
201 V
DD
207 DQ42 10 V
DD
SS
SS
DBI3_n
143 PARITY 209 V
SS
81 V
SS
85 V
SS
SS
SS
147 V
DD
151 WE_n/
213 V
217 V
SS
SS
SS
A14
219 DQS6_c 22 V
DD
89 V
SS
155 ODT0 221 DQS6_t 24 DQ12 90 V
SS
SS
2 V
4 DQ4 70 DQ24 136 V
SS
SS
68 V
72 V
134 EVENT_n,NF200 DQS5_t
SS
DD
138 CK1_t/NF 204 DQ47
SS
202 V
8 DQ0 74 DQS3_c 140 CK1_c/NF 206 V
SS
12 DM0_n/
76 DQS3_t 142 V
78 V
144 A0 210 V
SS
DD
208 DQ43
DBI0_n
80 DQ31 146 A10/AP 212 DQ53
SS
16 DQ6 82 V
84 DQ27 150 BA0 216 DQ48
SS
20 DQ2 86 V
SS
SS
148 V
DD
152 RAS_n/
214 V
218 V
A16
88 CB4/NC 154 V
SS
DD
220 DM6_n/
DBI6_n
SS
156 CAS_n/
222 V
A15
26 V
92 CB0/NC 158 A13 224 DQ54
SS
SS
SS
SS
SS
SS
SS
27 V
29 DQ9 95 DQS8_c 161 ODT1/NC227
31 V
33 DM1_n/
93 V
SS
97 DQS8_t 163 V
SS
99 V
159 V
SS
165 C1, CS3_n,NC231 V
SS
DD
DD
225 DQ55 28 DQ8 94 V
V
SS
30 V
229 DQ51 32 DQS1_c 98 V
SS
34 DQS1_t 100 CB6/NC 166 SA2 232 DQ60
DBI_n
35 V
37 DQ15 103 V
39 V
41 DQ10 107 V
43 V
101 CB2/NC 167 V
SS
SS
105 CB3/NC 171 V
SS
SS
109 CKE0 175 V
SS
233 DQ61 36 V
SS
169 DQ37 235 V
237 DQ56 40 V
SS
173 DQ33 239 V
241 DM7_n/
SS
SS
SS
38 DQ14 104 CB7/NC 170 DQ36 236 DQ57
42 DQ11 108 RESET_n 174 DQ32 240 DQS7_c
44 V
DBI7_n
45 DQ21 111 V
47 V
113 BG1 179 DQS4_t 245 DQ62 48 V
SS
49 DQ17 115 BG0 181 V
51 V
SS
117 V
53 DQS2_c 119 A12 185 V
177 DQS4_c 243 V
DD
247 V
SS
183 DQ38 249 DQ58 52 V
DD
251 V
SS
SS
SS
SS
46 DQ20 112 V
50 DQ16 116 ALERT_n 182 DQ39 248 V
54 DM2_n/
55 DQS2_t 121 A9 187 DQ34 253 SCL 56 V
57 V
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atf8c1gx64hz.pdf – Rev. E 4/16 EN
SS
123 V
DD
189 V
255 V
SS
DDSPD
58 DQ22 124 V
3
SS
96 DM8_n/
SS
DBI_n/NC
SS
102 V
SS
106 V
SS
110 CKE1/NC176 V
SS
SS
SS
DD
160 V
162 C0/
CS2_n/NC
164 V
REFCA
168 V
172 V
178 DM4_n/
DD
SS
SS
SS
226 V
228 DQ50
230 V
234 V
238 V
242 DQS7_t
244 V
DBI4_n
114 ACT_n 180 V
SS
118 V
SS
DD
184 V
SS
SS
246 DQ63
250 DQ59
120 A11 186 DQ35 252 V
DBI2_n
122 A7 188 V
SS
190 DQ45 256 SA0
DD
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© 2015 Micron Technology, Inc. All rights reserved.
SS
254 SDA
SS
SS
SS
SS
SS
SS
SS
8GB (x64, SR) 260-Pin DDR4 SODIMM
Pin Assignments
Table 4: Pin Assignments (Continued)
260-Pin DDR4 SODIMM Front 260-Pin DDR4 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
59 DQ23 125 A8 191 DQ44 257 V
61 V
63 DQ19 129 V
65 V
127 A6 193 V
SS
DD
131 A3 197 V
SS
259 V
SS
195 DQ40 – – 64 V
SS
– – 66 DQ28 132 A2 198 DQS5_c – –
PP
PP
60 V
126 A5 192 V
SS
SS
258 V
62 DQ18 128 A4 194 DQ41 260 SA1
SS
130 V
DD
196 V
SS
– –
TT
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8GB (x64, SR) 260-Pin DDR4 SODIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Diagram for pins specific to this module.
Table 5: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for
A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
C0, C1, C2
(RDIMM/LRDIMM on-
ly)
CKx_t
CKx_c
CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
Input Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
Input Clock: Differential clock inputs. All address, command, and control input signals are sampled
READ/WRITE commands in order to select one location out of the memory array in the respective bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE command to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Command Truth Table in the DDR4 component data sheet.
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. x16-based SDRAM only has BG0.
x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
on the crossing of the positive edge of CK_t and the negative edge of CK_c.
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After V
tialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET#) are disabled during self refresh.
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
has become stable during the power-on and ini-
REFCA
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
8GB (x64, SR) 260-Pin DDR4 SODIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol Type Description
ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the
PARITY Input Parity for command and address: This function can be enabled or disabled via the mode
RAS_n/A16
Input Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the com-
CAS_n/A15
WE_n/A14
RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE-
SAx Input
SCL Input
DQx, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. DQ represents
DM_n/DBI_n/
I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
TDQS_t (DMU_n,
DBIU_n), (DML_n/
DBIl_n)
SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
DQS_t
I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
DQS_c
DQSU_t
DQSU_c
DQSL_t
DQSL_c
ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error
EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical tem-
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is enabled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode
registers are programmed to disable RTT.
register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the
clock and at the same time as command and address with CS_n LOW.
mand and/or address being entered and have multiple functions. For example, for activation
with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation command with ACT_n HIGH, these are command pins for READ, WRITE, and other commands defined in Command Truth Table.
SET_n is HIGH. RESET_n must be HIGH during normal operation.
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range
on the I2C bus.
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
and from the temperature sensor/SPD EEPROM on the I2C bus.
DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic redundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of
the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of internal V
level during test via mode register setting MR[4] A[4] = HIGH; training times change
REF
when enabled.
data is masked when DM_n is sampled LOW coincident with that input data during a write access. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the
mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS
is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only
supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
combo device.
tered-aligned with write data. For x16 configurations, DQSL corresponds to the data on
DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe.
flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and
returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW until the on-going DRAM internal recovery transaction is complete. During connectivity test mode,
this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,
ALERT_n pin must be connected to VDD on DIMMs.
perature thresholds have been exceeded. This pin has no function (NF) on modules without
temperature sensors.
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atf8c1gx64hz.pdf – Rev. E 4/16 EN
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