Micron MTA36ASS4G72PF1Z – 32GB User Manual
Module height: 31.25mm (1.23in)
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
DDR4 SDRAM NVRDIMM
MTA36ASS4G72PF1Z – 32GB
Features
Features
• Nonvolatile registered DIMM (NVRDIMM)
– Highly reliable nonvolatile memory solution
– DDR4 RDIMM, NAND Flash, and PowerGEM
management integrated in a single module
– Persistent energy source options
• Option 1: Battery-free power source (PowerGEM)
• Option 2: Persistent DDR4 12V pin
– 32GB (4 Gig x 72) DDR4 RDIMM
– 64GB SLC Flash
– DDR4 functionality and operations supported as
defined in the component data sheet
– JEDEC-compliant DDR4 288-pin dual in-line
memory module connector
– Fast data transfer rate: PC4-2933
– VDD = 1.20V (typical)
– VPP = 2.5V (typical)
– V
– Supports ECC error detection and correction
– Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
– Low-power auto self refresh (LPASR)
– On-die V
– Dual-rank, comprised of TwinDie, x4 DRAM
components
– On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
– 16 internal banks; 4 groups of 4 banks each
– Fixed burst chop (BC) of 4 and burst length (BL)
of 8 via the mode register set (MRS)
– Selectable BC4 or BL8 on-the-fly (OTF)
– Gold edge contacts
– Halogen-free
– Fly-by topology
– Terminated control, command, and address bus
DDSPD
= 2.2–2.8V
generation and calibration
REFDQ
• Battery-free power source (ultra capacitor based
PowerGEM)
– Powers the Micron NVDIMM when the host sys-
tem loses power
– 5-year operating life
– No catastrophic failure modes
– RoHS-, REACH-, and UL-compliant
• Nonvolatile memory (NVM) system-level features
– In-system health monitoring of PowerGEM and
NAND Flash
– Automatic history tracking: tracks critical inter-
nal system parameters
– Interlocked control sequence for safe and reliable
operation (system protocol)
– I2C command/control bus
– Multiple backup trigger methods
• ADR, SAVE_n (DDR4 pin 230) assert, pull up to
2.5V through resistor on the NVDIMM
• RESET_n (DDR4 pin 58)
• SMBus command
Figure 1: 288-Pin NVDIMM (PCB 2562)
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T
– Storage (–25°C ≤ T
STG
≤ +95°C) None
OPER
≤ +125°C)
• Package
– 288-pin DIMM (halogen-free) Z
• Frequency/CAS latency
– 0.68ns @ CL = 21 (DDR4-2933) -2G9
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Table 1: Key Timing Parameters
Data Rate (MT/s)
CL =
20\
PC4-
Grade
Speed
-3G2 3200 3200,
2933
3200,
2933
2933 2666\
19
2666
-2G9 2933 – 2933 2933 2666\
2666
-2G6 2666 – – – 2666\
2666
-2G3 2400 – – – – 2400\
-2G1 2133 – – – – – 2133\
18\
17
2400\
2400
2400\
2400
2400\
2400
2400
16\
15
2133\
2133
2133\
2133
2133\
2133
2133\
2133
2133
14\
13
1866\
1866
1866\
1866
1866\
1866
1866\
1866
1866\
1866
12\
11
1600\
1600
1600\
1600
1600\
1600
1600\
1600
1600\
1600
Features
t
10\
9
RCD
ns
1333\–13.75 13.75 45.75
1333\–14.32
(13.75)
1333\–14.25
(13.75)
1333\–14.16
(13.75)
1333\
1333
14.06
(13.5)
1
1
1
1
t
RP
ns
14.32
(13.75)
14.25
(13.75)
14.16
(13.75)
14.06
(13.5)
1
1
1
1
t
RC
ns24 22 21
46.32
(45.75)
46.25
(45.75)
46.16
(45.75)
47.06
(46.5)
1
1
1
1
Note:
1. Down-bin timing, refer to component data sheet Speed Bin Tables for details.
Table 2: Addressing
Parameter 32GB
Row address 128K A[16:0]
Column address 1K A[9:0]
Device bank group address 4 BG[1:0]
Device bank address per group 4 BA[1:0]
Device configuration 16Gb TwinDie (4 Gig x 4), 16 banks
Module rank address 2 CS_n [1:0]
Table 3: Part Numbers and Timing Parameters – 32GB Modules
Base device: MT40A4G4,1 16Gb TwinDie DDR4 SDRAM
Module
Part Number
Density Configuration
MTA36ASS4G72PF1Z-2G9__ 32GB 4 Gig x 72 23.47 GB/s 0.68ns/2933 MT/s 21-21-21
Notes:
1. The data sheet for the base device can be found on micron.com.
2. All NVDIMM part numbers end with a five-character code (not shown) that designates die revision, PCB revision and controller type. Consult factory for current revision/controller codes. Example:
MTA36ASS4G72PF1Z-2G9PR1AB.
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-nRCD-nRP)
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Features
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
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ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
288-pin DDR4 Registered ‘PF1Z’ NVDIMM
SDRAM
Register
MUX
NVDIMM
Controller
Force_
save_n
SMB
Slave
NAND
Flash
Power
Management
Option 1
Option 2
Backup
Energy
Source
System
Power
Supply
DDR4
Host
SMB master
SPD interface
SAVE_n
1.2V/12V
Reset_n
RESET_n
VDD_2.5
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
NVDIMM System Block Diagram
This Micron NVDIMM is available as a 288-pin DDR4 RDIMM with a 72-bit-wide data
bus in a dual-rank x4 configuration, using 16Gb TwinDie DRAM components for 32GB
DRAM density.
Figure 2: Micron DDR4 NVDIMM System Block Diagram
NVDIMM System Block Diagram
A persistent energy source ensures continuity of power to the Micron NVDIMM after
the system power supply is interrupted. This enables the NVDIMM to save the contents
of the DDR4 SDRAM to the nonvolatile NAND Flash memory and shut down independently from the system's power supply.
The persistent energy source can be provided to the NVDIMM in one of two ways:
•
Option 1 – PowerGEM (green energy module): Designed by Agiga Tech,® this ultraca-
pacitor-based energy source is connected to the Micron NVDIMM via a proprietary
cable and connection, providing backup power as well as health monitoring features.
The ultracaps are charged through the 12V power pin on the DDR4 connector. Please
refer to the Ultracapacitor Power Module data sheet available from micron.com for
further information.
•
Option 2 – Backup Energy Source: Consists of a rechargeable energy source provided
by the system. After power interruption, the persistent 12V power pin on the JEDECcompliant DDR4 DIMM connector supplies the power needed to backup the data
from the DDR4 SDRAM to the NAND Flash. Implementation of this option requires
further system design. Without implementation of the PowerGEM, health monitoring
and power management become dependent on the system design.
Host Coordination Using Micron NVDIMM Control Signal
To prevent SDRAM data corruption due to a sudden power failure, the host must take
steps to ensure the SDRAM is placed in a safe state as soon as a power failure has been
detected.
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Host Coordination Using Micron NVDIMM Control Signal
The Micron NVDIMM will be able to provide proper coordination if the host meets the
following requirements:
• The host must have early warning that power is failing, allowing it to perform an orderly shutdown. Typically, this is achieved by the system monitoring the system power supply and providing a signal that indicates power is failing.
• The host must put the DDR4 SDRAM into self refresh before handing it off to the Micron NVDIMM subsystem. After this state is entered, the clock enable (CKE0) signal is
LOW and all SDRAM control signals except CKE0 and RESET_n are "Don't Care." The
SDRAM refreshes itself in this mode, preserving its contents as the host triggers the
NVDIMM to take control of the SDRAM, and the SDRAM contents are backed up to
the Flash memory.
• When the host regains control of the DDR4 SDRAM from the Micron NVDIMM controller (for example, after performing a RESTORE operation), the host must remove
the DDR4 SDRAM from self refresh. The host should take care not to assert the RESET_n signal after a RESTORE operation completes, as the RESET_n signal resets the
internal SDRAM state machine and restored data can be potentially lost.
For more detailed information regarding host coordination with the Micron NVDIMM
controller, refer to the Micron NVDIMM firmware specification.
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Pin Assignments
Pin Assignments
The pin assignment table below is a comprehensive list of all possible pin assignments
for DDR4 RDIMM modules. See the Functional Block Diagram for pins specific to this
module.
Table 4: Pin Assignments
288-Pin DDR4 NVDIMM Front 288-Pin DDR4 NVDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 12V 37 V
2 V
38 DQ24 74 CK0_t 110 DQS14_t/
SS
3 DQ4 39 V
4 V
SS
40 DQS12_t/
TDQS12_t
5 DQ0 41 DQS12_c/
TDQS12_c
6 V
7 DQS9_t/
42 V
SS
43 DQ30 79 A0 115 DQ42 151 V
TDQS9_t
8 DQS09_c/
44 V
TDQS9_c
9 V
45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 V
SS
73 V
SS
75 CK0_c 111 DQS14_c/
SS
76 V
77 V
78 EVENT_n 114 V
SS
80 V
SS
DD
DD
TT
DD
109 V
145 12V 181 DQ29 217 V
SS
146 V
TDQS14_t
147 V
TDQS14_c
112 V
148 DQ5 184 V
SS
113 DQ46 149 V
150 DQ1 186 DQS3_t 222 PARITY 258 DQ47
SS
116 V
152 DQS0_c 188 DQ31 224 BA1 260 DQ43
SS
REFCA
SS
SS
SS
253 DQ41
DD
182 V
218 CK1_t 254 V
SS
183 DQ25 219 CK1_c 255 DQS5_c
220 V
SS
185 DQS3_c 221 V
187 V
223 V
SS
225 A10/AP261 V
SS
DD
TT
DD
256 DQS5_t
257 V
259 V
SS
SS
SS
SS
10 DQ6 46 V
11 V
47 CB4 83 V
SS
12 DQ2 48 V
13 V
49 CB0 85 V
SS
14 DQ12 50 V
15 V
SS
51 DQS17_t/
SS
SS
SS
TDQS17_t
16 DQ8 52 DQS17_c/
TDQS17_c
17 V
18 DQS10_t/
53 V
SS
54 CB6 90 V
SS
TDQS10_t
19 DQS10_c/
55 V
SS
TDQS10_c
20 V
21 DQ14 57 V
22 V
23 DQ10 59 V
24 V
56 CB2 92 V
SS
SS
58 RESET_n 94 V
SS
DD
60 CKE0 96 V
SS
82 RAS_n/
118 V
A16
119 DQ48 155 DQ7 191 V
DD
84 CS0_n 120 V
121 DQS15_t/
DD
TDQS15_t
86 CAS_n/
A15
122 DQS15_c/
TDQS15_c
87 ODT0 123 V
88 V
124 DQ54 160 V
DD
89 CS1_n/NC125 V
126 DQ50 162 V
DD
91 ODT1/NC127 V
128 DQ60 164 DQS1_t 200 V
DD
93 CS2_n/C0129 V
130 DQ56 166 DQ15 202 V
SS
95 DQ36 131 V
132 DQS16_t/
SS
TDQS16_t
SS
SS
154 V
156 V
190 DQ27 226 V
SS
SS
192 CB5 228 WE_n/
SS
DD
227 NC 263 V
A14
157 DQ3 193 V
158 V
159 DQ13 195 V
SS
161 DQ9 197 DQS8_t 233 V
SS
163 DQS1_c 199 CB7 235 NC/C2271 DQ51
SS
165 V
SS
194 CB1 230 SAVE_n 266 DQS6_c
SS
196 DQS8_c 232 A13 268 V
SS
198 V
SS
201 CB3 237 CS3_n/
SS
229 V
SS
231 V
SS
234 A17 270 V
SS
236 V
SS
DD
DD
DD
DD
C1, NC
238 SA2 274 V
SS
167 V
SS
168 DQ11 204 V
203 CKE1/NC239 V
SS
DD
SS
240 DQ37 276 V
262 DQ53
SS
264 DQ49
265 V
SS
267 DQS6_t
SS
269 DQ55
SS
272 V
SS
273 DQ61
SS
275 DQ57
SS
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Pin Descriptions
Table 4: Pin Assignments (Continued)
288-Pin DDR4 NVDIMM Front 288-Pin DDR4 NVDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
25 DQ20 61 V
26 V
62 ACT_n 98 V
SS
27 DQ16 63 BG0 99 DQS13_t/
28 V
29 DQS11_t/
64 V
SS
65 A12/BC_n 101 V
TDQS11_t
30 DQS11_c/
66 A9 102 DQ38 138 V
TDQS11_c
31 V
67 V
SS
32 DQ22 68 A8 104 DQ34 140 SA1 176 V
33 V
69 A6 105 V
SS
34 DQ18 70 V
35 V
71 A3 107 V
SS
36 DQ28 72 A1 108 DQ40 144 NC 180 V
97 DQ32 133 DQS16_c/
DD
SS
TDQ13_t
100 DQS13_c/
DD
TDQS13_c
SS
103 V
DD
106 DQ44 142 V
DD
SS
SS
SS
169 V
205 NC 241 V
SS
SS
277 DQS7_c
TDQS16_c
134 V
135 DQ62 171 V
136 V
137 DQ58 173 V
170 DQ21 206 V
SS
207 BG1 243 V
SS
172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63
SS
209 V
SS
174 DQS2_c 210 A11 246 V
SS
242 DQ33 278 DQS7_t
DD
SS
245 DQS4_t 281 V
DD
SS
279 V
282 DQ59
139 SA0 175 DQS2_t 211 A7 247 DQ39 283 V
SS
212 V
DD
248 V
284 V
SS
DDSPD
141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA
143 V
178 V
PP
179 DQ19 215 V
PP
214 A4 250 V
SS
DD
216 A2 252 V
SS
286 V
SS
251 DQ45 287 V
288 V
SS
SS
SS
SS
PP
PP
PP
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
UDIMM, RDIMM, SODIMM, and LRDIMM modules. All pins listed may not be supported on the module defined in this data sheet. See functional block diagram specific to
this module to review all pins utilized on this module.
Table 5: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have
additional functions; see individual entries in this table). The address inputs also provide the op-code during the MODE REGISTER SET command. A17 is only defined for
x4 SDRAM configuration.
A10/AP Input Auto precharge: A10 is sampled during READ and WRITE commands to determine
whether auto precharge should be performed to the accessed bank after a READ or
WRITE operation (HIGH = Auto precharge; LOW = No auto precharge). A10 is sampled
during a PRECHARGE command to determine whether the PRECHARGE applies to one
bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by the bank group and bank addresses.
A12/BC_n Input Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if
burst chop (on-the-fly) will be performed. (HIGH = No burst chop; LOW = Burst-chopped). See the Command Truth Table in DDR4 component data sheet for more information.
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2019 Micron Technology, Inc. All rights reserved.
32GB (x72, ECC, TwinDie, DR) 288-Pin DDR4 NVRDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol Type Description
ACT_n Input Command input: ACT_n defines the activation command being entered along with
CS_n. The input into RAS_n/A16, CAS_n/A15, and WE_n/A14 will be considered as row
address A16, A15, and A14. See the Command Truth Table in DDR4 component data
sheet for more information.
BAx Input Bank address inputs: Define to which bank an ACTIVATE, READ, WRITE, or PRE-
CHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command.
BGx Input Bank group address inputs: Define to which bank group a REFRESH, ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are
used in the x4 and x8 configurations. x16-based SDRAMs only have BG0.
C0, C1, C2
(RDIMM/LRDIMM
only)
CKx_t
CKx_c
CKEx Input Clock enable: CKE HIGH activates, and CKE LOW deactivates, the internal clock sig-
CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides
ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal
PARITY Input Parity for command and address: This function can be enabled or disabled via the
Input Chip ID: These inputs are used only when devices are stacked, that is, 2H, 4H, and 8H
stacks for x4 and x8 configurations using though-silicon vias (TSVs). These pins are not
used in the x16 configuration. Some DDR4 modules support a traditional DDP package, which use CS1_n, CKE1, and ODT1 to control the second die. For all other stack
configurations, such as a 4H or 8H, it is assumed to be a single-load (master/slave)type configuration where C0, C1, and C2 are used as chip ID selects in conjunction
with a single CS_n, CKE, and ODT. Chip ID is considered part of the command code.
Input Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
nals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self refresh exit. After V
come stable during the power-on and initialization sequence, it must be maintained
during all operations (including SELF REFRESH). CKE must be held HIGH throughout
read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE)
are disabled during power-down. Input buffers (excluding CKE and RESET_n) are disabled during self refresh.
external rank selection on systems with multiple ranks. CS_n is considered part of the
command code. CS2_n and CS3_n are not used on UDIMMs.
to the DDR4 SDRAM. When ODT is enabled, on-die termination (RTT) is applied only to
each DQ, DQS_t, DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is enabled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, UDM_n, and
LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to
disable RTT.
mode register. When enabled in MR5, then DRAM calculates Parity with ACT_n,
RAS_n/A16, CAS_n/A15, WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be
maintained at the rising edge of the clock and at the same time with command and
address with CS_n LOW.
REFCA
has be-
CCM005-341111752-10458
ass36c4gx72pf1z.pdf - Rev. B 04/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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