Micron MTA18ASF2G72PDZ – 16GB User Manual

DDR4 SDRAM RDIMM

Module height: 31.25mm (1.23in)

MTA18ASF2G72PDZ – 16GB

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Features

• DDR4 functionality and operations supported as defined in the component data sheet

• 288-pin, registered dual in-line memory module (RDIMM)

• Fast data transfer rates: PC4-2666, PC4-2400

• 16GB (2 Gig x 72)

• VDD = 1.20V (NOM)

• VPP = 2.5V (NOM)

• V

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

• Low-power auto self refresh (LPASR)

• Data bus inversion (DBI) for data bus

• On-die V

• Dual-rank

• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM

• 16 internal banks; 4 groups of 4 banks each

• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

= 2.5V (NOM)

DDSPD

generation and calibration

REFDQ

Figure 1: 288-Pin RDIMM (MO-309, R/C-E1)

Options Marking

• Operating temperature – Commercial (0°C ≤ T

• Package – 288-pin DIMM (halogen-free) Z

• Frequency/CAS latency – 0.75ns @ CL = 19 (DDR4-2666) -2G6 – 0.83ns @ CL = 17 (DDR4-2400) -2G3

≤ 95°C) None

OPER

Table 1: Key Timing Parameters

Industry Speed Grade

-2G6 PC4-2666 2666 2666 2400 2133 2133 1866 1866 1600 – 1333 – 14.16 14.16 46.16

-2G4 PC4-2400 – 2400 2400 2400 2133 1866 1866 1600 1600 – 1333 13.32 13.32 45.32

-2G3 PC4-2400 – 2400 2400 2133 2133 1866 1866 1600 1600 1333 – 14.16 14.16 46.16

-2G1 PC4-2133 – – – 2133 2133 1866 1866 1600 1600 – 1333 13.5 13.5 46.5

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Nomen-

clature

Data Rate (MT/s)

CL =

20,

CL =19CL =18CL =17CL =16CL =15CL =14CL =13CL =12CL =11CL =

10 CL = 9

1

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

t

RCD

(ns)

t

RP

(ns)

t

RC

(ns)

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Table 2: Addressing

Parameter 16GB

Row address 64K A[15:0]

Column address 1K A[9:0]

Device bank group address 4 BG[1:0]

Device bank address per group 4 BA[1:0]

Device configuration 8Gb (1 Gig x 8), 16 banks

Module rank address 2 CS_n[1:0]

Table 3: Part Numbers and Timing Parameters – 16GB Modules

Base device: MT40A1G8,1 8Gb DDR4 SDRAM

Part Number

2

Density Configuration

MTA18ASF2G72PDZ-2G6__ 16GB 2 Gig x 72 21.3 GB/s 0.75ns/2666 MT/s 19-19-19

MTA18ASF2G72PDZ-2G3__ 16GB 2 Gig x 72 19.2 GB/s 0.83ns/2400 MT/s 17-17-17

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

Features

Notes:

1. The data sheet for the base device can be found on micron.com.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MTA18ASF2G72PDZ-2G6B1.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Pin Assignments

The pin assignment table below is a comprehensive list of all possible pin assignments for DDR4 RDIMM modules. See the Functional Block Diagram for pins specific to this module.

Table 4: Pin Assignments

288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 NC 37 V

2 V

38 DQ24 74 CK0_t 110 DQS14_t/

SS

3 DQ4 39 V

4 V

SS

40 DQS12_t/

TDQS12_t

5 DQ0 41 DQS12_c/

TDQS12_c

6 V

7 DQS9_t/

42 V

SS

43 DQ30 79 A0 115 DQ42 151 V

TDQS9_t

8 DQS09_c/

44 V

TDQS9_c

9 V

45 DQ26 81 BA0 117 DQ52 153 DQS0_t 189 V

SS

73 V

SS

75 CK0_c 111 DQS14_c/

SS

76 V

77 V

78 EVENT_n 114 V

SS

80 V

SS

DD

TT

DD

109 V

145 NC 181 DQ29 217 V

SS

146 V

TDQS14_t

147 V

TDQS14_c

112 V

148 DQ5 184 V

SS

113 DQ46 149 V

150 DQ1 186 DQS3_t 222 PARITY 258 DQ47

SS

116 V

152 DQS0_c 188 DQ31 224 BA1 260 DQ43

SS

REFCA

SS

253 DQ41

DD

182 V

218 CK1_t 254 V

SS

183 DQ25 219 CK1_c 255 DQS5_c

220 V

SS

185 DQS3_c 221 V

187 V

223 V

SS

225 A10/AP261 V

SS

DD

TT

DD

256 DQS5_t

257 V

259 V

SS

10 DQ6 46 V

11 V

47 CB4 83 V

SS

12 DQ2 48 V

13 V

49 CB0 85 V

SS

14 DQ12 50 V

15 V

SS

51 DQS17_t/

SS

TDQS17_t

16 DQ8 52 DQS17_c/

TDQS17_c

17 V

18 DQS10_t/

53 V

SS

54 CB6 90 V

SS

TDQS10_t

19 DQS10_c/

55 V

SS

TDQS10_c

20 V

21 DQ14 57 V

22 V

23 DQ10 59 V

24 V

56 CB2 92 V

SS

58 RESET_n 94 V

SS

DD

60 CKE0 96 V

SS

82 RAS_n/

118 V

A16

119 DQ48 155 DQ7 191 V

DD

84 CS0_n 120 V

121 DQS15_t/

DD

TDQS15_t

86 CAS_n/

A15

122 DQS15_c/

TDQS15_c

87 ODT0 123 V

88 V

124 DQ54 160 V

DD

89 CS1_n/NC125 V

126 DQ50 162 V

DD

91 ODT1/NC127 V

128 DQ60 164 DQS1_t 200 V

DD

93 CS2_n/C0129 V

130 DQ56 166 DQ15 202 V

SS

95 DQ36 131 V

132 DQS16_t/

SS

TDQS16_t

SS

154 V

156 V

190 DQ27 226 V

SS

192 CB5 228 WE_n/

SS

DD

227 NC 263 V

A14

157 DQ3 193 V

158 V

159 DQ13 195 V

SS

161 DQ9 197 DQS8_t 233 V

SS

163 DQS1_c 199 CB7 235 NC/C2271 DQ51

SS

165 V

SS

194 CB1 230 NC 266 DQS6_c

SS

196 DQS8_c 232 A13 268 V

SS

198 V

SS

201 CB3 237 CS3_n/

SS

229 V

SS

231 V

SS

234 A17 270 V

SS

236 V

SS

DD

C1, NC

238 SA2 274 V

SS

167 V

SS

168 DQ11 204 V

203 CKE1/NC239 V

SS

DD

SS

240 DQ37 276 V

262 DQ53

SS

264 DQ49

265 V

SS

267 DQS6_t

SS

269 DQ55

SS

272 V

SS

273 DQ61

SS

275 DQ57

SS

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

3

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Pin Assignments

Table 4: Pin Assignments (Continued)

288-Pin DDR4 RDIMM Front 288-Pin DDR4 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

25 DQ20 61 V

26 V

62 ACT_n 98 V

SS

27 DQ16 63 BG0 99 DQS13_t/

28 V

29 DQS11_t/

64 V

SS

65 A12/BC_n 101 V

TDQS11_t

30 DQS11_c/

66 A9 102 DQ38 138 V

TDQS11_c

31 V

67 V

SS

32 DQ22 68 A8 104 DQ34 140 SA1 176 V

33 V

69 A6 105 V

SS

34 DQ18 70 V

35 V

71 A3 107 V

SS

36 DQ28 72 A1 108 DQ40 144 NC 180 V

97 DQ32 133 DQS16_c/

DD

SS

TDQ13_t

100 DQS13_c/

DD

TDQS13_c

SS

103 V

DD

106 DQ44 142 V

DD

SS

169 V

205 NC 241 V

SS

277 DQS7_c

TDQS16_c

134 V

135 DQ62 171 V

136 V

137 DQ58 173 V

139 SA0 175 DQS2_t 211 A7 247 DQ39 283 V

170 DQ21 206 V

SS

207 BG1 243 V

SS

172 DQ17 208 ALERT_n 244 DQS4_c 280 DQ63

SS

209 V

SS

174 DQS2_c 210 A11 246 V

SS

212 V

SS

242 DQ33 278 DQS7_t

DD

SS

245 DQS4_t 281 V

DD

SS

248 V

DD

SS

279 V

SS

282 DQ59

SS

284 V

DDSPD

141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA

143 V

178 V

PP

179 DQ19 215 V

PP

214 A4 250 V

SS

DD

216 A2 252 V

SS

286 V

SS

251 DQ45 287 V

288 V

SS

PP

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

DQ Map

Table 5: Component-to-Module DQ Map

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

DQ Map

Component

Reference

Number

U2 0 3 157 U3 0 11 168

U4 0 19 179 U5 0 27 190

U6 0 CB3 201 U8 0 35 249

U9 0 43 260 U10 0 51 271

U11 0 59 282 U12 0 56 130

Component

DQ Module DQ

1 0 5 1 8 16

2 2 12 2 10 23

3 1 150 3 9 161

4 7 155 4 15 166

5 4 3 5 12 14

6 6 10 6 14 21

7 5 148 7 13 159

1 16 27 1 24 38

2 18 34 2 26 45

3 17 172 3 25 183

4 23 177 4 31 188

5 20 25 5 28 36

6 22 32 6 30 43

7 21 170 7 29 181

1 CB0 49 1 32 97

2 CB2 56 2 34 104

3 CB1 194 3 33 242

4 CB7 199 4 39 247

5 CB4 47 5 36 95

6 CB6 54 6 38 102

7 CB5 192 7 37 240

1 40 108 1 48 119

2 42 115 2 50 126

3 41 253 3 49 264

4 47 258 4 55 269

5 44 106 5 52 117

6 46 113 6 54 124

7 45 251 7 53 262

1 56 130 1 59 282

2 58 137 2 57 275

3 57 275 3 58 137

4 63 280 4 60 128

5 60 128 5 63 280

6 62 135 6 61 273

7 61 273 7 62 135

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

5

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Table 5: Component-to-Module DQ Map (Continued)

DQ Map

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

U13 0 48 119 U14 0 40 108

1 51 271 1 43 260

2 49 264 2 41 253

3 50 126 3 42 115

4 52 117 4 44 106

5 55 269 5 47 258

6 53 262 6 45 251

7 54 124 7 46 113

U15 0 32 97 U16 0 CB0 49

1 35 249 1 CB3 201

2 33 242 2 CB1 194

3 34 104 3 CB2 56

4 36 95 4 CB4 47

5 39 247 5 CB7 199

6 37 240 6 CB5 192

7 38 102 7 CB6 54

U17 0 24 38 U18 0 16 27

1 27 190 1 19 179

2 25 183 2 17 172

3 26 45 3 18 34

4 28 36 4 20 25

5 31 188 5 23 177

6 29 181 6 21 170

7 30 43 7 22 32

U19 0 8 16 U20 0 0 5

1 11 168 1 3 157

2 9 161 2 1 150

3 10 23 3 2 12

4 12 14 4 4 3

5 15 166 5 7 155

6 13 159 6 5 148

7 14 21 7 6 10

Module Pin

Number

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

6

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Functional Block Diagram

DQ DQ DQ DQ DQ DQ DQ DQ ZQ

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

U2

DQ DQ DQ DQ DQ DQ DQ DQ

U20

DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39

U8

DQ DQ DQ DQ DQ DQ DQ DQ

U15

DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

U3

DQ DQ DQ DQ DQ DQ DQ DQ

U19

DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

U9

DQ DQ DQ DQ DQ DQ DQ DQ

U14

DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23

U4

DQ DQ DQ DQ DQ DQ DQ DQ

U18

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55

U10

DQ DQ DQ DQ DQ DQ DQ DQ

U13

DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

U5

DQ DQ DQ DQ DQ DQ DQ DQ

U17

DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

U11

DQ DQ DQ DQ DQ DQ DQ DQ

U12

CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7

U6

DQ DQ DQ DQ DQ DQ DQ DQ

U16

DQ DQ DQ DQ DQ DQ DQ DQ ZQ

CS1_n CS0_n

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

ZQ

Vss

DM_n/ CS_n DQS_t DQS_c

DBI_n

DQS0_t DQS0_c

DBI0_n/DM0_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DM_n/ CS_n DQS_t DQS_c

DBI_n

DQS1_t DQS1_c

DBI1_n/DM1_n

DQS2_t

DQS2_c

DBI2_n/DM2_n

DQS3_t

DQS3_c

DBI3_n/DM3_n

DQS8_t DQS8_c

DBI8_n/DM8_n

DQS4_t DQS4_c

DBI4_n/DM4_n

DQS5_t DQS5_c

DBI5_n/DM5_n

DQS6_t DQS6_c

DBI6_n/DM6_n

DQS7_t

DQS7_c

DBI7_n/DM7_n

U7

A/B-CS_n[1:0], A/B-BA[1:0]A/B-BG[1:0],

A/B-ACT_n, A/B-A[17, 13:0], A/B-RAS_n/A16,

A/B-CAS_n/A15, A/B-WE_n/A14,

A/B-PAR, A/B-CKE[1:0], A/B-ODT[1:0]

CK[3:0]_t CK[3:0]_c

Command, control, address, and clock line terminations:

DDR4

SDRAM

VTT

DDR4

SDRAM

VDD

U1

A0

SPD EEPROM/ Temperature

sensor

A1 A2

SA0

SA1

SDA

SCL

EVT

EVENT#

SA2

Rank 0: U2–U6, U8–U11 Rank 1: U12–U20

CKNC_t CKNC_c

Vss

VREFCA

VSS

DDR4 SDRAM, Register

VDD

Control, command and address termination

VDDSPD

SPD EEPROM/Temp Sensor, Register

VTT

DDR4 SDRAM, Register

DDR4 SDRAM

VPP

CS0_n

CS1_n BA[1:0] BG[1:0]

ACT_n A[17, 13:0] RAS_n/A16 CAS_n/A15

WE_n/A14

CKE0

CKE1 ODT0 ODT1

PAR_IN

ALERT_CONN

A/BCS0_n: Rank 0 A/BCS1_n: Rank 1 A/BBA[1:0]: DDR4 SDRAM A/BBG[1:0]: DDR4 SDRAM A/BACT_n: DDR4 SDRAM A/BA[17,13:0]: DDR4 SDRAM A/B-RAS_n/A16: DDR4 SDRAM A/B-CAS_n/A15: DDR4 SDRAM A/B-WE_n/A14: DDR4 SDRAM A/BCKE0: Rank 0 A/BCKE1: Rank 1 A/BODT0: Rank 0 A/BODT1: Rank 1 A/BPAR: DDR4 SDRAM ALERT_DRAM: DDR4 SDRAM

R

E

G

I

S

T

E

R

&

P

L

RESET_CONN

CK_t CK_c

CK[1:0]_c

DDR4 SDRAM

RESET_DRAM: DDR4 SDRAM

CK[1:0]_t

ZQ

VSS

SA0 SA1 SA2

SCL

SDA

Figure 2: Functional Block Diagram

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Note:

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Functional Block Diagram

1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver.

7

Micron Technology, Inc. reserves the right to change products or specifications without notice.

General Description

High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins.

DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

Fly-By Topology

DDR4 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR4.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

General Description

Module Manufacturing Location

Micron Technology manufactures modules at sites world-wide. Customers may receive modules from any of the following manufacturing locations:

Table 6: DRAM Module Manufacturing Locations

Manufacturing Site Location Country of Origin Specified on Label

Boise, USA USA

Aguadilla, Puerto Rico Puerto Rico

Xian, China China

Singapore Singapore

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

8

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Address Mapping to DRAM

Address Mirroring

To achieve optimum routing of the address bus on DDR4 multi rank modules, the address bus will be wired as shown in the table below, or mirrored. For quad rank modules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted address pins have no secondary functions allowing for normal operation when crosswired. Data is still read from the same address it was written. However, Load Mode operations require a specific address. This requires the controller to accommodate for a rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more details.

Table 7: Address Mirroring

Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored

A0 A0 A0

A1 A1 A1

A2 A2 A2

A3 A3 A4

A4 A4 A3

A5 A5 A6

A6 A6 A5

A7 A7 A8

A8 A8 A7

A9 A9 A9

A10 A10 A10

A11 A11 A13

A13 A13 A11

A12 A12 A12

A14 A14 A14

A15 A15 A15

A16 A16 A16

A17 A17 A17

BA0 BA0 BA1

BA1 BA1 BA0

BG0 BG0 BG1

BG1 BG1 BG0

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Address Mapping to DRAM

Registering Clock Driver Operation

Registered DDR4 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD01 Specification.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

9

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Control Words

Parity Operations

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Registering Clock Driver Operation

To reduce the electrical load on the host memory controller's command, address, and control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD presents a single load to the controller while redriving signals to the DDR4 SDRAM devices, which helps enable higher densities and increase signal integrity. The RCD also provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple differential pairs of clock outputs.

The RCD device(s) used on DDR4 RDIMMs and LRDIMMs contain configuration registers known as control words, which the host uses to configure the RCD based on criteria determined by the module design. Control words can be set by the host controller through either the DRAM address and control bus or the I2C bus interface. The RCD I2C bus interface resides on the same I2C bus interface as the module temperature sensor and EEPROM.

The RCD includes a parity-checking function that can be enabled or disabled in control word RC0E. The RCD receives a parity bit at the DPAR input from the memory controller and compares it with the data received on the qualified command and address inputs; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If parity checking is enabled, the RCD forwards commands to the SDRAM when no parity error has occurred. If the parity error function is disabled, the RCD forwards sampled commands to the SDRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled.

Rank Addressing

The chip select pins (CS_n) on Micron's modules are used to select a specific rank of DRAM. The RDIMM is capable of selecting ranks in one of three different operating modes, dependant on setting DA[1:0] bits in the DIMM configuration control word located within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules. For quad-rank modules, either direct or encoded QuadCS mode is used.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

10

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Temperature Sensor With SPD EEPROM Operation

Thermal Sensor Operations

The integrated thermal sensor continuously monitors the temperature of the module PCB directly below the device and updates the temperature data register. Temperature data may be read from the bus host at any time, which provides the host real-time feedback of the module's temperature. Multiple programmable and read-only temperature registers can be used to create a custom temperature-sensing solution based on system requirements and JEDEC JC-42.2.

EVENT_n Pin

The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pullup to V can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial presence-detect (SPD) EEPROM.

EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to the clear event bit in the status register. In comparator mode, the EVENT_n pin clears itself when the error condition is removed. Comparator mode is always used when the temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n pin is only asserted if the measured temperature exceeds the TCRIT limit; it then remains asserted until the temperature drops below the TCRIT limit minus the TCRIT hysteresis.

. EVENT_n is a temperature sensor output used to flag critical events that

DDSPD

SPD EEPROM Operation

DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable blocks. The SPD content is aligned with these blocks as shown in the table below.

Block Range Description

0 0–127 000h–07Fh Configuration and DRAM parameters

1 128–255 080h–0FFh Module parameters

2 256–319 100h–13Fh Reserved (all bytes coded as 00h)

320–383 140h–17Fh Manufacturing information

3 384–511 180h–1FFh End-user programmable

The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining 128 bytes of storage are available for use by the customer.

The EEPROM resides on a two-wire I2C serial interface and is not integrated with the memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achievable at 2.5V (NOM).

Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently programmed or corrupted. The upper 128 bytes remain available for customer use and are unprotected.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

11

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.

Table 8: Absolute Maximum Ratings

Symbol Parameter Min Max Units Notes

V

DDQ

V

VIN, V

Table 9: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

V

REFCA(DC)

I

VTT

V

I

I/O

I

OZpd

I

OZpu

I

VREFCAVREFCA

VDD supply voltage relative to V

DD

V

supply voltage relative to V

DDQ

Voltage on VPP pin relative to V

PP

Voltage on any pin relative to V

OUT

VDD supply voltage 1.14 1.20 1.26 V 1

DD

DRAM activating power supply 2.375 2.5 2.75 V 2

PP

Input reference voltage –

SS

0.49 × V

–0.4 1.5 V 1

–0.4 3.0 V 2

–0.4 1.5 V

DD

0.5 × V

DD

0.51 × V

DD

command/address bus

Termination reference current from V

Termination reference voltage (DC) –

TT

command/address bus

I

Input leakage current; any input excluding ZQ; 0V <

I

TT

–750 – 750 mA

0.49 × VDD 20mV

0.5 × VDD0.51 × VDD + 20mV

– – – µA 5

VIN < 1.1V

I

Input leakage current; ZQ –3 – 3 µA 6, 7

I

DQ leakage; 0V < VIN < V

Output leakage current; V

DD

= VDD; DQ is disabled – – 5 µA

OUT

= VSS; DQ and ODT

OUT

–4 – 4 µA 7

– – 50 µA

are disabled; ODT is disabled with ODT input HIGH

leakage; V

= VDD/2 (after DRAM is ini-

REFCA

–2 – 2 µA 7

tialized)

V 3

V 4

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Notes:

1. V

balls on DRAM are tied to VDD.

DDQ

2. VPP must be greater than or equal to VDD at all times.

3. V

must not be greater than 0.6 × VDD. When VDD is less than 500mV, V

REFCA

may be

REF

less than or equal to 300mV.

4. VTT termination voltages in excess of specification limit adversely affect command and address signals' voltage margins and reduce timing margins.

5. Command and address inputs are terminated to VDD/2 in the registering clock driver. Input current is dependent on termination resistance set in the registering clock driver.

6. Tied to ground. Not connected to edge connector.

7. Multiply by number of DRAM die on module.

12

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Electrical Specifications

Table 10: Thermal Characteristics

Symbol Parameter/Condition Value Units Notes

T

C

T

C

T

OPER

T

OPER

T

STG

RH

STG

NA Change Rate of Storage Temperature 20 °C/hour

Commercial operating case temperature 0 to 85 °C 1, 2, 3

>85 to 95 °C 1, 2, 3, 4

Normal operating temperature range 0 to 85 °C 5, 7

Extended temperature operating range (optional) >85 to 95 °C 5, 7

Non-operating storage temperature –55 to 100 °C 6

Non-operating Storage Relative Humidity (non-condensing) 5 to 95 %

Notes:

1. Maximum operating case temperature; TC is measured in the center of the package.

2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation.

3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.

4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs interval refresh rate.

5. The refresh rate must double when 85°C < T

OPER

≤ 95°C.

6. Storage temperature is defined as the temperature of the top/center of the DRAM and does not reflect the storage temperatures of shipping trays.

7. For additional information, refer to technical note TN-00-08: "Thermal Applications" available at micron.com.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR4 component data sheets. Component specifications are available at micron.com. Module speed grades correlate with component speed grades, as shown below.

Table 11: Module and Component Speed Grades

DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-2G6 -075

-2G4 -083E

-2G3 -083

-2G1 -093E

-1G9 -107E

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the edge connector of the module, not at the DRAM. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

IDD Specifications

Table 12: DDR4 IDD Specifications and Conditions – 16GB (Die Revision A)

Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) component data sheet

Parameter Symbol 2400 Units

One bank ACTIVATE-PRECHARGE current I

One bank ACTIVATE-PRECHARGE, wordline boost, IPP current I

One bank ACTIVATE-READ-PRECHARGE current I

Precharge standby current I

Precharge standby ODT current I

Precharge power-down current I

Precharge quite standby current I

Active standby current I

Active standby IPP current I

Active power-down current I

Burst read current I

Burst read I

current I

DDQ

Burst write current I

Burst refresh current (1x REF) I

Burst refresh IPP current (1x REF) I

Self refresh current: Normal temperature range (0°C to 85°C) I

Self refresh current: Extended temperature range (0°C to 95°C) I

Self refresh current: Reduced temperature range (0°C to 45°C) I

Auto self refresh current (25°C) I

Auto self refresh current (45°C) I

Auto self refresh current (75°C) I

Bank interleave read current I

Bank interleave read IPP current I

Maximum power-down current I

DD0

PP0

DD1

DD2N

DD2NT

DD2P

DD2Q

DD3N

PP3N

DD3P

DD4R

DDQ4R

DD4W

DD5B

PP5B

DD6N

DD6E

DD6R

DD6A

DD7

PP7

DD8

1

2

1

2

1

2

1

2

810 mA

54 mA

945 mA

900 mA

810 mA

540 mA

810 mA

990 mA

54 mA

720 mA

1620 mA

855 mA

1710 mA

2295 mA

297 mA

540 mA

630 mA

450 mA

360 mA

450 mA

630 mA

2115 mA

162 mA

360 mA

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Notes:

1. One module rank in the active I

2. All ranks in this I

DD/PP

condition.

15

, the other rank in I

DD/PP

Micron Technology, Inc. reserves the right to change products or specifications without notice.

DD2P/PP3N

.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

IDD Specifications

Table 13: DDR4 IDD Specifications and Conditions – 16GB (Die Revision B)

Values are for the MT40A1G8 DDR4 SDRAM only and are computed from values specified in the 8Gb (1 Gig x 8) component data sheet

Parameter Symbol 2666 2400 Units

One bank ACTIVATE-PRECHARGE current I

One bank ACTIVATE-PRECHARGE, wordline boost, IPP current I

One bank ACTIVATE-READ-PRECHARGE current I

Precharge standby current I

Precharge standby ODT current I

Precharge power-down current I

Precharge quite standby current I

Active standby current I

Active standby IPP current I

Active power-down current I

Burst read current I

Burst read I

current I

DDQ

Burst write current I

Burst refresh current (1x REF) I

Burst refresh IPP current (1x REF) I

Self refresh current: Normal temperature range (0°C to 85°C) I

Self refresh current: Extended temperature range (0°C to 95°C) I

Self refresh current: Reduced temperature range (0°C to 45°C) I

Auto self refresh current (25°C) I

Auto self refresh current (45°C) I

Auto self refresh current (75°C) I

Bank interleave read current I

Bank interleave read IPP current I

Maximum power-down current I

DD0

PP0

DD1

DD2N

DD2NT

DD2P

DD2Q

DD3N

PP3N

DD3P

DD4R

DDQ4R

DD4W

DD5B

PP5B

DD6N

DD6E

DD6R

DD6A

DD7

PP7

DD8

1

2

1

2

1

2

1

2

684 657 mA

54 54 mA

792 765 mA

630 612 mA

675 675 mA

450 450 mA

540 540 mA

828 774 mA

54 54 mA

702 666 mA

1530 1440 mA

855 855 mA

1404 1332 mA

2475 2475 mA

279 279 mA

540 540 mA

630 630 mA

360 360 mA

144 144 mA

360 360 mA

540 540 mA

1845 1800 mA

162 162 mA

450 450 mA

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Notes:

1. One module rank in the active I

2. All ranks in this I

DD/PP

condition.

16

, the other rank in I

DD/PP

Micron Technology, Inc. reserves the right to change products or specifications without notice.

DD2P/PP3N

.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Registering Clock Driver Specifications

Table 14: Registering Clock Driver Electrical Characteristics

DDR4 RCD01 devices or equivalent

Parameter Symbol Pins Min Nom Max Units

DC supply voltage V

DC reference voltage V

DC termination voltage

High-level input

V

IH. CMOS

voltage

Low-level input

V

IL. CMOS

voltage

DRST_n pulse width

IT_Pow-

er_stable

AC high-level output

V

voltage

AC low-level output

V

voltage

AC differential out-

V

OHdiff(AC)

put high measurement level (for output slew rate)

AC differential out-

V

OLdiff(AC)

put low measurement level (for output slew rate)

DD

REF

V

TT

t

IN-

OH(AC)

OL(AC)

All outputs except

Yn_t - Yn_c, BCK_t -

– 1.14 1.2 1.26 V

V

REFCA

– V

DRST_n 0.65 × V

0.49 × V

REF

DD

- 40mV V

DD

0.5 × V

DD

REF

– V

0 – 0.35 × V

0.51 × V

V

REF

DD

+ 40mV V

DD

– 1.0 – – µs

VTT + (0.15 × VDD) – – V

ALERT_n

– – VTT + (0.15 x VDD) V

– 0.3 × V

DD

– mV

BCK_c

– –0.3 × V

DD

– mV

V

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

Note:

1. Timing and switching specifications for the register listed are critical for proper operation of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. See the JEDEC RCD01 specification for complete operating electrical characteristics. Registering clock driver parametric values are specified for device default control word settings, unless otherwise stated. The RC0A control word setting does not affect parametric values.

17

Micron Technology, Inc. reserves the right to change products or specifications without notice.

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Temperature Sensor With SPD EEPROM

The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the serial presence-detect (SPD) EEPROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete details.

SPD Data

For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.

Table 15: Temperature Sensor With SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Nom Max Units

Supply voltage V

DDSPD

Input low voltage: logic 0; all inputs V

Input high voltage: logic 1; all inputs V

Output low voltage: 3mA sink current V

Input leakage current: (SCL, SDA) VIN = V

Output leakage current: V

OUT

= V

DDSPD

> 2V V

DDSPD

or V

DDSPD

or V

SSSPD

, SDA in High-Z I

IL

IH

OL

I

LI

LO

– 2.5 – V

–0.5 – V

V

× 0.7 – V

DDSPD

– – 0.4 V

– – ±5 µA

× 0.3 V

+ 0.5 V

Table 16: Temperature Sensor and EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Clock frequency

Clock pulse width HIGH time

Clock pulse width LOW time

Detect clock LOW timeout

SDA rise time

SDA fall time

Data-in setup time

Data-in hold time

Data out hold time

Start condition setup time

Start condition hold time

Stop condition setup time

Time the bus must be free before a new transition can start

Write time

Warm power cycle time off

Time from power-on to first command

f

SCL 10 1000 kHz

t

HIGH 260 – ns

t

LOW 500 – ns

t

TIMEOUT 25 35 ms

t

R – 120 ns

t

F – 120 ns

t

SU:DAT 50 – ns

t

HD:DI 0 – ns

t

HD:DAT 0 350 ns

t

SU:STA 260 – ns

t

HD:STA 260 – ns

t

SU:STO 260 – ns

t

BUF 500 – ns

t

W – 5 ms

t

POFF 1 – ms

t

INIT 10 – ms

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

18

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Module Dimensions

31.40 (1.236)

31.10 (1.224)

2.50 (0.098) D (2X)

0.75 (0.03) R (8X)

Front view

133.48 (5.255)

133.22 (5.244)

Back view

1.5 (0.059)

1.3 (0.051)

3.9 (0.153) MAX

3.0 (0.118) (4X) TYP

9.5 (0.374) TYP

Pin 1

4.8 (0.189) TYP

5.95 (0.234) TYP

126.65 (4.99) TYP

0.85 (0.033) TYP

0.60 (0.0236) TYP

0.75 (0.030) R

64.6 (2.54) TYP

56.10 (2.21) TYP

Pin 288

Pin 145

2.20 (0.087) TYP

72.25 (2.84) TYP

0.5 (0.0197) TYP

28.9 (1.14) TYP

10.2 (0.4) TYP

25.5 (1.0) TYP

22.95 (0.9) TYP

10.2 (0.4) TYP

22.95 (0.90) TYP

3.35 (0.132) TYP (2X)

3.15 (0.124) TYP

14.6 (0.57) TYP

8.0 (0.315) TYP

16.1 (0.63) TYP

Pin 144

1.25 (0.049) x 45° (2X)

U2

U3

U4

U5

U6

U8

U9

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U7

U1

Figure 3: 288-Pin DDR4 RDIMM

16GB (x72, ECC, DR) 288-Pin DDR4 RDIMM

Module Dimensions

Notes:

1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

PDF: 09005aef862e760f asf18c2gx72pdz.pdf - Rev. C 2/16 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Micron MTA18ASF2G72PDZ – 16GB User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

DDR4 SDRAM RDIMM

Features

Pin Assignments

DQ Map

Functional Block Diagram

General Description

Fly-By Topology

Module Manufacturing Location

Address Mapping to DRAM

Address Mirroring

Registering Clock Driver Operation

Control Words

Parity Operations

Rank Addressing

Temperature Sensor With SPD EEPROM Operation

Thermal Sensor Operations

EVENT_n Pin

SPD EEPROM Operation

Electrical Specifications

DRAM Operating Conditions

Design Considerations

IDD Specifications

Registering Clock Driver Specifications

Temperature Sensor With SPD EEPROM

SPD Data

Module Dimensions