Micron MT8JSF12864HZ – 1GB, MT8JSF25664HZ – 2GB User Manual

Module height: 30mm (1.18in)
1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO-

DDR3 SDRAM SODIMM

MT8JSF12864HZ – 1GB MT8JSF25664HZ – 2GB
DIMM

Features

Features
• DDR3 functionality and operations supported as defined in the component data sheet
• 204-pin, small-outline dual in-line memory module (SODIMM)
• Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400
• 1GB (128 Meg x 64)
• 2GB (256 Meg x 64)
• VDD = 1.5V ±0.075V
• V
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Single rank
• On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
= +3.0V to +3.6V
DDSPD
Figure 1: 204-Pin SODIMM (MO-268 R/C B)
Options Marking
• Operating temperature
– Commercial (0°C TA +70°C) None – Industrial (–40°C TA +85°C) I
• Package – 204-pin DIMM (halogen-free) Z
• Frequency/CAS latency – 1.25ns @ CL = 11 (DDR3-1600) -1G6 – 1.5ns @ CL = 9 (DDR3-1333) -1G4 – 1.87ns @ CL = 7 (DDR3-1066) -1G1
Note:
1. Contact Micron for industrial temperature module offerings.
1
Table 1: Key Timing Parameters
Speed Grade
-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125
-1G4 PC3-10600 1333 1333 1066 1066 800 667 13.125 13.125 49.125
-1G1 PC3-8500 1066 1066 800 667 13.125 13.125 50.625
-1G0 PC3-8500 1066 800 667 15 15 52.5
-80B PC3-6400 800 667 15 15 52.5
PDF: 09005aef83364a85 jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
Nomenclature
Industry
Products and specifications discussed herein are subject to change by Micron without notice.
Data Rate (MT/s) t
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
RCD
(ns)
t
RP
(ns)
t
RC
(ns)CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5
1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO-
Table 2: Addressing
Parameter 1GB 2GB
Refresh count 8K 8K
Row address 16K A[13:0] 32K A[14:0]
Device bank address 8 BA[2:0] 8 BA[2:0]
Device configuration 1Gb (128 Meg x 8) 2Gb (256 Meg x 8)
Column address 1K A[9:0] 1K A[9:0]
Module rank address 1 S0# 1 S0#
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,1 1Gb DDR3 SDRAM
Part Number
2
Density Configuration
MT8JSF12864H(I)Z-1G6__ 1GB 128 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT8JSF12864H(I)Z-1G4__ 1GB 128 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT8JSF12864H(I)Z-1G1__ 1GB 128 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
Module
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
DIMM
Features
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,1 2Gb DDR3 SDRAM
Part Number
22
Density Configuration
MT8JSF25664H(I)Z-1G6__ 2GB 256 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT8JSF25664H(I)Z-1G4__ 2GB 256 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT8JSF25664H(I)Z-1G1__ 2GB 256 Meg x 64 8.5 GB/s 1.87ns/1066 MT/s 7-7-7
Module
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT8JSF12864HZ-1G1D1.
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
PDF: 09005aef83364a85 jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO-
DIMM

Pin Assignments

Pin Assignments
Table 5: Pin Assignments
204-Pin DDR3 SODIMM Front 204-Pin DDR3 SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 V
REFDQ
3 V
5 DQ0 57 DQ24 109 BA0 161 V
7 DQ1 59 DQ25 111 V
9 V
11 DM0 63 DM3 115 CAS# 167 V
13 V
15 DQ2 67 DQ26 119 A13 171 DQS6 16 DQ6 68 DQ30 120 NC 172 V
17 DQ3 69 DQ27 121 NC 173 V
19 V
21 DQ8 73 CKE0 125 NC 177 DQ51 22 DQ12 74 NC 126 V
23 DQ9 75 V
25 V
27 DQS1# 79 BA2 131 DQ33 183 DQ57 28 DM1 80 NF/A14 132 DQ37 184 V
29 DQS1 81 V
31 V
33 DQ10 85 A9 137 DQS4 189 V
35 DQ11 87 V
37 V
39 DQ16 91 A5 143 DQ35 195 V
41 DQ17 93 V
43 V
45 DQS2# 97 A1 149 DQ41 201 SA1 46 DM2 98 A0 150 V
47 DQS2 99 V
49 V
51 DQ18 103 CK0# 155 V
53 DQ19 105 V
55 V
SS
61 V
SS
65 V
SS
71 V
SS
77 NC 129 DQ32 181 DQ56 26 V
SS
83 A12 135 DQS4# 187 DM7 32 V
SS
89 A8 141 DQ34 193 DQ59 38 V
SS
95 A3 147 DQ40 199 V
SS
101 CK0 153 DM5 50 DQ22 102 CK1 154 DQS5
SS
107 A10 159 DQ43 4 DQ4 56 DQ28 108 BA1 160 DQ47
SS
113 WE# 165 DQ49 10 DQS0# 62 DQ3# 114 S0# 166 DQ53
SS
117 V
SS
123 V
SS
127 V
DD
133 V
DD
139 V
DD
145 V
DD
151 V
DD
157 DQ42 2 V
DD
SS
163 DQ48 8 V
DD
SS
169 DQS6# 14 V
DD
SS
175 DQ50 20 V
DD
179 V
SS
185 V
SS
191 DQ58 36 DQ15 88 V
SS
197 SA0 42 DQ21 94 V
SS
203 V
SS
SS
52 DQ23 104 CK1# 156 V
SS
SS
SS
SS
DDSPD
TT
6 DQ5 58 DQ29 110 RAS# 162 V
12 DQS0 64 DQ3 116 ODT0 168 V
18 DQ7 70 DQ31 122 NC 174 DQ54
24 DQ13 76 V
30 RESET# 82 V
34 DQ14 86 A7 138 V
40 DQ20 92 A4 144 V
44 V
48 V
SS
SS
SS
SS
SS
SS
SS
SS
SS
54 V
60 V
66 V
72 V
SS
SS
SS
SS
DD
106 V
112 V
118 V
124 V
128 V
DD
DD
DD
DD
REFCA
SS
78 NC 130 DQ36 182 DQ61
134 V
DD
SS
84 A11 136 DM4 188 DQS7
SS
140 DQ38 192 DQ62
DD
90 A6 142 DQ39 194 DQ63
SS
146 DQ44 198 EVENT#
DD
96 A2 148 DQ45 200 SDA
SS
100 V
152 DQS5# 204 V
DD
SS
158 DQ46
164 DQ52
170 DM6
176 DQ55
178 V
180 DQ60
186 DQS7#
190 V
196 V
202 SCL
SS
SS
SS
SS
SS
SS
SS
TT
PDF: 09005aef83364a85 jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO-
DIMM

Pin Descriptions

Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module.
Table 6: Pin Descriptions
Symbol Type Description
Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
RESET# Input
Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
CBx I/O Check bits: Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx,
DQSx#
Input Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
try and clocks on the DRAM.
is masked when DM is sampled HIGH, along with that input data, during a write ac­cess. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
entered.
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
(LVCMOS)
I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial­ized as though a normal power-up was executed.
decoder.
dress range on the I2C bus.
cation to and from the temperature sensor/SPD EEPROM on the I2C bus.
read data; input with write data; center-aligned with write data.
PDF: 09005aef83364a85 jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin Halogen-Free DDR3 SDRAM SO-
Table 6: Pin Descriptions (Continued)
Symbol Type Description
SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sen-
sor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Err_Out# Output
EVENT# Output
V
DD
V
DDSPD
V
REFCA
V
REFDQ
V
SS
V
TT
NC No connect: These pins are not connected on the module.
NF No function: These pins are connected within the module, but provide no functional-
Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function.
Parity error output: Parity error found on the command and address bus.
(open drain)
Temperature event:The EVENT# pin is asserted by the temperature sensor when criti-
(open drain)
cal temperature thresholds have been exceeded.
Supply Power supply: 1.5V ±0.075V. The component VDD and V
module VDD.
Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
Supply Reference voltage: Control, command, and address VDD/2.
Supply Reference voltage: DQ, DM VDD/2.
Supply Ground.
Supply Termination voltage: Used for control, command, and address VDD/2.
ity.
Pin Descriptions
are connected to the
DDQ
DIMM
PDF: 09005aef83364a85 jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
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