Device configuration1Gb (128 Meg x 8)2Gb (256 Meg x 8)
Column address1K A[9:0]1K A[9:0]
Module rank address1 S0#1 S0#
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,1 1Gb DDR3 SDRAM
Part Number
2
DensityConfiguration
MT8JSF12864H(I)Z-1G6__1GB128 Meg x 6412.8 GB/s1.25ns/1600 MT/s11-11-11
MT8JSF12864H(I)Z-1G4__1GB128 Meg x 6410.6 GB/s1.5ns/1333 MT/s9-9-9
MT8JSF12864H(I)Z-1G1__1GB128 Meg x 648.5 GB/s1.87ns/1066 MT/s7-7-7
Module
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
DIMM
Features
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,1 2Gb DDR3 SDRAM
Part Number
22
DensityConfiguration
MT8JSF25664H(I)Z-1G6__2GB256 Meg x 6412.8 GB/s1.25ns/1600 MT/s11-11-11
MT8JSF25664H(I)Z-1G4__2GB256 Meg x 6410.6 GB/s1.5ns/1333 MT/s9-9-9
MT8JSF25664H(I)Z-1G1__2GB256 Meg x 648.5 GB/s1.87ns/1066 MT/s7-7-7
Module
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT8JSF12864HZ-1G1D1.
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
SymbolTypeDescription
AxInputAddress inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAxInputBank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
DMxInputData mask (x8 devices only): DM is an input mask signal for write data. Input data
ODTxInputOn-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
Par_InInputParity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#InputCommand inputs: RAS#, CAS#, and WE# (along with S#) define the command being
RESET#Input
Sx#InputChip select: Enables (registered LOW) and disables (registered HIGH) the command
SAxInputSerial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
SCLInputSerial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
CBxI/OCheck bits: Used for system error detection and correction.
DQxI/OData input/output: Bidirectional data bus.
DQSx,
DQSx#
InputClock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
try and clocks on the DRAM.
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
entered.
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
(LVCMOS)
I/OData strobe: Differential data strobes. Output with read data; edge-aligned with
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
decoder.
dress range on the I2C bus.
cation to and from the temperature sensor/SPD EEPROM on the I2C bus.
read data; input with write data; center-aligned with write data.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
SDAI/OSerial data: Used to transfer addresses and data into and out of the temperature sen-
sor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Err_Out#Output
EVENT#Output
V
DD
V
DDSPD
V
REFCA
V
REFDQ
V
SS
V
TT
NC–No connect: These pins are not connected on the module.
NF–No function: These pins are connected within the module, but provide no functional-
OutputRedundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Parity error output: Parity error found on the command and address bus.
(open drain)
Temperature event:The EVENT# pin is asserted by the temperature sensor when criti-
(open drain)
cal temperature thresholds have been exceeded.
SupplyPower supply: 1.5V ±0.075V. The component VDD and V
module VDD.
SupplyTemperature sensor/SPD EEPROM power supply: 3.0–3.6V.
SupplyReference voltage: Control, command, and address VDD/2.
SupplyReference voltage: DQ, DM VDD/2.
SupplyGround.
SupplyTermination voltage: Used for control, command, and address VDD/2.
ity.
Pin Descriptions
are connected to the
DDQ
DIMM
PDF: 09005aef83364a85
jsf8c128_256x64hz.pdf - Rev. E 04/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.