MICRON MT4LC8M8P4TG-6S, MT4LC8M8P4TG-5S, MT4LC8M8P4TG-5, MT4LC8M8P4DJ-5, MT4LC8M8P4DJ-5S Datasheet

1

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

8 MEG x 8 EDO DRAM PART NUMBERS

REFRESH

PART NUMBER ADDRESSING PACKAGE REFRESH

MT4LC8M8C2DJ-x 4K SOJ Standard
MT4LC8M8C2DJ-x S 4K SOJ Self
MT4LC8M8C2TG-x 4K TSOP Standard
MT4LC8M8C2TG-x S 4K TSOP Self
MT4LC8M8P4DJ-x 8K SOJ Standard
MT4LC8M8P4DJ-x S 8K SOJ Self
MT4LC8M8P4TG-x 8K TSOP Standard
MT4LC8M8P4TG-x S 8K TSOP Self

x = speed

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x8 pinout, timing, functions,
and packages

• 12 row, 11 column addresses (C2) or
13 row, 10 column addresses (P4)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL­compatible

• Extended Data-Out (EDO) PAGE MODE access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms

• Optional self refresh (S) for low-power data
retention

OPTIONS MARKING

• Refresh Addressing
4,096 (4K) rows C2
8,192 (8K) rows P4

• Plastic Packages
32-pin SOJ (400 mil) DJ
32-pin TSOP (400 mil) TG

• Timing
50ns access -5
60ns access -6

• Refresh Rates
Standard Refresh (64ms period) None
Self Refresh (128ms period) S*

NOTE: 1. The 8 Meg x 8 EDO DRAM base number

differentiates the offerings in one place—
MT4LC8M8C2. The fifth field distinguishes the
address offerings: C2 designates 4K addresses and
P4 designates 8K addresses.

2. The “#” symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC8M8C2DJ-5

DRAM

MT4LC8M8P4, MT4LC8M8C2

For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html

PIN ASSIGNMENT (Top View)

KEY TIMING PARAMETERS

SPEEDtRCtRACtPC

t

AAtCACtCAS

-5 84ns 50ns 20ns 25ns 13ns 8ns

-6 104ns 60ns 25ns 30ns 15ns 10ns

**NC on C2 version and A12 on P4 version

32-Pin SOJ 32-Pin TSOP

V

CC

DQ0
DQ1
DQ2
DQ3

NC

V

CC

WE#

RAS#

A0
A1
A2
A3
A4
A5

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

SS

DQ7
DQ6
DQ5
DQ4

Vss
CAS#
OE#
NC

/A12**

A11
A10
A9
A8
A7
A6

V

SS

VCC

DQ0
DQ1
DQ2
DQ3

NC

V

CC

WE#

RAS#

A0
A1
A2
A3
A4
A5

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

V

SS

DQ7
DQ6
DQ5
DQ4

V

SS

CAS#
OE#
NC/A12**

A11
A10
A9
A8
A7
A6

V

SS

GENERAL DESCRIPTION

The 8 Meg x 8 DRAM is a high-speed CMOS, dy­namic random-access memory devices containing
67,108,864 bits and designed to operate from 3V to

3.6V. The MT4LC8M8C2 and MT4LC8M8P4 are func­tionally organized as 8,388,608 locations containing
eight bits each. The 8,388,608 memory locations are
arranged in 4,096 rows by 2,048 columns on the C2
version and 8,192 rows by 1,024 columns on the P4
version. During READ or WRITE cycles, each location is

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8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

FUNCTIONAL BLOCK DIAGRAM

MT4LC8M8P4 (13 row addresses)

A0-

A12

RAS#

13

13

10

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

V

DD

V

SS

13

WE#

CAS#

10

CONTROL

LOGIC

COLUMN­ADDRESS

BUFFER(10)

ROW-

ADDRESS

BUFFERS (13)

8,192

1,024

COLUMN

DECODER

OE#

DQ0­DQ7

8

8

8

8

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

8,192 x 1,024 x 8

MEMORY

ARRAY

COMPLEMENT

SELECT

1,024 x 8

8,192 x 8

FUNCTIONAL BLOCK DIAGRAM

MT4LC8M8C2 (12 row addresses)

A0-

A11

RAS#

12

12

11

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

V

DD

V

SS

12

WE#

CAS#

11

CONTROL

LOGIC

COLUMN-

ADDRESS

BUFFER(11)

ROW-

ADDRESS

BUFFERS (12)

4,096

2,048

COLUMN

DECODER

OE#

DQ0­DQ7

8

8

8

8

REFRESH

COUNTER

ROW SELECT

ROW

DECODER

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN

BUFFER

4,096 x 2,048 x 8

MEMORY

ARRAY

COMPLEMENT

SELECT

2,048 x 8

4,096 x 8

3

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

uniquely addressed via the address bits. First, the row
address is latched by the RAS# signal, then the column
address is latched by CAS#. Both devices provide EDO­PAGE-MODE operation, allowing for fast successive
data operations (READ, WRITE, or READ-MODIFY­WRITE) within a given row.

The 8 Meg x 8 DRAM must be refreshed periodically

in order to retain stored data.

DRAM ACCESS

Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. The data for
each location is accessed via the eight I/O pins (DQ0­DQ7). A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE occurs
when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply­ing input data. If a LATE WRITE or READ-MODIFY­WRITE is attempted while keeping OE# LOW, no write
will occur, and the data outputs will drive read data
from the accessed location.

Figure 1

OE# CONTROL of DQs

EDO PAGE MODE

DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 8 Meg x 8
DRAM offers an accelerated page mode cycle by elimi­nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (tCP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms in the noted
appendix).

EDO operates like any DRAM READ or FAST-PAGE­MODE READ, except data is held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. OE# can be brought LOW or HIGH
while CAS# and RAS# are LOW, and the DQs will
transition between valid data and High-Z. Using OE#,
there are two methods to disable the outputs and keep
them disabled during the CAS# HIGH time. The first
method is to have OE# HIGH when CAS# transitions
HIGH and keep OE# HIGH for tOEHC thereafter. This
will disable the DQs, and they will remain disabled
(regardless of the state of OE# after that point) until
CAS# falls again. The second method is to have OE#
LOW when CAS# transitions HIGH and then bring OE#
HIGH for a minimum of tOEP anytime during the CAS#
HIGH period. This will disable the DQs, and they will
remain disabled (regardless of the state of OE# after that
point) until CAS# falls again (see Figure 1). During

V
V

IH
IL

CAS#

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

ROW COLUMN (A)

COLUMN (B)

DON’T CARE

UNDEFINED

V
V

IH
IL

OE#

V
V

IOH
IOL

OPEN

DQ

t

OD

VALID DATA (B)

VALID DATA (A)

COLUMN (C)

VALID DATA (A)

t

OE

VALID DATA (C)

COLUMN (D)

VALID DATA (D)

t

OD

t

OEHC

t

OD

t

OEP

t

OES

The DQs go back to
Low-Z if

t

OES is met.

The DQs remain High-Z
until the next CAS# cycle
if

t

OEHC is met.

The DQs remain High-Z
until the next CAS# cycle
if

t

OEP is met.

GENERAL DESCRIPTION (continued)

4

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

covers all rows. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address­ing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method, some
compatibility issues may become apparent. For ex­ample, both C2 and P4 versions require 4,096 CBR
REFRESH cycles, yet each requires a different number of
RAS#-ONLY REFRESH cycles (C2 = 4,096 and P4 =
8,192). JEDEC strongly recommends the use of CBR
REFRESH for this device.

An optional self refresh mode is also available on the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified tRASS. The “S” option allows for
an extended period of 128ms, or 31.25µs per row for a
4K refresh and 15.625µs per row for an 8K refresh, when
using a distributed CBR REFRESH. This refresh rate can
be applied during normal operation, as well as during
a standby or battery backup mode.

The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM
controller utilizes a RAS#-ONLY or burst CBR refresh
sequence, all 1,024 rows must be refreshed using a
minimum tRC refresh rate prior to resuming normal
operation.

EDO PAGE MODE (continued)

other cycles, the outputs are disabled at tOFF time after
RAS# and CAS# are HIGH or at tWHZ after WE# transi­tions LOW. The tOFF time is referenced from the rising
edge of RAS# or CAS#, whichever occurs last. WE# can
also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.

EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#,
just like for single location accesses. However, subse­quent column locations within the row may then be
accessed at the page mode cycle time. This is accom­plished by cycling CAS# while holding RAS# LOW and
entering new column addresses with each CAS# cycle.
Returning RAS# HIGH terminates the EDO-PAGE-MODE
operation.

DRAM REFRESH

The supply voltage must be maintained at the speci­fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (P4)
or all 4,096 rows (C2) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC8M8P4 in­ternally refreshes two rows for every CBR cycle, whereas
the MT4LC8M8C2 refreshes one row for every CBR
cycle. So with either device, executing 4,096 CBR cycles

V
V

IH
IL

CAS#

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

ROW COLUMN (A)

DON’T CARE

UNDEFINED

V
V

IH
IL

WE#

V
V

IOH
IOL

OPEN

DQ

t

WPZ

The DQs go to High-Z if WE# falls and, if tWPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).

V
V

IH
IL

OE#

VALID DATA (B)

t

WHZ

WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).

t

WHZ

COLUMN (D)

VALID DATA (A)

COLUMN (B)

COLUMN (C)

INPUT DATA (C)

Figure 2

WE# CONTROL of DQs

5

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................ -1V to +4.6V

Voltage on NC, Inputs or I/O Pins

Relative to VSS ....................................... -1V to +4.6V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Note: 1) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 V
INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2VCC + 0.3 V 26
INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26
INPUT LEAKAGE CURRENT:

Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 µA 27
All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:
IOUT = -2mA VOH 2.4–V

OUTPUT LOW VOLTAGE:
IOUT = 2mA VOL – 0.4 V

OUTPUT LEAKAGE CURRENT:
Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); IOZ -5 5 µA
DQ is disabled and in High-Z state

6

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

4K 8K

PARAMETER/CONDITION SYMBOL SPEED REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL ICC1 ALL 1 1 mA
(RAS# = CAS# = VIH)

STANDBY CURRENT: CMOS
(RAS# = CAS#  VCC - 0.2V; DQs may be left open; ICC2 ALL 500 500 µA
other inputs: VIN  VCC - 0.2V or VIN ≤ 0.2V)

OPERATING CURRENT: Random READ/WRITE ICC3 -5 175 135 mA 25
Average power supply current -6 165 125
(RAS#, CAS#, address cycling: tRC = tRC [MIN])

OPERATING CURRENT: EDO PAGE MODE ICC4 -5 155 155 mA 25
Average power supply current -6 125 125
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])

REFRESH CURRENT: RAS#-ONLY ICC5 -5 175 135 mA 22
Average power supply current -6 165 125
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])

REFRESH CURRENT: CBR ICC6 -5 165 165 mA 4, 7
Average power supply current -6 155 155
(RAS#, CAS#, address cycling: tRC = tRC [MIN])

REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or CBR ICC7 ALL 400 400 µA 4, 7
cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11,
OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open)

REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with ICC8 ALL 350 400 µA 4, 7
RAS#  tRASS (MIN) and CAS# held LOW; WE# =
VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)

7

8 Meg x 8 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D20_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

8 MEG x 8

EDO DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address

t

AA 25 30 ns

Column-address setup to CAS# precharge

t

ACH 12 15 ns

Column-address hold time (referenced to RAS#)

t

AR 38 45 ns

Column-address setup time

t

ASC 0 0 ns

Row-address setup time

t

ASR 0 0 ns

Column address to WE# delay time

t

AWD 42 49 ns 18

Access time from CAS#

t

CAC 13 15 ns

Column-address hold time

t

CAH 8 10 ns

CAS# pulse width

t

CAS 8 10,000 10 10,000 ns

CAS# LOW to “Don’t Care” during Self Refresh

t

CHD 15 15 ns

CAS# hold time (CBR Refresh)

t

CHR 8 10 ns 4

CAS# to output in Low-Z

t

CLZ 0 0 ns

Data output hold after CAS# LOW

t

COH 3 3 ns

CAS# precharge time

t

CP 8 10 ns 13

Access time from CAS# precharge

t

CPA 28 35 ns

CAS# to RAS# precharge time

t

CRP 5 5 ns

CAS# hold time

t

CSH 38 45 ns

CAS# setup time (CBR Refresh)

t

CSR 5 5 ns 4

CAS# to WE# delay time

t

CWD 28 35 ns 18

Write command to CAS# lead time

t

CWL 8 10 ns

Data-in hold time

t

DH 8 10 ns 19

Data-in setup time

t

DS 0 0 ns 19

Output disable

t

OD 0 12 0 15 ns 23, 24

Output enable time

t

OE 12 15 ns 20

OE# hold time from WE# during

t

OEH 8 10 ns 24

READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH

t

OEHC 5 10 ns

OE# HIGH pulse width

t

OEP 5 5 ns

OE# LOW to CAS# HIGH setup time

t

OES 4 5 ns

Output buffer turn-off delay

t

OFF 0 12 0 15 ns 17, 23

CAPACITANCE

(Note: 2)

PARAMETER SYMBOL MAX UNITS

Input Capacitance: Address pins CI1 5pF
Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF
Input/Output Capacitance: DQ CIO 7pF